Module 4 – Interfacing Chips

100003/CS500D
Microprocessors and Microcontrollers
Course Outcomes

● CO1: Illustrate the architecture, modes of operation and addressing modes of

microprocessors.
● CO2: Develop 8086 assembly language programs.
● CO3: Demonstrate interrupts, its handling and programming in 8086.
● CO4: Illustrate how different peripherals (8255,8254,8257) and memory
are interfaced with microprocessors.
● CO5: Outline features of microcontrollers and develop low level programs.
 ● Programmable Peripheral
Interface – 8255 PPI

● General purpose programmable I/O

device designed to interface the CPU
with its outside world such as ADC,
8255 DAC, keyboard etc.

● Can be programmed according to the

given condition.

● It can be used with almost any

microprocessor.
● The Intel 8255 Programmable Peripheral Interface (PPI) chip was developed and
manufactured by Intel in the first half of the 1970s for the microprocessors.

● The 8255 provides 24 parallel input/output lines with a variety of programmable

operating modes.

● It is available in a 40-pin DIP package.

● It found wide applicability in digital processing systems and was later cloned by
other manufacturers.

● The 82C55 is a CMOS version for higher speed and lower current consumption.

● 8255 consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C.

● These ports can be assigned as input or output functions.

PIN Diagram of 8255
Internal Architecture of 8255
● Consists of data bus buffer, control logic and Group A and Group B controls.

● Data Bus Buffer: This tri-state bi-directional buffer is used to interface the internal data lines
of 8255 to the system data bus.

● Input or Output instructions executed by the CPU either Read data from or Write data into the
buffer.

● Output data from the CPU to the ports or control register, and input data to the CPU from the
ports or status register are all passed through the buffer.

● Read/Write Control Logic: The control logic manages all the internal and external transfers of
both data and control words.

● RD/, WR/, A0, A1 and RESET are the inputs provided by the microprocessor.
● Group A and Group B Controls: Each of the Group A and Group B control blocks receives
control words from the CPU and issues appropriate commands to the ports associated with it.

● The Group A control block controls Port A and PC4-PC7 while the Group B control block
controls Port B and PC0-PC3.

● Port A: It can be programmed in three modes: mode 0, mode 1 and mode 2.

● Port B: It can be programmed in mode 0 and mode 1.

● Port C: Port C can be split into two parts and each can be used as control signals for ports A
and B in the handshake mode. It can be programmed for bit set/reset operation.
Modes of Operation of 8255
There are two basic operational modes of 8255:

● Bit Set-Reset mode (BSR mode).

● Input/Output mode (I/O mode).

● The two modes are selected on the basis of the value present at the D7 bit of the control word
register.

● When D7 = 1, 8255 operates in I/O mode, and when D7 = 0, it operates in the BSR mode.

● BSR mode and I/O mode are independent and selection of BSR mode does not affect the
operation of other ports in I/O mode.
Bit set/reset (BSR) mode
● The Bit Set/Reset (BSR) mode is applicable to port C only.

● Each line of port C (PC0 - PC7) can be set/reset by suitably loading the control word register.
● D7 bit is always 0 for BSR mode.

● Bits D6, D5 and D4 are don't care bits.

● Bits D3, D2 and D1 are used to select the pin of Port C.

D3 D2 D1 Bit/pin of Port C
0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7

● Bit D0 is used to set/reset the selected pin of Port C.

Input/Output (I/O) mode
● This mode is selected when D7 bit of the Control Word Register is 1. There are three I/O
modes.

● Mode 0 - Simple I/O

● Mode 1 - Strobed I/O
● Mode 2 - Strobed Bi-directional I/O
● Mode 0 – Simple or basic I/O Mode

● In this mode all of the ports A, B and C can be used as input or output mode.

● This mode has interrupt handling capability.

● Mode 1 - Strobed Input/output mode

● If port A or port B is to be used for handshake (strobed) input or output operation, then
initialize that port in mode 1.

● Port A and port B can be initialized to operate in different modes, i.e., for e.g., port A can
operate in mode 0 and port B in mode 1).

● Some of the pins of port C function as handshake lines before actual data transmission.
● For port B in this mode (irrespective of whether is acting as an input port or output port), PC0,
PC1 and PC2 pins function as handshake lines.

● If port A is initialized as mode 1 input port, then, PC3, PC4 and PC5 function as handshake
signals.

● Pins PC6 and PC7 are available for use as input/output lines.

● The mode 1 which supports handshaking has following features:

○ Two ports i.e. port A and B can be used as 8-bit i/o ports.

○ Each port uses three lines of port C as handshake signal and remaining two signals can be used as i/o
ports.

○ Interrupt logic is supported.

○ Input and Output data are latched.

● Mode 2 - Strobed Bidirectional Input/Output mode

● Only port A can be initialized in this mode.

● Port A can be used for bidirectional handshake data transfer.

● This means that data can be input or output on the same eight lines (PA0 - PA7).

● Pins PC3 - PC7 are used as handshake lines for port A.

● The remaining pins of port C (PC0 - PC2) can be used as input/output lines if group B is
initialized in mode 0 or as handshaking for port B if group B is initialized in mode 1.
● Programming in Mode 0:

● The Ports A, B and C can be configured as simple input or output ports by writing the
appropriate control word in the control word register.

● In the control word, D7 is set to ‘1’ and D6, D5 and D2 are all set to ‘0’ to configure all the ports
in Mode 0 operation.

● The status of bits D4, D3, D1 and D0 then determine whether the corresponding ports are to
be configured as Input or Output.

● For example in mode 0, if Port A and Port B are to operate as output ports with Port C lower as
input, and Port C upper as output, the control word that will have to be loaded into the control
register will be as follows.
● To communicate with peripherals through 8255 three steps are necessary:

● Determine the addresses of Port A, B, C and Control register according to Chip

Select Logic and the Address lines A0 and A1.

● Write a control word in control register.

● Write I/O instructions to communicate with peripherals through port A, B, C.
● The common applications of 8255 are:

○ Traffic light control

○ Generating square wave
○ Interfacing with DC motors and stepper motors
 ● Intel 8253 and 8254 are

Peripheral Chips for Programmable Interval Timers

(PTIs) designed for

Timing Control microprocessors to perform

timing and counting functions
using three 16-bit registers.
● It has 3 independent counters, each capable of handling clock inputs up to 10 MHz
and size of each counter is 16 bit.

● It operates in +5V regulated power supply and has 24 pin signals.

● All modes are software programmable.

● The 8254 is an advanced version of 8253

● Each counter has 2 input pins, i.e. Clock & Gate, and 1 pin for “OUT” output.
● Gate is used to enable or disable counting.

● To operate a counter, a 16-bit count is loaded in its register and gate is set.

● On command, it begins to decrement the count until it reaches 0, then it generates

a pulse that can be used to interrupt the CPU.

● Compatible with almost all microprocessors.

● 8254 has a powerful command called READ BACK command, which allows the user
to check the count value, the programmed mode, the current mode, and the
current status of the counter.
Differences between 8254 and 8253

8253 8254

Its operating frequency is 0 - 2.6 MHz Its operating frequency is 0 - 10 MHz

It uses N-MOS technology It uses H-MOS technology

Read-Back command is not available Read-Back command is available

Reads and writes of the same counter Reads and writes of the same counter can be
cannot be interleaved. interleaved.
8254 Architecture & PIN Diagram
● There are three counters, a data bus buffer, Read/Write control logic, and
a control register.

● Each counter has two input signals - CLOCK & GATE, and one output
signal - OUT.

● Data Bus Buffer

● It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the
8253/54 to the system data bus.

● It has three basic functions −

○ Programming the modes of 8253/54.
○ Loading the count registers.
○ Reading the count values.
● Read/Write Logic
● It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1.

● In the peripheral I/O mode, the RD and WR signals are connected to IOR
and IOW, respectively.

● In the memory mapped I/O mode, these are connected to MEMR and
MEMW.

● Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the
8253/54, and CS is tied to a decoded address.

● The control word register and counters are selected according to the
signals on lines A0 & A1.
CS RD WR A1 A0 Result

0 1 0 0 0 Write Counter 0

0 1 0 0 1 Write Counter 1

0 1 0 1 0 Write Counter 2

0 1 0 1 1 Write Control Word Register

0 0 1 0 0 Read Counter 0

0 0 1 0 1 Read Counter 1

0 0 1 1 0 Read Counter 2

0 0 1 1 1 No operation (Tristated)

0 1 1 X X No operation (Tristated)

1 X X X X 8254 Not Selected

● Counters

● Each counter consists of a single, 16 bit-down counter, which can be

operated in either binary or BCD.

● Its input and output is configured by the selection of modes stored in the
control word register.

● The programmer can read the contents of any of the three counters
without disturbing the actual count in process.
● Control Word Register

● This register is accessed when lines A0 & A1 are at logic 1.

● It is used to write a command word, which specifies the counter to be

used, its mode, and either a read or write operation.
Operating Modes of 8254
● Mode 0 (Interrupt on Terminal Count) – Mode 0 is typically used for
event counting.

● After the Control Word is written, OUT is initially low, and will remain low
until the counter reaches zero it is decremented by 1 after every clock
cycle.

● OUT then goes high and remains high until a new count or a new Mode 0
Control Word is written into the counter.

● GATE = 1 enables counting, GATE = 0 disables counting.

● Mode 1 (Hardware Retriggreable One Shot) – OUT will be initially high.

● OUT will go low on the CLK pulse following a trigger to begin the one-shot
pulse, and will remain low until the counter reaches zero.
● Mode 2 (Rate Generator) – Initially value of OUT is low. When counting is
enabled, it becomes high and this process repeats periodically.

● Value of count = Input Frequency / Output Frequency. This mode works as

a frequency divider.
● Mode 3 (Square Wave Generator) – Counting is enabled when GATE = 1
and disabled when GATE = 0.

● This mode is used to generate square waveform and time period (equal
to count) is generated.

● If N is count and is even then ontime of wave = N/2 and offtime = N/2

● If N is odd the ontime = (N + 1) / 2 and offtime = (N – 1) / 2

● Mode 4 (Software Triggered Strobe) – In this mode counting is enabled
by using GATE = 1 and disabled by GATE = 0.

● Initially value of OUT is high and becomes low when value of count is at
last stage. Count is reloaded again for subsequent clock pulse.
● Mode 5 (Hardware Triggered Strobe) – OUT will initially be high.

● Counting is triggered by a rising edge of GATE.

● When the initial count has expired, OUT will go low for one clock pulse
and then go high again.

● After writing the Control Word and initial count, the counter will not be
loaded until the clock pulse after a trigger.
 ● The Intel 8257 is a 4 channel
DMA (Direct Memory Access)
8257 Controller which requests the
CPU for bus access, on behalf
of the peripheral devices.
DMA – Direct Memory Access
● A direct memory access (DMA) is an operation in which data is copied
(transported) from one resource to another resource in a computer
system without the involvement of the CPU.

● DMA allows data to be sent directly from an attached device (such as a

disk drive) to the memory on the computer's motherboard.

● The microprocessor is freed from involvement with the data transfer, thus
speeding up overall computer operation.
8257-Introduction
● A DMAC is an independent (from CPU) resource of a computer system
added for the concurrent execution of DMA-operations.

● The DMAC replaces the CPU for the transfer task of data from the I/O-
device to the main memory (or vice versa) which otherwise would have
been executed by the CPU.

● The CPU initiates the transfer, does other operations while the transfer is
in progress and receives an interrupt from the DMA controller when the
operation is done.
Features of 8257

• It has four channels which can be used over four I/O devices.
• Each channel has 16-bit address and 16-bit counter.
• Each channel can transfer data up to 64kb and can be programmed
independently.
• Each channel can perform read transfer, write transfer and verify transfer
operations.
• It generates MARK signal to the peripheral device that 128 bytes have
been transferred.
• It operates in 2 modes, i.e., Master mode and Slave mode.
DMA Controller Interfacing
Working of DMA Controller
● The DMA controller 8257 works in two modes namely slave mode and
master mode.

● Likely the processor also works in two modes namely active mode and
HOLD mode.

● The processor normally works in active mode where the processor works
as the master of the computer system.
Working of DMA Controller
● The processor goes to the HOLD state only when DMA transfer is
required, and it gives control of the system bus to 8257

● When the processor is programming 8257 it is in slave mode.

● But at the time of reading the internal memory of the register it is in

active mode and becomes the master of the computer system.

● Initially, when any device has to send data between the device and the
memory, the device has to send DMA request (DREQ) to DMA controller.
Working of DMA Controller
● The DMA controller sends Hold request (HRQ) to the CPU signaling the
CPU through its HOLD pin that it needs to use the buses and waits for the
CPU to assert the HLDA.

● The CPU will finish the present bus cycle and respond to the DMA request
by putting high on its HLDA (hold acknowledge), thus telling the 8257 DMA
that it can go ahead and use the buses to perform its task.

● Now the CPU is in HOLD state and the DMA controller has to manage the
operations over buses between the CPU, memory, and I/O devices.
Working of DMA Controller
● HOLD must remain active high as long as DMA is performing its task.

● While the DMA is using the buses to transfer data, the CPU is sitting idle.

● DMAC will activate DACK (DMA acknowledge), which tells the peripheral
device that it will start to transfer the data.
Working of DMA Controller
● DMAC starts to transfer the data from memory to peripheral as follows
○ DMA puts the address of the first byte of the block on the address bus •
○ Activates MEMR
○ Reads the byte from memory into the data bus
○ Then activates IOW to write it to the peripheral.
○ Then DMAC decrements the counter and increments the address pointer
○ Repeats this process until the count reaches zero and the task is finished

● After DMA finishes its job, it will make HOLD go low and then the CPU will
regain control over the buses.
8257 PIN Diagram
Signal Description of 8257
● DRQ0−DRQ3: These are the four individual channel DMA request inputs,
which are used by the peripheral devices for using DMA services. When
the fixed priority mode is selected, then DRQ0 has the highest priority and
DRQ3 has the lowest priority among them.

● DACK0 − DACK3: These are the active-low DMA acknowledge lines, which
updates the requesting peripheral about the status of their request by the
CPU. These lines can also act as strobe lines for the requesting devices.
Signal Description of 8257
● Do − D7: These are bidirectional, data lines which are used to interface the
system bus with the internal data bus of DMA controller. In the Slave
mode, it carries command words to 8257 and status word from 8257. In
the master mode, these lines are used to send higher byte of the
generated address to the latch. This address is further latched using
ADSTB signal.

● IOR: It is an active-low bidirectional tri-state input line, which is used by

the CPU to read internal registers of 8257 in the Slave mode. In the
master mode, it is used to read data from the peripheral devices during a
memory write cycle.
Signal Description of 8257
● IOW: It is an active low bi-direction tri-state line, which is used to load the
contents of the data bus to the 8-bit mode register or upper/lower byte of
a 16-bit DMA address register or terminal count register. In the master
mode, it is used to load the data to the peripheral devices during DMA
memory read cycle.

● CLK: It is a clock frequency signal which is required for the internal

operation of 8257.

● RESET: This signal is used to RESET the DMA controller by disabling all the
DMA channels.
Signal Description of 8257
● Ao - A3 :These are the four least significant address lines. In the slave
mode, they act as an input, which selects one of the registers to be read
or written. In the master mode, they are the four least significant memory
address output lines generated by 8257.

● CS: It is an active-low chip select line. In the Slave mode, it enables the
read/write operations to/from 8257. In the master mode, it disables the
read/write operations to/from 8257.

● A4 - A7: These are the higher nibble of the lower byte address generated
by DMA in the master mode.
Signal Description of 8257
● READY: It is an active-high asynchronous input signal, which makes DMA
ready by inserting wait states.

● HRQ: This signal is used to receive the hold request signal from the
output device. In the slave mode, it is connected with a DRQ input line
8257. In Master mode, it is connected with HOLD input of the CPU.

● HLDA: It is the hold acknowledgement signal which indicates the DMA

controller that the bus has been granted to the requesting peripheral by
the CPU when it is set to 1.
Signal Description of 8257
● MEMR: It is the low memory read signal, which is used to read the data
from the addressed memory locations during DMA read cycles.

● MEMW: It is the active-low three state signal which is used to write the
data to the addressed memory location during DMA write operation.

● ADST: This signal is used to convert the higher byte of the memory
address generated by the DMA controller into the latches.

● AEN: This signal is used to disable the address bus/data bus.

Signal Description of 8257
● TC: It stands for ‘Terminal Count’, which indicates the present DMA cycle
to the present peripheral devices.

● MARK: The mark will be activated after each 128 cycles or integral
multiples of it from the beginning. It indicates the current DMA cycle is the
128th cycle since the previous MARK output to the selected peripheral
device.

● Vcc: It is the power signal which is required for the operation of the circuit.
Architecture of 8257
8257 Architecture

• Data Bus Buffer: 8-bit Tristate, bidirectional buffer interfaces the internal
bus of 8257 with the external system bus under the control of various
control signals.

• Read/Write Logic: In the slave mode, the read/write logic accepts the I/O
Read or I/O Write signals, decodes the A0-A3 lines and either writes the
contents of the data bus to the addressed internal register or reads the
selected register depending upon whether IOW or IOR signal is activated.
In master mode, the read/write logic generates the IOR and IOW signals to
control the dataflow to or from the selected peripheral.
8257 Architecture

• Control Logic: The control logic controls the sequences of operations and
generates the required control signals like AEN, ADSTB, MEMR,MEMW, TC
and MARK along with the address lines A4-A7, in master mode.

• Priority Resolver: The priority resolver resolves the priority of the four
DMA channels depending upon whether normal priority or rotating
priority is programmed.
Register Organization of 8257

Each of the four channels has a pair of 16-bit registers, DMA Address Register and
Terminal Count Register.

a) DMA Address Register: Each DMA channel has one DMA address register. The
function of this register is to store the address of the starting memory location,
which will be accessed by the DMA channel. The device that wants to transfer data
over a DMA channel, will access the block of the memory with the starting address
stored in the DMA Address Register.

b) Terminal Count Registers: Each of the four DMA channels of 8257 has one
terminal count register (TC). This 16-bit register is used for ascertaining that the
data transfer through a DMA channel ceases or stops after the required number of
DMA cycles.
After each DMA cycle, the terminal count register content will be decremented by
one and finally it becomes zero after the required number of DMA cycles are over.
The bits 14 and 15 of this register indicate the type of the DMA operation
(transfer).
c) Mode Set Register: The mode set register is used for programming the 8257 as
per the requirements of the system. The function of the mode set register is to
enable the DMA channels individually and also to set the various modes of
operation as shown in Figure
d) Status Register: The lower order 4-bits of this register contain the terminal count
status for the four individual channels. If any of these bits is set, it indicates that the
specific channel has reached the terminal count condition. The update flag is not
affected by the read operation. This flag can only be cleared by resetting 8257. The
update flag is set every time, the channel 2 registers are loaded with contents of
the channel 3 registers. It is cleared by the completion of the first DMA cycle of the
new block. This register can only read.
Rotating Priority