Verilog Practice programs

1.BCD counter counts from 00 to 99 and repeat

RTL Code:
module bcd(input clk,rst,output q1,q2);
reg [3:0] q1,q2;

always@(posedge clk)
begin
if(rst)
q1<=4'b0;
else
begin
if(q1==4'b1001)
q1<=4'b0;
else
q1<=q1+1'b1;
end
end

always@(posedge clk)
begin
if(rst)
q2<=4'b0;
else
begin
if((q1==4'b1001) && (q2<4'b1001))
q2<=(q2+1'b1);
else if(q1==4'b1001 &&q2==4'b1001)
q2<=4'b0;
end
end
endmodule

Test Bench :
module bcd_test;

// Inputs
reg clk;
reg rst;

// Outputs
wire [3:0]q1,q2;

// Instantiate the Unit Under Test (UUT)

bcd uut (
.clk(clk),
.rst(rst),
.q1(q1),
.q2(q2)
);
 initial
begin
clk=1'b0;
forever
#5 clk=~clk;
end

task reset;
begin
@(negedge clk)
rst=1'b1;
@(negedge clk)
rst=1'b0;
end
endtask

task initialize;
begin
rst=1'b1;
end
endtask

initial begin
initialize;
reset;
end
 initial
$monitor($time,"clk=%b,rst=%b,q2=%d,q1=%d",clk,rst,q2,q1);

Endmodule

2.Generate a clock of 15ns time period clock

Code :
`timescale 1ns/500ps
module clock;
real period=15;
reg clk;

initial
begin
clk=1'b0;
forever
#(period/2) clk=~clk;
end

initial
$monitor($realtime,"clk=%b",clk);

endmodule
3.Design a JK Flipflop the output is delayed by 2 clock
cycles
RTL Code :
module jkki(input clock,rst,j,k,output q,qbar);
wire w1,w1bar,w2,w2bar,w3,w3bar,w4,w4bar;
dff d1(clock,rst,j,w1,w1bar);
dff d2(clock,rst,w1,w2,w2bar);
dff d3(clock,rst,k,w3,w3bar);
dff d4(clock,rst,w3,w4,w4bar);
jkff j1(clock,rst,w2,w4,q,qbar);
endmodule

module dff(input clock,rst,din,output q,qbar);

reg q;
always@(posedge clock)
begin
if(rst)
q<=0;
else
q<=din;
end
assign qbar=~q;
endmodule

Test Bench :
module jkki_tb;
reg clock,rst,j,k;
wire q,qbar;
integer i;

// Instantiate the Unit Under Test (UUT)

jkki uut (clock,rst,j,k,q,qbar);

initial
begin
clock=1'b0;
forever
#5 clock=~clock;
end

task reset;
begin
@(negedge clock)
rst=1'b1;
@(negedge clock)
rst=1'b0;
end
endtask

task inputs(input m,input n);

begin
@(negedge clock)
begin
j=m;
k=n;
end
end
endtask

initial begin
reset;
#10;
repeat(2)
begin
for(i=0;i<4;i=i+1)
begin
 inputs(i[1],i[0]);
end
end

end

initial
$monitor($time,"clock=%b,rst=%b,j=%b,k=%b,q=%b,qba
r=%b",clock,rst,j,k,q,qbar);

endmodule
4.8 bit up down counter
RTL Code :
module updown8(input clock,resetn,sel,output out);
reg [3:0]out;
always@(posedge clock)
begin
if(~resetn)
out<=0;
else if(sel&&out<8)
out<=out+1'b1;
else if(sel&&out==8)
out<=0;
else if(~sel&&out>0)
out<=out-1'b1;
else if(~sel&&out==0)
out<=8;
else
out<=out;
end
endmodule
Test Bench :
module updown8_tb;

// Inputs
 reg clock;
reg resetn;
reg sel;

// Outputs
wire [3:0]out;

// Instantiate the Unit Under Test (UUT)

updown8 uut (
.clock(clock),
.resetn(resetn),
.sel(sel),
.out(out)
);

initial
begin
clock=1'b0;
forever
#5 clock=~clock;
end

task reset;
begin
@(negedge clock)
resetn=1'b0;
@(negedge clock)
resetn=1'b1;
end
endtask

task select(input i);

begin
@(negedge clock)
sel=i;
end
endtask

initial begin
reset;
select(1);
#150;
select(0);
#100 $finish;

end
initial
 $monitor($time,"sel=%b,out=%d",sel,out);

endmodule
5. counter which counts even numbers in up counting and odd
numbers in down counting
RTL code :
module updownoddeven(input clock,sel,rst,output dout);
reg [3:0]dout;

always@(posedge clock)
begin
if(rst)
dout<=0;
else if(sel)
begin
if(dout%2==0)
dout<=dout+2;
else
dout<=dout+1;
end
else if(~sel)
begin
if(dout%2==0)
dout<=dout-1;
else
dout<=dout-2;
end
end

endmodule

Test Bench :
module updownoddeven_tb;

// Inputs
reg clock;
reg sel;
reg rst;

// Outputs
wire [3:0]dout;

// Instantiate the Unit Under Test (UUT)

updownoddeven uut (
.clock(clock),
.sel(sel),
.rst(rst),
.dout(dout)
);

initial
 begin
clock=1'b0;
forever
#5 clock=~clock;
end

task reset;
begin
@(negedge clock)
rst=1'b1;
@(negedge clock)
rst=1'b0;
end
endtask

initial begin
reset;
#10;
sel=1'b1;
#150;
sel=1'b0;
#100 $finish;
 end
initial
$monitor($time,"clock=%b,sel=%b,dout=%d",clock,sel,dout);

endmodule
6.2 Bit comparator using decoders
RTL Code :
module deco2x4(input a,b,output y);
reg [3:0] y;
always@(*)
begin
case({a,b})
2'b00:y=4'b0001;
2'b01:y=4'b0010;
2'b10:y=4'b0100;
2'b11:y=4'b1000;
endcase
end
endmodule

module comp2bit(input a1,a0,b1,b0,output less,greater,equal);

wire [3:0]w,x;
deco2x4 d1(a1,a0,w);
deco2x4 d2(b1,b0,x);
assign
less=((w[0]&x[1])|(w[0]&x[2])|(w[0]&x[3])|(w[1]&x[2])|(w[1]&x[3])|
(w[2]&x[3]));
assign
greater=((w[1]&x[0])|(w[2]&x[0])|(w[2]&x[1])|(w[3]&x[0])|(w[3]&x[
1])|(w[3]&x[2]));
assign equal=((w[0]&x[0])|(w[1]&x[1])|(w[2]&x[2])|(w[3]&x[3]));
endmodule

Test Bench :
module deco2x4_tb;
reg a,b;
wire [3:0]y;
deco2x4 uut (a,b,y);
integer i;

task inputs(input c,d);

begin
a=c;
b=d;
end
endtask

task initialize;
begin
 a=0;
b=0;
end
endtask

initial begin
initialize;
#10;
for(i=0;i<4;i=i+1)
begin
{a,b}=i;
#10;
end
#100 $finish;
end

initial
$monitor($time,"a=%b,b=%b,y=%b",a,b,y);

endmodule
7.Sequence detector 00/11
Design code :
module det0011(input clk,rst,in,output y);
parameter s0=3'b000,
 s1=3'b001,
s2=3'b010,
s3=3'b011,
s4=3'b100,
s5=3'b101,
s6=3'b110;
reg [2:0] pre_state,next_state;
always@(posedge clk)
begin
if(rst)
pre_state=s0;
else
pre_state=next_state;
end

always@(in or pre_state)
begin
next_state=s0;
case(pre_state)
s0:begin
if(in)
next_state=s2;
else
next_state=s1;
 end
s1:begin
if(in)
next_state=s3;
else
next_state=s6;
end
s2:begin
if(in)
next_state=s5;
else
next_state=s4;
end
s3:begin
if(in)
next_state=s5;
else
next_state=s4;
end
s4:begin
if(in)
next_state=s2;
else
next_state=s6;
 end
s5:begin
if(in)
next_state=s5;
else
next_state=s4;
end
s6:begin
if(in)
next_state=s3;
else
next_state=s6;
end
default:next_state=pre_state;
endcase
end

assign y=((pre_state==s5)||(pre_state==s6))?1'b1:1'b0;
endmodule
Test Bench :
module det0011_tb;

// Inputs
reg clk;
 reg rst;
reg in;

// Outputs
wire y;

// Instantiate the Unit Under Test (UUT)

det0011 uut (
.clk(clk),
.rst(rst),
.in(in),
.y(y)
);

initial
begin
clk=1'b0;
forever
#5 clk=~clk;
end

task reset;
begin
@(negedge clk)
rst=1'b1;
@(negedge clk)
rst=1'b0;
end
endtask

task inputs(input i);

begin
@(negedge clk);
in=i;
end
endtask

task initialize;
begin
in=1'b0;
rst=1'b0;
end
endtask

task delay;
begin
#10;
end
endtask

initial
begin
$monitor("in=%b,state=%b,rst=%b,clk=%b,y=%b",in,uut.pre_state,rst
,clk,y);
reset;
delay;
repeat(5)
begin
inputs({$random}%2);
inputs({$random}%2);
inputs(0);
inputs(0);
end
end

endmodule
8.Draw the block diagram of a dual port synchronous Static
RAM of size (64x16). Clock is active at posedge , reset is
active high synchronous reset. Address pointers are input
ports, “re” and “we” are two active high control inputs. The
memory supports simultaneous read and write operation.
Implement parameter over-riding such that the new RAM has
a size (16x64)
RTL Code :
module mem64x16(input clock,clear,wr_enb,rd_enb,addr,din,output
dout,error);
parameter address=6,
width=16,
length=64;
reg [width-1:0]dout;
wire [width-1:0]din;
wire [address-1:0]addr;
reg [width-1:0]mem[length-1:0];
integer i;
reg error;

always@(posedge clock or posedge clear)

begin
if(clear)
begin
for(i=0;i<length;i=i+1)
mem[i]<=0;
dout<=0;
error<=0;
end
else if(wr_enb && rd_enb)
error<=1'b1;
else if(wr_enb&&~rd_enb)
begin
error<=0;
mem[addr]<=din;
end
else if(rd_enb&&~wr_enb)
begin
error<=0;
dout<=mem[addr];
end
end
endmodule

module memparameter(input
clock,clear,wr_enb,rd_enb,addr,din,output dout,error);
mem64x16 #(4,64,16)
m1(clock,clear,wr_enb,rd_enb,addr,din,dout,error);
endmodule

9.Sequence detector 11011(melay)

RTL code :
module seq11011(input clk,in,rst,output y);
parameter s0=2'b000,
s1=3'b001,
 s2=3'b010,
s3=3'b011,
s4=3'b100;
reg [2:0] pre_state,next_state;
reg y,out;
always@(posedge clk)
begin
if(rst)
begin
pre_state=s0;
y=1'b0;
end
else
begin
pre_state=next_state;
y=out;
end
end

always@(in or pre_state)
begin
next_state=s0;
case(pre_state)
s0:begin
 if(in)
begin
next_state=s1;
out=1'b0;
end
else
begin
out=1'b0;
next_state=s0;
end
end
s1:begin
if(in)
begin
next_state=s2;
out=1'b0;
end
else
begin
out=1'b0;
next_state=s0;
end
end
s2:begin
 if(in)
begin
out=1'b0;
next_state=s2;
end
else
begin
out=1'b0;
next_state=s3;
end
end
s3:begin
if(in)
begin
next_state=s4;
out=1'b0;
end
else
begin
out=1'b0;
next_state=s0;
end
end
s4:begin
 if(in)
begin
next_state=s0;
out=1'b1;
end
else
begin
out=1'b0;
next_state=s0;
end
end
default:begin
next_state=pre_state;
out=1'b0;
end
endcase
end

endmodule
Test Bench :
module seq11011_tb;

// Inputs
reg clk;
 reg in;
reg rst;

// Outputs
wire y;

// Instantiate the Unit Under Test (UUT)

seq11011 uut (
.clk(clk),
.in(in),
.rst(rst),
.y(y)
);

initial
begin
clk=1'b0;
forever
#5 clk=~clk;
end

task reset;
begin
@(negedge clk)
rst=1'b1;
@(negedge clk)
rst=1'b0;
end
endtask

task inputs(input i);

begin
@(negedge clk);
in=i;
end
endtask

task initialize;
begin
in=1'b0;
rst=1'b0;
end
endtask

task delay;
begin
#10;
end
endtask

initial
begin
$monitor("in=%b,state=%b,rst=%b,clk=%b,y=%b",in,uut.pre_state,rst
,clk,y);
reset;
delay;
repeat(5)
begin
inputs(1);
inputs(1);
inputs(0);
end
end
endmodule
10.NX1 Mux
RTL code :
module nxmux(input s,din,output dout);
parameter sel=2,
data=4;
integer i;
wire [sel-1:0]s;
wire [data-1:0]din;
reg dout;

always@(*)
begin
for(i=0;i<data;i=i+1)
begin
if(s==i)
dout=din[i];
end
end
endmodule

module nx1mux(input s,din,output dout);

wire [3:0]s;
wire [15:0]din;
nxmux #(4,16) m1(s,din,dout);
endmodule

Test Bench :
module nx1mux_tb;
parameter sel=4,
data=16;
integer i,j;
// Inputs
 reg [sel-1:0]s;
reg [data-1:0]din;

// Outputs
wire dout;

// Instantiate the Unit Under Test (UUT)

nx1mux uut (
.s(s),
.din(din),
.dout(dout)
);

initial begin
// Initialize Inputs
s = 0;
din = 0;
j=1;
for(i=0;i<(data+sel);i=i+1)
begin
j=j*2;
end
// Wait 100 ns for global reset to finish
#100;
for(i=0;i<j;i=i+1)
begin
 {s,din}=i;
#5;
end
end
initial
$monitor($time,"s=%b,din=%b,dout=%b",s,din,dout);

endmodule

11. . Derive a minimal state table for an FSM that acts as a 3bit parity
generator. For every 3 bits observed on the input ′w′ during 3
consecutive cycles, the FSM generates the parity p=1 if and only if
the no. of 1s is odd.
Design code :
module odd3bit(input clk,in,rst,output y);
parameter s0=4'b0000,
s1=4'b0001,
s2=4'b0010,
s3=4'b0011,
s4=4'b0100,
s5=4'b0101,
s6=4'b0110,
s7=4'b0111,
s8=4'b1000,
s9=4'b1001,
s10=4'b1010;
reg [3:0] pre_state,next_state;
always@(posedge clk)
begin
if(rst)
pre_state=s0;
else
pre_state=next_state;
end

always@(in or pre_state)
begin
next_state=s0;
case(pre_state)
s0:begin
if(in)
next_state=s2;
else
next_state=s1;
end
s1:begin
if(in)
next_state=s3;
else
next_state=s4;
 end
s2:begin
if(in)
next_state=s6;
else
next_state=s5;
end
s3:begin
if(in)
next_state=s6;
else
next_state=s7;
end
s4:begin
if(in)
next_state=s8;
else
next_state=s4;
end
s5:begin
if(in)
next_state=s3;
else
next_state=s9;
 end
s6:begin
if(in)
next_state=s10;
else
next_state=s5;
end
s7:begin
if(in)
next_state=s3;
else
next_state=s9;
end
s8:begin
if(in)
next_state=s6;
else
next_state=s7;
end
s9:begin
if(in)
next_state=s8;
else
next_state=s4;
 end
s10:begin
if(in)
next_state=s10;
else
next_state=s5;
end
default:next_state=pre_state;
endcase
end

assign
y=((pre_state==s7)||(pre_state==s8)||(pre_state==s9)||(pre_state=
=s10))?1'b1:1'b0;
endmodule
Test Bench :
module odd3bit_tb;

// Inputs
reg clk;
reg in;
reg rst;

// Outputs
 wire y;

// Instantiate the Unit Under Test (UUT)

odd3bit uut (
.clk(clk),
.in(in),
.rst(rst),
.y(y)
);

initial
begin
clk=1'b0;
forever
#5 clk=~clk;
end

task reset;
begin
@(negedge clk)
rst=1'b1;
@(negedge clk)
rst=1'b0;
end
endtask

task inputs(input i);

begin
@(negedge clk);
in=i;
end
endtask

task initialize;
begin
in=1'b0;
rst=1'b0;
end
endtask

task delay;
begin
#10;
end
endtask

initial
begin
$monitor("in=%b,state=%b,rst=%b,clk=%b,y=%b",in,uut.pre_state,rst
,clk,y);
reset;
delay;
repeat(5)
begin
inputs({$random}%2);
inputs({$random}%2);
end
end

endmodule
12.Generate real random numbers between 1.000 to 2.000
module rand;
real a;
real c;
integer i;

initial
begin
for(i=0;i<5;i=i+1)
begin
#5;
c=({$random}%1000);
c=c+1000;
c=c/1000;
$display($time,"c=%f",c);
end
end
endmodule
13.D ff using d latch
RTL Code :
module dff(input clock,rst,din,output q,qbar);
wire w,x;
dff_latch d1(~clock,din,rst,w,x);
dff_latch d2(clock,w,rst,q,qbar);
endmodule

module dff_latch(input ctrl,d,rst,output q,qbar);

reg q;
always@(*)
begin
if(rst)
q<=0;
else if(ctrl)
q<=d;
else if(~ctrl)
q<=q;
end
assign qbar=~q;
endmodule
Test Bench :
module dff_tb;

// Inputs
reg clock;
reg rst;
reg din;

// Outputs
wire q;
wire qbar;
integer i;

// Instantiate the Unit Under Test (UUT)

dff uut (
.clock(clock),
 .rst(rst),
.din(din),
.q(q),
.qbar(qbar)
);

initial
begin
clock=1'b0;
forever
#5 clock=~clock;
end

task reset;
begin
@(negedge clock)
rst=1'b1;
@(negedge clock)
rst=1'b0;
end
endtask
 task initialize;
begin
din=0;
rst=0;
end
endtask

initial begin
initialize;
#10;
reset;
#10;
for(i=0;i<2;i=i+1)
begin
@(negedge clock)
din=i;
end
end

initial
$monitor($time,"clock=%b,din=%b,rst=%b,q=%b,qbar=
%b",clock,din,rst,q,qbar);
endmodule
14.Generate a sequence 01,10,01,20,01,40,01,80 and repeat
RTL Code :
module seq01(input clock,rst,output out);
reg [7:0]out;
reg [1:0] count;
reg [3:0]temp;

always@(posedge clock)
begin
if(rst)
begin
count<=0;
out[7:4]<=0;
temp<=0;
end
else if(out[7:4]!=0)
out[7:4]<=0;
else if(out[7:4]==8)
begin
out[7:4]<=0;
count<=0;
end
else if(count==3)
begin
out[7:4]<=2**count;
count<=0;
end
else if(count<3)
begin
out[7:4]<=2**count;
count<=count+1;
end
end

always@(posedge clock)
begin
if(rst)
out[3:0]<=1;
else if(out[3:0]==0)
out[3:0]<=1;
else if(out[3:0]==1)
out[3:0]<=0;
end
endmodule
Test Bench :
module seq01_tb;

// Inputs

reg clock;

reg rst;

// Outputs

wire [7:0]out;

// Instantiate the Unit Under Test (UUT)

seq01 uut (

.clock(clock),
 .rst(rst),

.out(out)

);

initial

begin

clock=0;

forever

#5 clock=~clock;

end

task reset;

begin

@(negedge clock)

rst=1'b1;
 @(negedge clock)

rst=1'b0;

end

endtask

initial begin

reset;

end

initial

$monitor($time,"out=%b",out);

endmodule
15. Write a RTL code to design a sequential circuit that counts the following
sequence 1,2,2,3,3,3,4,4,4,4,5,5,5,5,5 and repeat the sequence.
RTL Code :
module seq12233(input clock,rst,output out);
reg [2:0]out;
reg [2:0]count;
always@(posedge clock)
begin
if(rst)
begin
out<=3'd1;
count<=3'd1;
end
else
begin
if(count==out&&out<3'd5)
begin
count<=3'd1;
out<=out+3'd1;
end
else if(count==out&&out==3'd5)
begin
count<=3'd1;
out<=3'd1;
end
else if(count<out&&out<3'd6)
begin
out<=out;
count<=count+3'd1;
end
end
end
endmodule
Test Bench :
module seq12233_tb;

reg clock;
reg rst;

wire [2:0]out;

// Instantiate the Unit Under Test (UUT)

seq12233 uut (
.clock(clock),
.rst(rst),
.out(out)
);
initial
begin
clock=1'b0;
forever
#5 clock=~clock;
end

task reset;
begin
 @(negedge clock)
rst=1'b1;
@(negedge clock)
rst=1'b0;
end
endtask

initial begin
reset;
end
initial
$monitor($time,"clock=%b,out=%d",clock,out);

endmodule
16. Design an 8-bit counter by using a forever loop, named block and disabling
of named block. The counter starts counting at count = 5 and finishes at count
= 67. The count is incremented at positive edge of clock. The clock has a time
period of 10. The counter counts through the loop only once and then is
disabled.
Code :
module forever_counter;

reg clock;
reg [7:0]count;

initial
begin
clock=0;
forever
#5 clock=~clock;
end

initial
begin:counting
count=5;
forever
begin
if(count==67)
disable counting;
else
begin
@(posedge clock)
count=count+1'b1;
end
end
end

initial
$monitor($time,"count=%d",count);

endmodule

17. . Write Verilog Behavioral code for generating an infinite

sequence of numeric patterns 5-7-5-7.......................... using the "for"
loop.
Code :
module forin;
reg [3:0]a;
integer i;

initial
begin
for(i=0;i<10;i=i)
begin
a=5;
#5;
a=7;
#5;
end
end
initial
$monitor($time,"a=%d",a);
Endmodule
18. Write synthesizable RTL code for a 8-bit left shift SISO register
such that shifting happens for the first 4 clock cycles within every 8
clock cycles. (Reset is active high, synchronous reset). For the rest 4
clock cycles shifter acts like a buffer.
RTL Code :
module shiftreg2(input clk,rst,din,output dout);
parameter bits=8;
reg [bits-1:0]q;
reg dout;
reg [2:0]count,p;

always@(posedge clk)
begin
if(rst)
begin
q<=0;
dout<=0;
count<=0;
p<=0;
end
else if(count<4)
begin
q<={q[bits-2:0],din};
dout<=din;
count<=count+1;
end
else if(count==4)
begin
q<=q;
p<=p+1;
dout<=dout;
if(p==3)
begin
p<=0;
count<=count-3'b100;
end
end
end
endmodule
Test Bench :
module shiftreg2_test;
reg clk,rst,din;
wire dout;
shiftreg2 uut (clk,rst,din,dout);
initial
begin
clk=1'b0;
forever
#5 clk=~clk;
end

task reset;
begin
@(negedge clk)
rst=1'b1;
 @(negedge clk)
rst=1'b0;
end
endtask

task inputs(input k);

begin
@(negedge clk)
din=k;
end
endtask

task initialize;
begin
rst=1'b1;
din=1'b0;
end
endtask

initial begin
initialize;
#10;
reset;
 #10;
repeat(10)
begin
inputs(1'b1);
inputs(1'b0);
inputs(1'b1);
inputs(1'b0);
end
end

initial
$monitor($time,"clk=%b,rst=%b,din=%b,q=%b,dout=%b,count=
%d,p=%d",clk,rst,din,uut.q,dout,uut.count,uut.p);

endmodule
19.Jhonson counter 4 bit
RTL code :
module jhonson4bit(input rst,clock,output q);
reg [3:0]q;
always@(posedge clock or posedge rst)
begin
if(rst)
q<=0;
else
q<={~q[0],q[3:1]};
end
endmodule
Test Bench:
module jhonson4bit_tb;

// Inputs
reg rst;
reg clock;

// Outputs
wire [3:0]q;

// Instantiate the Unit Under Test (UUT)

jhonson4bit uut (
.rst(rst),
.clock(clock),
.q(q)
);

initial
begin
clock=1'b0;
forever
 #5 clock=~clock;
end

task reset;
begin
@(negedge clock)
rst=1'b1;
@(negedge clock)
rst=1'b0;
end
endtask

initial begin
reset;
end
initial
$monitor($time,"clock=%b,q=%b",clock,q);

endmodule
20. Draw the block diagram of a dual port synchronous Static RAM of
size (64x16). Clock is active at posedge , reset is active high
synchronous reset. Address pointers are input ports, “re” and “we”
are two active high control inputs. The memory supports
simultaneous read and write operation. Implement parameter over-
riding such that the new RAM has a size (16x64).
RTL Code :
module smem64x16(input
clock,clear,wr_enb,rd_enb,addr,din,output dout,error);
reg [15:0]dout;
wire [15:0]din;
wire [5:0]addr;
reg [15:0]mem[63:0];
integer i;
reg error;

always@(posedge clock or posedge clear)

begin
if(clear)
begin
for(i=0;i<64;i=i+1)
mem[i]<=0;
dout<=0;
error<=0;
end
else if(wr_enb && rd_enb)
error<=1'b1;
else if(wr_enb&&~rd_enb)
begin
error<=0;
mem[addr]<=din;
end
else if(rd_enb&&~wr_enb)
begin
error<=0;
dout<=mem[addr];
end
end
endmodule
Test Bench :
module smem64x16_tb;

// Inputs
reg clock;
reg clear;
reg wr_enb;
reg rd_enb;
reg [5:0]addr;
reg [15:0]din;

reg[5:0]n;

// Outputs
wire [15:0]dout;
wire error;

// Instantiate the Unit Under Test (UUT)

smem64x16 uut (
.clock(clock),
.clear(clear),
.wr_enb(wr_enb),
.rd_enb(rd_enb),
.addr(addr),
.din(din),
.dout(dout),
.error(error)
);

initial
begin
clock=0;
forever #5 clock=~clock;
end

task clr;
begin
clear=1'b1;
#20;
clear=1'b0;
end
endtask

task write(input [5:0]h,input [15:0]g);

begin
@(negedge clock)
begin
rd_enb=1'b0;
wr_enb=1'b1;
addr=h;
din=g;
end
end
endtask

task read(input [5:0]h);

begin
@(negedge clock)
begin
wr_enb=1'b0;
rd_enb=1'b1;
addr=h;
end
end
endtask

task initialize;
begin
clear=0;
wr_enb=0;
rd_enb=0;
addr=0;
din=0;
end
endtask

initial begin
clr;
initialize;
#10;
repeat(4)
begin
n={$random}%64;
write(n,{$random}%65535);
read(n);
 end
#20;
rd_enb=1'b1;
wr_enb=1'b1;
#50 $finish;
end

initial
$monitor($time,"clock=%b,clear=%b,addr=%d,din=%d,dout=%d
,wr_enb=%b,rd_enb=%b,error=%b",clock,clear,addr,din,dout,wr_enb
,rd_enb,error);
Endmodule
21. Write a RTL code using dataflow abstraction for
designing a 4 bit comparator such that when c=1 it acts
as a signed comparator & when c=0 it acts as an
unsigned comparator
RTL Code :
module masscomp3(input a,b,c,output g,l,e);
wire [3:0]a,b;
reg g,l,e;
always@(*)
begin
if(c==0)
begin
e=(a[3]~^b[3])&(a[2]~^b[2])&(a[1]~^b[1])&(a[0]~^b[0]);
g=(a[3]&(~b[3]))|((a[3]~^b[3])&(a[2]&(~b[2])))|((a[3]~^b[3])
&(a[2]~^b[2])&(a[1]&(~b[1])))|((a[3]~^b[3])&(a[2]~^b[2])&(a[
1]~^b[1])&(a[0]&(~b[0])));
l=(~a[3]&(b[3]))|((a[3]~^b[3])&(~a[2]&(b[2])))|((a[3]~^b[3])&
(a[2]~^b[2])&(~a[1]&(b[1])))|((a[3]~^b[3])&(a[2]~^b[2])&(a[1
]~^b[1])&(~a[0]&(b[0])));
end
else if(c==1)
begin
e=(a[3]~^b[3])&(a[2]~^b[2])&(a[1]~^b[1])&(a[0]~^b[0]);
g=(~a[3]&(b[3]))|((a[3]~^b[3])&(a[2]&(~b[2])))|((a[3]~^b[3])
&(a[2]~^b[2])&(a[1]&(~b[1])))|((a[3]~^b[3])&(a[2]~^b[2])&(a[
1]~^b[1])&(a[0]&(~b[0])));
l=(a[3]&(~b[3]))|((a[3]~^b[3])&(~a[2]&(b[2])))|((a[3]~^b[3])&
(a[2]~^b[2])&(~a[1]&(b[1])))|((a[3]~^b[3])&(a[2]~^b[2])&(a[1
]~^b[1])&(~a[0]&(b[0])));
end
end
endmodule
Test Bench :
module masscomp3_test;
reg [3:0]a,b;
reg c;
wire g,l,e;
integer i;

masscomp3 uut (a,b,c,g,l,e);

initial begin
a=0;b=0;c=0;
#20;
for(i=0;i<=255;i=i+1)
begin
{a,b}=i;
#5;
end
c=1;
for(i=0;i<255;i=i+1)
begin
{a,b}=i;
#5;
end
end

initial
 $monitor($time,"a=%b,b=%b,c=%b,g=%b,l=%b,e=%b",a,b,c,g,l,e
);
endmodule