Microprocessor

Module 1: Introduction to Microprocessor and Microcomputer Architecture

1. Microprocessor Basics
● Definition: A microprocessor is a programmable electronic chip that functions as
the central processing unit (CPU) of a computer. It performs arithmetic and logic
operations, decision-making, and data processing.
● Microcomputer: A microprocessor-based system with limited resources.
Examples include embedded systems in devices like washing machines and
mobile phones.

Microprocessor-based system
2. Key Concepts
● Bit and Word:
○ Bit: Smallest unit of data in computing, represented by 0 or 1.
○ Word: A fixed-sized piece of data handled as a unit by the microprocessor
(e.g., 16-bit, 32-bit).
● Bus System:
○ Data Bus: Carries data between the processor, memory, and peripherals.
○ Address Bus: Transmits the address of the data.
○ Control Bus: Manages control signals and the coordination of different
parts of the computer.
3. Microprocessor Architecture
● ALU (Arithmetic and Logic Unit):
○ Performs arithmetic (addition, subtraction) and logic operations (AND,
OR).
○ Stores result in the accumulator.
● Registers:
○ General-Purpose Registers: Six 8-bit registers (B, C, D, E, H, L) that can
form 16-bit register pairs (BC, DE, HL).
○ Accumulator (A): An 8-bit register used for arithmetic and logic
operations.
 ○ Flag Register: Consists of five flags (Zero, Sign, Parity, Carry, Auxiliary
Carry) that indicate the outcome of operations.
● Control Unit: Directs the operation of the processor by generating control
signals.
4. Microprocessor Classification
● Data Bus Width:
○ 4-bit, 8-bit, 16-bit, 32-bit processors: Refers to the size of the data bus,
determining how much data can be processed at a time.
● Application-Based:
○ General-Purpose Microprocessors: Used in general computing (e.g.,
Intel Pentium).
○ Microcontrollers: Integrated with memory and I/O ports for specific
control applications (e.g., 8051).
○ Special-Purpose Processors: Designed for specific tasks like signal
processing (DSPs, ASICs).
● Architecture-Based:
○ RISC (Reduced Instruction Set Computer): Simplified instructions for
fast execution.
○ CISC (Complex Instruction Set Computer): More complex instructions
that can perform multiple operations.

Module 2: 8085 Microprocessor Architecture

 Internal Architecture of 8085
1. Overview
● 8085 Microprocessor:
○ 8-bit processor with a 16-bit address bus.
○ Can address up to 64KB of memory.
○ Operates at a maximum clock frequency of 3 MHz.
2. Internal Architecture

● Registers:
○ Accumulator (A): Core register for arithmetic operations.
○ Flag Registers:
 Flag register
■ Zero (Z) Flag: Set to 1 if the result of an operation is zero.
■ Carry (CY) Flag: Set to 1 if an arithmetic operation results in a
carry out of the most significant bit.
■ Sign (S) Flag: Copies the most significant bit of the result to
indicate its sign (1 for negative, 0 for positive).
■ Parity (P) Flag: Set to 1 if the result has an even number of 1s.
■ Auxiliary Carry (AC) Flag: Set to 1 if there is a carry from bit D3 to
bit D4.
○ General Purpose Registers: B, C, D, E, H, L, used for temporary data
storage.
○ Stack Pointer (SP): Points to the top of the stack, a special region in
memory used for temporary storage during function calls.
○ Program Counter (PC): Holds the address of the next instruction to be
executed.
● Instruction Set:
○ Data Transfer: MOV, MVI (move instructions).
○ Arithmetic: ADD, SUB, INR, DCR.
○ Logical: ANA, XRA, CMP.
○ Branching: JMP, CALL, RET, conditional branches.
○ Machine Control: HLT, NOP (No Operation), DI (Disable Interrupts), EI
(Enable Interrupts).
● Timing and Control Unit:
○ Generates control signals for data bus, address bus, and control bus
coordination.
○ Controls machine cycles: Fetch, decode, and execute.
3. Instruction Cycle

● Fetch-Decode-Execute:
○ Fetch: Retrieve the instruction from memory.
○ Decode: Interpret the instruction.
○ Execute: Perform the operation.
4. 8085 Pin Configuration and Signals

8085 microprocessor pin layout and signal groups

● Address and Data Buses:
○ A8-A15: High-order address bus.
○ AD0-AD7: Multiplexed address and data bus.
● Control & Status Signals:
○ ALE (Address Latch Enable): Distinguishes between address and data
on the multiplexed bus.
○ RD̅ (Read): Indicates data is being read from memory or I/O.
○ WR̅ (Write): Indicates data is being written to memory or I/O.
○ IO/M, S1 and S0: Status signals.

SI S0 States

0 0 Halt

0 1 Write
 1 0 Read

1 1 Fetch

Status signals and associated operations

● Power and Clock:
○ Vcc: +5V power supply.
○ Vss: Ground reference
○ X1, X2: Connections for an external clock crystal to set the operating
frequency.
○ CLK: Clock output
● Externally Initiated and Interrupt Signals
○ RESET IN̅: When this pin's signal is low, the Program Counter (PC) is set
to 0, buses are tri-stated, and the processor is reset.
○ RESET OUT: This signal indicates that the processor is being reset and
can be used to reset other devices.
○ READY: When this signal is low, the processor waits for an integral
number of clock cycles until it goes high.
○ HOLD: This signal indicates that a peripheral device, like a Direct Memory
Access (DMA) controller, is requesting the use of the address and data
buses.
○ HLDA (Hold Acknowledge): This signal acknowledges the HOLD
request.
○ INTR (Interrupt Request): A general-purpose interrupt signal.
○ INTA̅ (Interrupt Acknowledge): This signal is used to acknowledge an
interrupt request.
○ RST 7.5, RST 6.5, RST 5.5 (Restart Interrupts): These are vectored
interrupts with higher priority than the INTR interrupt.
○ TRAP: This is a non-maskable interrupt with the highest priority.
● Serial I/O Signals
○ SID (Serial Input Data): This is the serial input signal. A bit on this line is
loaded into the D7 bit of register A using the RIM (Read Interrupt Mask)
instruction.
○ SOD (Serial Output Data): This is the serial output signal. The output
SOD can be set or reset using the SIM (Set Interrupt Mask) instruction.

Module 3: Instruction Set and Execution in 8085

1. Instruction Set Classification
● Data Transfer Instructions:
 ○ MOV: Copy data between registers.
○ MVI: Move immediate data into a register.
● Arithmetic Instructions:
○ ADD, SUB: Basic arithmetic operations.
○ INR, DCR: Increment and decrement.
● Logical Instructions:
○ ANA: Logical AND.
○ XRA: Logical XOR.
○ CMP: Compare registers.
● Branching Instructions:
○ JMP: Unconditional jump.
○ CALL: Call a subroutine.
○ RET: Return from a subroutine.
● Machine Control Instructions:
○ NOP: No operation, used for timing adjustments.
○ HLT: Halt the processor.
2. Addressing Modes
● Immediate Addressing: Operand is specified in the instruction itself.
○ Example: MVI A, 05H (Move 05H to Accumulator A).
● Register Addressing: Operand is in one of the registers.
○ Example: MOV A, B (Copy the content of register B to A).
● Direct Addressing: The address of the operand is given explicitly.
○ Example: LDA 2000H (Load the content of memory location 2000H into
A).
● Indirect Addressing: The address of the operand is specified in a register pair.
○ Example: MOV A, M (Move the content of the memory location pointed to
by HL to A).
● Implicit Addressing: The operand is implied in the instruction.
○ Example: CMA (Complement the content of the accumulator).

Module 4: Instruction Execution and Timing Diagram

1. Instruction Cycle
● Instruction Cycle: The time taken to fetch, decode, and execute an instruction.
○ Machine Cycle: The time required to complete one operation (e.g.,
memory read, memory write).
○ T-State: One subdivision of the machine cycle, corresponding to one clock
period.
2. Opcode Fetch Cycle
● Process:
 ○ The address of the instruction is placed on the address bus.
○ The control unit fetches the opcode from memory and places it in the
instruction register.
○ The instruction is then decoded and executed.
3. Timing Diagrams
● Memory Read Cycle: Timing diagram showing how data is read from memory.
● Memory Write Cycle: Diagram showing the timing for writing data to memory.
● I/O Read/Write Cycle: Diagrams for input/output operations.
4. Example Timing Diagram
● IN 80H: Timing diagram for the IN instruction, which inputs data from an I/O port
to the accumulator.

Module 5: Interrupts in 8085

1. Interrupt Structure
● Interrupts: Mechanism to handle external or internal events that require
immediate attention.
● Types of Interrupts:
○ Software Interrupts: Triggered by an instruction in the program.
○ Hardware Interrupts: Triggered by external hardware signals.
○ Vectored Interrupts: Automatically jumps to a predefined memory
location.
○ Non-Vectored Interrupts: Requires the interrupting device to supply the
address of the ISR.
○ Maskable Interrupts: Can be disabled or masked.
○ Non-Maskable Interrupts: Cannot be disabled.
2. Interrupt Handling
● Interrupt Process:
○ Save the current program state (PC and registers).
○ Jump to the ISR.
○ Execute the ISR.
○ Restore the program state and continue execution.
● Interrupt Sources in 8085:
○ TRAP: Non-maskable, highest priority.
○ RST7.5, RST6.5, RST5.5: Maskable, vectored interrupts.
○ INTR: General-purpose interrupt.
Hardware interrupts of 8085

Interrupt Interrupt Maskable or Edge or Level Priority

vector non-maskable triggered
 TRAP 0024H Non-maskable Level 1

RST 7.5 003CH Maskable Rising edge 2

RST 6.5 0034H Maskable Level 3

RST 5.5 002CH Maskable Level 4

INTR Decided by Maskable Level 5

hardware

3. Masking Interrupts
● Masking: Selectively disabling specific interrupts.
● EI: Enable interrupts.
● DI: Disable interrupts.
● SIM/RIM Instructions: Set Interrupt Mask and Read Interrupt Mask.

Module 6: 8086 Microprocessor

● Type: 16-bit microprocessor.
● Address Bus: 20-bit, allowing access to up to 2^20 or 1 MB of memory.
● I/O Ports: Supports up to 64K I/O ports.
● Registers: Contains 14 registers, each 16-bit wide.
● Bus: Multiplexed address and data bus; uses AD0-AD15 and A16-A19.
● Power Supply: Requires a +5V power supply.
● Package: Available as a 40-pin dual in-line package (DIP).
● Clock: Operates with a single-phase clock with a 33% duty cycle.
1. Operating Modes
● Minimum Mode: Single microprocessor configuration. Selected by applying logic
1 to the MN/MX# pin.
● Maximum Mode: Multi-processor configuration. Selected by applying logic 0 to
the MN/MX# pin.

2. Bus Interface Unit (BIU)

● Instruction Queue: Prefetches up to 6 bytes of instructions from memory to
speed up execution, implementing a pipeline architecture.
● Segment Registers:
○ CS (Code Segment): Holds the starting address of the code segment.
○ DS (Data Segment): Points to the data segment in memory.
○ SS (Stack Segment): Points to the stack segment.
○ ES (Extra Segment): Typically used for string operations.
 ● Instruction Pointer (IP): Holds the address of the next instruction to be
executed.
● Address Calculation: The 20-bit physical address is formed by combining a
16-bit segment address with a 16-bit offset address.
3. Execution Unit (EU)
● Control Circuitry: Manages instruction decoding and execution.
● ALU (Arithmetic Logic Unit): Performs arithmetic and logical operations.
● Instruction Decoder: Converts instructions into executable operations.
● Pointer and Index Registers:
○ SP (Stack Pointer): Points to the current position in the stack.
○ BP (Base Pointer): Typically used for accessing data on the stack.
○ SI (Source Index) and DI (Destination Index): Used for indexed
addressing and string operations.
● Flag Register: Contains status flags that reflect the outcome of ALU operations
(e.g., Zero Flag, Sign Flag).
4. Bus Interface Unit (BIU) Operations
● Prefetching: Instruction bytes are fetched in advance and stored in the
instruction queue, allowing the BIU to look ahead in the program and fetch
instructions during idle periods.
● Pipeline Operation: Overlapping of instruction fetch and execution enhances
processing efficiency.
● Address Generation: The BIU generates the physical memory addresses by
combining the segment and offset addresses, enabling access to a 1MB address
space.
5. Memory Segmentation
● Segments: The 8086 uses four segments (Code, Data, Stack, Extra) to manage
memory. Each segment is 64KB in size.
● Advantages:
○ Allows efficient management of memory and easier relocation of
programs.
○ Segmentation helps in modular programming and enhances security by
limiting the access of code to its own segment.
6. 8086 Register Organization
● General-Purpose Registers: AX, BX, CX, and DX, each can be divided into two
8-bit registers (e.g., AX into AH and AL).
● Segment Registers: CS, DS, SS, ES—each pointing to different segments in
memory.
● Pointer Registers: SP, BP.
● Index Registers: SI, DI, used for operations on arrays and strings.
● Instruction Pointer (IP): Tracks the next instruction to execute.
 ● Flags Register: 9 status flags indicating conditions like carry, zero, sign, and
overflow.
7. 8086 Pin Configuration
● Address/Data Multiplexing: Pins AD0-AD15 are used for both address and
data, with the address being sent first, followed by the data.
8. Minimum and Maximum Mode Operations
● Minimum Mode:
○ Suitable for small systems with a single processor.
○ Provides all necessary control signals internally.
● Maximum Mode:
○ Suitable for systems with multiple processors.
○ Requires an external bus controller (8288) to generate control signals.
9. Instruction Set and Execution
● Instruction Pipeline: Allows prefetching of instructions to speed up execution.
● Clock Cycles: Execution of instructions involves multiple clock cycles, with
different stages for fetching, decoding, and executing.
Bus Arbitration and Control in Maximum Mode
● Bus Controller (8288): Generates command signals like memory read/write and
I/O read/write.
● Bus Arbitration: In a multiprocessor system, the 8086 uses bus arbitration to
control access to shared resources.

8051 Microcontroller Overview

The 8051 microcontroller is one of the most widely used microcontrollers in embedded systems.
Its architecture, memory management, and features make it a powerful tool for controlling
various electronic devices.

Key Features:

● 8-bit CPU: The microcontroller can handle 8-bit data at a time.

● 16-bit Program Counter (PC): This allows the 8051 to address up to 64KB of memory.
 ● 8-bit Stack Pointer (SP): Points to the top of the stack in RAM.
● 128 bytes of Internal RAM: Used for storing temporary data during program execution.
● 128 bytes of Special Function Registers (SFRs): These registers control specific
functions within the microcontroller.
● 32 I/O Pins: Organized into four 8-bit ports (P0 to P3), which can be used for various
input/output operations.
● Two 16-bit Timer/Counters (T0 and T1): These are essential for timing operations.
● Five Interrupts: Including two external and three internal interrupts.
● Full-Duplex Serial Communication: Facilitates serial communication via a built-in serial
port.

8051 Microcontroller Pin Diagram:

Pins 1 - 8 (PORT 1):

● Pins 1 to 8 are the PORT 1 Pins of 8051.

● PORT 1 Pins consists of 8 - bit bidirectional Input / Output Port with internal pull-up resistors.
● In some of the newer 8051 Microcontrollers, few PORT 1 Pins have dual functions. P1.0 and
P1.1 act as Timer 2 and Timer 2 Trigger Input respectively.

Pin 9 (RST):

● Pin 9 is the Reset Input Pin.

 ● It is an active HIGH Pin i.e. if the RST Pin is HIGH for a minimum of two machine cycles, the
microcontroller will be reset. During this time, the oscillator must be running.

Pins 10 - 17 (PORT 3):

● Pins 10 to 17 form the PORT 3 pins of the 8051 Microcontroller.

● PORT 3 also acts as a bidirectional Input / Output PORT with internal pull-ups.
● Additionally, all the PORT 3 Pins have special functions multifunctional for the 8051
microcontrollers.

Architecture:

The 8051 architecture is designed to be efficient and straightforward, making it ideal for a range
of applications. It includes:

● Accumulator (A): Used for arithmetic operations.

● B Register: Primarily used for multiplication and division.
● Program Status Word (PSW): Stores the status of the program.
● Data Pointer (DPTR): Consists of two 8-bit registers (DPH and DPL) and is used for
addressing external memory.
● Port Registers (P0 to P3): Control the I/O ports.

FLAG:
 ● Carry Flag(CY): During addition and subtraction any carry or borrow is generated then

carry flag is set otherwise carry flag resets. It is used in arithmetic, logical, jump, rotate

and Boolean operations.

● Auxiliary carry flag(AC): If during addition and subtraction any carry or borrow is

generated from lower 4 bit to higher 4 bit then AC sets else it resets. It is used in BCD

arithmetic operations.

● Overflow flag(OV): If in signed arithmetic operations result exceeds more than 7 bit

than OV flag sets else resets.It is used in signed arithmetic operations only.

● Parity flag(P): If in result, even no. Of ones "1" are present than it is called even parity

and parity flag sets. In result odd no. Of ones "1"are present than it is called odd parity

and parity flag resets.

Memory Organization:

The 8051 has two types of memory:

● Program Memory (ROM): Used to store the program code. Early models used external
memory for this purpose, but later versions included internal ROM.
● Data Memory (RAM): Used for storing data and intermediate results. The internal RAM
is divided into three main areas:
○ Working Registers: 32 bytes from 00h to 1Fh.
○ Bit-Addressable Area: 16 bytes from 20h to 2Fh.
○ General-Purpose RAM: 80 bytes from 30h to 7Fh.

Instruction set of 8051

1. Data Transfer Instructions

These instructions are used to move data from one place to another within the microcontroller.
The common data transfer instructions include:

● MOV dest, src: Move data from source to destination.

○ Example: MOV A, #0x25 (Move immediate value 25h to the accumulator A).
● MOVC A, @A+DPTR: Move code byte relative to DPTR and Accumulator.
● MOVX A, @DPTR: Move external data pointed by DPTR to the Accumulator.
● PUSH direct: Push the direct byte onto the stack.
● POP direct: Pop the byte from the stack to the direct address.

2. Arithmetic Instructions

These instructions perform arithmetic operations such as addition, subtraction, multiplication,

and division.

● ADD A, src: Add the source operand to the accumulator.

○ Example: ADD A, R0 (Add the contents of register R0 to the accumulator).
● ADDC A, src: Add with carry the source operand to the accumulator.
● SUBB A, src: Subtract the source operand and the carry flag from the accumulator.
● MUL AB: Multiply A and B and store the result in A and B.
● DIV AB: Divide A by B and store the quotient in A and remainder in B.
● INC dest: Increment the destination operand by 1.
● DEC dest: Decrement the destination operand by 1.

3. Logical Instructions

These instructions are used for bitwise logical operations, including AND, OR, XOR, and rotate
operations.

● ANL dest, src: Perform bitwise AND operation between source and destination.
○ Example: ANL A, R1 (AND the contents of R1 with the accumulator).
● ORL dest, src: Perform bitwise OR operation between source and destination.
● XRL dest, src: Perform bitwise XOR operation between source and destination.
● CLR A: Clear the accumulator.
● CPL A: Complement the bits of the accumulator.
● RL A: Rotate the bits of the accumulator left.
● RLC A: Rotate the bits of the accumulator left through the carry.
● RR A: Rotate the bits of the accumulator right.
● RRC A: Rotate the bits of the accumulator right through the carry.

4. Control Instructions

Control instructions are used for controlling the flow of the program, including jumps, calls, and
returns.
 ● ACALL addr11: Absolute call to a subroutine within the same 2K block.
● LCALL addr16: Long call to a subroutine located anywhere in the 64K code memory.
● LJMP addr16: Long jump to any location in the 64K code memory.
● SJMP rel: Short jump relative to the current PC.
● JZ rel: Jump if the accumulator is zero.
● JNZ rel: Jump if the accumulator is not zero.
● CJNE dest, src, rel: Compare and jump if not equal.
● DJNZ reg, rel: Decrement the register and jump if not zero.

5. Bit Manipulation Instructions

These instructions are used to operate on individual bits in the registers or memory.

● SETB bit: Set the specified bit to 1.

○ Example: SETB P1.0 (Set bit 0 of port 1 to 1).
● CLR bit: Clear the specified bit to 0.
● CPL bit: Complement the specified bit.
● ANL C, bit: AND the carry bit with the specified bit.
● ORL C, bit: OR the carry bit with the specified bit.
● MOV C, bit: Move the specified bit to the carry.
● MOV bit, C: Move the carry to the specified bit.

6. Boolean (Bit-Level) Operations

These instructions provide direct control over the individual bits, allowing detailed and efficient
manipulation of data.

● JB bit, rel: Jump if the specified bit is set.

○ Example: JB P1.0, LABEL (Jump to LABEL if bit 0 of port 1 is set).
● JNB bit, rel: Jump if the specified bit is not set.
● JBC bit, rel: Jump if the specified bit is set, and then clear the bit.

7. Miscellaneous Instructions

These include other operations that do not fit into the above categories.

● NOP: No operation. Used for creating delays or for timing adjustments.

● SWAP A: Swap the nibbles within the accumulator.
● DA A: Decimal adjust the accumulator after addition.

Interrupt System:
The 8051 has a robust interrupt system that allows it to handle external and internal events
efficiently. The interrupt system can pause the main program, execute a predefined routine, and
then resume the program. Key features include:

● Interrupt Priority: Higher-priority interrupts can override lower-priority ones.

● External Interrupts: Triggered by external signals, useful for responding to hardware
events.
● Timer Interrupts: Triggered by the internal timers reaching a specified value.
● Serial Interrupt: Triggered by the completion of a serial communication operation.