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31 views4 pages

Term Project

Uploaded by

knight hollow
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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11310PME 320200 Electronics II Term Project

Due date: 2024/12/27 23:59

⚫ Design a folded differential amplifier (Using rfml018.l as the library file)


Consider the folded differential amplifier in fig.1. VDD=1.8V, VSS=0V, CL=10pF,
and RL=1MΩ. Please design IBias and the sizes of all transistors to satisfy the
following specifications.
Table. 1
Specifications Units
Pdiss ≤ 600 μW
DC characteristics ICMR: 𝑉𝑖𝑛,𝑚𝑖𝑛 ≤ 0.7; 𝑉𝑖𝑛,𝑚𝑎𝑥 ≥ 1.2 V
Vout,min ≤ 0.4; Vout,max ≥ 1.4 V
AV ≥ 40 dB
𝑓3𝑑𝐵 ≥ 100 kHz
AC characteristics PM ≥ 60 °
PSRR(@1kHz) ≥ 30 dB
CMRR(@1kHz) ≥ 30 dB
Transient characteristics Slew rate ≥ 10 V/μs

Fig.1
1. Estimate the value of the Level-1 parameters in Table.2 for both NMOS and
PMOS transistors according to the equations in Table.2, parameters in Table. 3
and your library file (rfml018.l). Please give the units for the parameters in your
report.(Hint : Select nch.1 and pch.1 models, which you may use in your design,
from the Spice file. The models in the Spice file are BSIM3. Refer to the manual
of SPICE for explanation on parameters in the models)
Table. 2 Level-1 parameters of a MOS transistor

Table. 3 Silicon constants

2. Design Ibias and W/L of all the transistors by hand calculation.


(Using parameters extracted from question 1.)
(Please elaborate on the calculation of each answer and make a table like below)
Number W(μm) L(μm) m W/L
M1
M2
M3
3. Use SPICE to check whether all specifications are satisfied. If not, redesign
your circuit to meet the specifications and explain all the adjustments you
made. The following results before and after adjustment must be included in your
report.
(a) For ICMR, connect the amplifier as the configuration in Fig.2 when VDD =
1.8V. Plot vOUT v.s. vIN and ID(M5) v.s. vIN. Mark explicitly the input-common
mode range in the plot. Set v1 = v2 = 0.7V &1.2V. Use .op to check whether
the all transistors operate in the saturation region. Include the summary of
transistor operation in your report.
Fig. 2 Plot of ICMR
(b) With VDD=1.8V. Print out power dissipation and the biasing condition of
M1-M7 for (i) v1=v2=1.2V (ii)v1=v2=0.7V
(c) With VDD=1.8V. Connect the amplifier as the configuration in Fig. 3. Plot vout
vs. vin. Mark explicitly the output dynamic range in the plot.

Fig. 3 Plot of output dynamic range


(d) Plot the open-loop frequency response (both magnitude and phase) of the
amplifier. Mark explicitly Av, f3dB, UGB, PM in the plot.
(e) Plot the frequency of the PSRR+ and PSRR- of the Op-amp.
(f) Plot the frequency response of the CMRR of the Op-amp.
(g) With v1 and v2 connected to the signals in Fig. 4 (2µs pulse signal with rising
and falling of 10ns). Plot vout vs. time. According to the result, calculate the
positive and negative slew rates of the amplifier.

Fig. 4 Input signal for testing of slew rate


(h) Give a table of the size of each transistor after satisfying all the specifications.
Number W(μm) L(μm) m W/L
M1
M2
M3
* Also provide the final value of Ibias and power dissipation.
4. Summarize the specifications of the amplifier in the table of the following form.
Specifications Simulation Units
Pdiss ≤ 600 μW
DC characteristics ICMR: 0.7~1.2 V
Vout range: 0.4~1.4 V
AV ≥ 40 dB
𝑓3𝑑𝐵 ≥ 100 kHz
AC characteristics PM ≥ 60 °
PSRR(@1kHz) ≥ 30 dB
CMRR(@1kHz) ≥ 30 dB
Transient
Slew rate ≥ 10 V/μs
characteristics
5. Please submit your netlist file (*.netlist) and report (*.PDF) to the eeclass System.
Note that your design will be a Spice sub-circuit that we will include in our test
circuits. Therefore, your netlist should provide everything in the Op-amp as
shown in Fig.5 and use EXACTLY the SAME node names in Fig.5. Your sub-
circuit syntax will be as follows:

.subckt opamp <pi> <ni> <o> <vdd> <gnd>


*Your amp goes here
.ends opamp

Fig.5 Operational amplifier sub-circuit

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