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7 views15 pages

Slide 04

Uploaded by

ravi.alwar200
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Introduction to VHDL

What is VHDL
● VHSIC Hardware Description Language.
● VHSIC: Very High Speed Integrated Circuit

● Developed by US Department of Defense

● Language syntax and structure are based on Ada

● Standardized in 1987 (IEEE 1076)

● Used to describes behavior and/or structure of digital


circuits.
What is VHDL (cont'd)

● Output is configuration of the actual connections in the


chip (FPGAs, CPLDs, ASICs)

● VHDL code may contain concurrent and/or sequential


and sequential statements.

● Case insensitive (except std logic value 'X', 'Z', etc.)


Design Flow

● Design Entry → Code

● Compilation (synthesis) → netlist

● Functional and Timing Simulation

● Programming (place and route)

● I/O mapping

● Testing
Design Example
● Full Adder Design and Implementation
● Always draw a block diagram conceptualizing the

entity.

S = A  B Cin

Cout = (A · B) + (Cin · (A B)


Design Example

● Design Implementation In VHDL


ENTITY full_adder IS
PORT (
Describe
a, b, cin: IN STD_LOGIC; input and
s, cout: OUT STD_LOGIC output
);
END full_adder;
ARCHITECTURE dataflow OF full_adder IS
BEGIN Describe
s <= a XOR b XOR cin; Internal
detail
cout <= (a AND b) OR (cin AND (a XOR b));
END dataflow;
VHDL Structure
● Three Fundamental Language Structures
VHDL Structure: LIBRARY
● LIBRARY declarations:
– Contains a list of all libraries to be used in the design. For example:
ieee, std, work, etc
– A LIBRARY is collection of commonly used pieces of code. Placing
such pieces inside a library allows them to be reused or shared by
other designs.
● Typical Library Structure
LIBRARY library_name;
USE library_name.package_name.package_parts;

● Example Library Declaration

LIBRARY ieee;
USE ieee.std_logic_1164.all;

NOTE: std_logic_1164 package is required for multi-level logic as opposed to binary logic.
VHDL Structure: LIBRARY

● What is inside Libraries?


VHDL Structure: LIBRARY

● Other Available IEEE library packages:


● std_logic_arith: Specifies the SIGNED and UNSIGNED data
types and related arithmetic and comparison operations. It
also contains several data conversion functions, which allow
one type to be converted into another: conv_integer(p),
conv_unsigned(p, b), conv_signed(p, b),
conv_std_logic_vector(p, b) etc.
● std_logic_signed: Contains functions that allow operations
with STD_LOGIC_VECTOR data to be performed as if the
data were of type SIGNED.
● std_logic_unsigned: Contains functions that allow
operations with STD_LOGIC_VECTOR data to be performed
as if the data were of type UNSIGNED.
VHDL Structure:Entity
● An ENTITY is a list with specifications of all input and output
pins (PORTS) of the circuit.
● Syntax
ENTITY entity_name IS
PORT ( port_name : signal_mode signal_type;
port_name : signal_mode signal_type;
…
);
END entity_name;

● Mode of the signal can be IN, OUT, INOUT


● type of the signal can be BIT, STD_LOGIC, INTEGER, etc
● Top level entity name must always be the same as project
name
VHDL Structure:Entity

● ENTITY Example: Two input NAND gate:

ENTITY nand_gate IS
PORT ( a, b : IN BIT;
x : OUT BIT );
END nand_gate;
VHDL Structure:Architecture

● An ARCHITECTURE is a VHDL description of how the circuit


behaves.
● Syntax:
ARCHITECTURE architecture_name OF entity_name IS
[declarations]
BEGIN
(code)
END architecture_name;
● Declarative part is optional (optional)
● Used to declare internal signals and constants (among
others)
● Name of architecture can be any (not VHDL reserved words)
VHDL Structure:Architecture

● Architecture Example:Two input NAND gate:

X = ab

ARCHITECTURE myarch OF nand_gate IS


BEGIN
x <= a NAND b;
END myarch;
VHDL Structure:Comments

● Two or more dashes indicate start of a comment

-- This is an indication of a comment in VHDL

– Use comment as many as possible to describe your code

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