State Machines

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 Introduction to State Machine
● State Machine or Finite State Machine (FSM) is a tool used for
modeling the behavior of systems.
● State machine describes how the system reacts to inputs i.e,
the outputs that will be generated, the state that the system
● State machine can be used to model a simple digital circuit to
complicated circuit such as microprocessors.
● State machine can be represented using state table or state
diagram

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 Introduction to State Machine
● Example of systems :
● Counters, traffic light controller, digital alarm clock, lift
controller, vending machine controller, etc.

Input Output

clk

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 Introduction to State Machine
● Suppose that we have a system with 1 input and 1 output
● Our system has 4 operating states, but can be in only 1 state
at a time
● Output will be generated depending on received input or
both of input and current state

Input Output

clk

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 State Table
● State table is a straightforward way of describing a state machine
● It consists of columns where all possible states are listed and
rows that lists all possible inputs.
● At cross-points, the next states that the system will be in
corresponding to input and the current state are indicated.
Current State S1 S2 S3 S4
Input
a S2 - - S2
b - S3 - -
c - - S4 -
d - - S3 -
e - - - S1
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 State Table
● Output of the system depends on current state

State S1 S2 S3 S4

Output W X Y Z

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 State Diagram
● An alternative method for describing state machines using graphical
representation.
● State diagram consists of:
– Circles which represent states
– Arrows which represent transitions between states
– Specified input that creates state transition
– Output to be generated
S2
input
input output input

S1 S3
output input
output

input
S4 input
output

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 State Machine
● There are two types of state machines:
– Moore machine --> Outputs depend on current state

– Mealy machine --> Outputs depend on current state and input

• Moore machine:
Y =  (Z)

Z+ =  (X, Z)
• Mealy machine:
Y =  (X, Z)

Z+ =  (X, Z)

Y ← outputs Z ← current state  () ← output function

+
X ← inputs Z ← next state  () ← state function
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 Moore Machine
Moore machine --> Output depends on current state only

S1 input = e
S3
--------- --------
output=p output=r

input = a
input = f
input = c

S4 S2
---------- ---------- input = b
input = d output=q
output=s

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 Mealy Machine
Mealy machine --> Output depends on current state and input

input = e
/output = x
S1 S3

input = a
input = f /output = y input = c
/output = v /output = w

input =e
S4 S2 /output = u
input = d
/output = z

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 VHDL User-Defined Data Type
● VHDL has predefined data types, for example:
TYPE bit IS ('0', '1'); -- predefined type in provided package
SIGNAL d, q : bit; -- using predefined type
● Users are allowed to define their own data types, for example:
TYPE operation_mode IS (off, on, standby);
SIGNAL mode : operation_mode;
SIGNAL sw : bit;
.........
mode <= off;
IF (mode = off AND sw = '1') THEN
mode <= on;
END IF;

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 VHDL User-Defined Data Type
● In our case, we need to define a new data type
TYPE state IS (S1, S2, S3, S4);
SIGNAL CurrentState : state;
● Now we can use CurrentState as follows:
IF (CurrentState = S1) THEN
IF(input = '1') THEN
CurrentState <= S2;
END IF;
END IF

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 Moore Machine VHDL Example
ENTITY MooreMachine IS
PORT(input, clk, reset : IN std_logic; OutputControl: PROCESS(CurrentState)
output : OUT std_logic_vector(1 downto 0)); BEGIN
END MooreMachine; IF (CurrentState = S1) THEN
output <= "00";
ARCHITECTURE behavior of MooreMachine IS ELSIF (CurrentState = S2) THEN
TYPE FSM_state IS (S1, S2, S3, S4); output <= "01";
SIGNAL CurrentState : FSM_state := S1; ELSIF (CurrentState = S3) THEN
BEGIN output <= "10";
StateControl: PROCESS(clk, reset) ELSIF (CurrentState = S4) THEN
BEGIN output <= "11";
IF (reset = '1') THEN END IF;
CurrentState <= S1; END PROCESS OutputControl;
ELSIF (clk'EVENT AND clk = '1') THEN END behavior;
IF (CurrentState = S1) THEN
IF (input = '1') THEN
CurrentState <= S2;
END IF;
ELSIF (CurrentState = S2) THEN S1 1 S2
IF (input = '0') THEN ---- ----
CurrentState <= S3; 00 01
END IF;
ELSIF (CurrentState = S3) THEN 0
IF (input = '1') THEN 0
CurrentState <= S4;
END IF; S3
ELSIF (CurrentState = S4) THEN
S4 ----
----
IF (input = '0') THEN 11 10
CurrentState <= S1; 1
END IF;
END IF;
END IF; 13
END PROCESS StateControl;
 Mealy Machine VHDL Example
ENTITY MealyMachine IS OutputControl: PROCESS(CurrentState, input)
PORT(input, clk, reset : IN std_logic; BEGIN
output : OUT std_logic_vector(1 downto 0)); IF (CurrentState = S1) THEN
END MealyMachine; IF (input = '1') THEN
output <= "00";
ARCHITECTURE behavior of MealyMachine IS END IF;
TYPE FSM_state IS (S1, S2, S3, S4); ELSIF (CurrentState = S2) THEN
SIGNAL CurrentState : FSM_state; IF (input = '0') THEN
BEGIN output <= "01";
StateControl: PROCESS(clk, reset) END IF;
BEGIN ELSIF (CurrentState = S3) THEN
IF (reset = '1') THEN IF (input = '1') THEN
CurrentState <= S1; output <= "10";
ELSIF (clk'EVENT AND clk = '1') THEN END IF;
IF (CurrentState = S1) THEN ELSIF (CurrentState = S4) THEN
IF (input = '1') THEN IF (input = '0') THEN
CurrentState <= S2; output <= "11";
END IF; END IF;
ELSIF (CurrentState = S2) THEN END IF;
IF (input = '0') THEN END PROCESS OutputControl;
CurrentState <= S3; END behavior;
END IF;
ELSIF (CurrentState = S3) THEN S1 S2
IF (input = '1') THEN
CurrentState <= S4; 1/00
END IF;
ELSIF (CurrentState = S4) THEN 0/01
IF (input = '0') THEN 0/11
CurrentState <= S1;
END IF; S3
END IF;
S4 1/10
END IF; 14
END PROCESS StateControl;
 Examples of state machine
● A simple 3-floor lift controller modeling
Lift can be in any floor
Si - in floor ith
Request can come from any floor 3rd Floor
Ri - request from floor ith

Lift can be asked to move up or down

2nd Floor
u , d - up/down by n floors
n n

3
2
1st Floor
1

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 Examples of state machine
● Elevator controller modeling
R2/-

3rd Floor

S2

R3/U1 2nd Floor

R2/U1

R1/D1 R2/D1 3
2
1st Floor
R3/U2 1
S1 S3
R1/D2
R3/-
R1/-

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 Examples of state machine
● Next step is to assign binary code to all inputs and outputs
R1 = 01
R2 = 10
} input R2/-

}
R3 = 11
D1 = 001
D2 = 010 S2

U1 = 011 output
R3/U1
R2/U1
U2 = 100
R1/D1
No Go = 111 R2/D1

● Input must be synchronized

R3/U2
to clock signal S1 S3
R1/D2
R3/-
R1/-
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