Digital circuit implementation


Programmable logic devices

CPLDs

FPGAs
 Programmable Logic

Programmable Logic Devices (PLDs) are ICs with a large

number of gates and flip flops that can be configured with
basic software to perform a specific logic function or perform
the logic for a complex circuit. Major types of PLDs are:
SPLD: (Simple PLDs) are the earliest type of array logic used for
fixed functions and smaller circuits with a limited number of gates.
(The PAL and GAL are both SPLDs).
CPLD: (Complex PLDs) are multiple SPLDs arrays and inter-
connection arrays on a single chip.
FPLD: (Field Programmable Gate Array) are a more flexible
arrangement than CPLDs, with much larger capacity.

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 Programmable Logic

Advantages to PLDs include

 Reduced complexity of circuit boards
• Lower power requirements
• Less board space
• Simpler testing procedures
 Higher reliability
 Design flexibility

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 PALs and GALs

All PLDs contain arrays. Two important SPLDs are PALs

(Programmable Array Logic) and GALs (Generic Array
Logic). A typical array consists of a matrix of conductors
connected in rows and columns to AND gates.
A A B B
PALs have a one time
programmable (OTP)
array, in which fuses are
X
permanently blown,
creating the product
terms in an AND array.

Simplified AND-OR array

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 PALs and GALs

All PLDs contain arrays. Two important SPLDs are PALs

(Programmable Array Logic) and GALs (Generic Array
Logic). A typical array consists of a matrix of conductors
connected in rows and columns to AND gates.
A A B B
PALs have a one time
programmable (OTP)
array, in which fuses are
X
permanently blown,
creating the product
terms in an AND array.

Simplified AND-OR array

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 PALs and GALs

The GAL (Generic Array Logic) is similar to a PAL but can

be reprogrammed. For this reason, they are useful for new
product development (prototyping) and for training purposes.
A A B B

GALs were developed by

Lattice Semiconductor.
They are high speed,
X
extremely fast devices
and can interface with
both 3.3 V or 5 V logic
signals.

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 PALs and GALs

PALs and GALs can be represented with a simplified

diagram. A single line can represent multiple gate inputs. The
logic shown is for the XOR gate, given previously.
Input buffer A A B B
Single line with slash
indicating multiple AND
gate inputs

Fuse blown
2 AB
X X
Fuse intact AB + AB

X X 2
AB

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 PALs and GALs

PALs and GALs have large array logic and include output
logic that varies in complexity. The output logic is connected
to each OR gate and together is referred to as a macrocell.
Two types of PAL/GAL macrocells are shown. For these
particular macrocells, the I/O pins can serve as an input or an
output. Tristate control

From From
AND I/O AND I/O
array array
To AND To AND
array array
Programmable fuse link to
control output polarity

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 CPLDs
A complex programmable logic device (CPLD) has
multiple logic array blocks (LABs) that are actually SPLDs
on a single IC. LABs are connected via a programmable
interconnect array (PIA). Various CPLDs have different
structures for these elements.

Logic array Logic array

I/O block (LAB) block (LAB) I/O
SPLD SPLD

PIA
Logic array Logic array
I/O block (LAB) block (LAB) I/O
SPLD SPLD

Logic array Logic array

I/O block (LAB) block (LAB) I/O
SPLD SPLD
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 CPLDs

The PIA is the interconnection between the LABs. Logic is

fitted to the CPLD and routing is determined by a high-level
programming language called a hardware description language
(HDL).

Logic array Logic array

I/O block (LAB) block (LAB) I/O
SPLD SPLD

PIA
Logic array Logic array
I/O block (LAB) block (LAB) I/O
SPLD SPLD

Logic array Logic array

I/O block (LAB) block (LAB) I/O
SPLD SPLD

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 CPLDs

The architecture of a CPLD is the way in which the internal

elements are configured. A portion of the Altera MAX 7000
series is shown. This structure is typical for CPLDs although
densities, size, speed, and internal factors (macrocells, etc) will
vary between manufacturers.
General-purpose inputs
I/O Logic array block PIA Logic array block I/O
control (LAB A) (LAB B) control
block block
I/O pins I/O pins
Macrocell 1 Macrocell 1

8Ð16 Macrocell 2 36 36 Macrocell 2 8-16

16 16

Macrocell 16 Macrocell 16
8-16 8-16

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 CPLDs

Macrocells in the Altera MAX 7000 series can generate up to

five product terms. For expressions requiring more terms, the
output can be expanded as described in the text.

Parallel expanders
from other
macrocells

Product-term To I/O
Associated
selection control
matrix logic
block

Expander example
A
B
Shared C ABC(E + F)=ABCE + ABCF
expander

36 lines from PIA 15 expander E +F

product terms EF Product term from another
from other macrocell in same LAB
macrocells

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 Macrocells

In addition to combination logic, some macrocells have

registered outputs available (using programmable flip-
flops). This allows the CPLD to perform sequential logic.
Global Global
Parallel expanders clear clock
from other
macrocells
From
MUX 5 I/O

To I/O
MUX 1 PRE
D/T Q
Product-
term C
selection
matrix MUX 2 EN
CLR

VCC MUX 3
Shared
expander

MUX 4

36 lines 15 expander product

from PIA terms from other
macrocells

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 FPGAs

A field programmable gate array (FPGA) uses a different

architecture than a CPLD. The configurable logic block
(CLB) is the basic element which is replicated many times.

CLBs are arranged in a row

and column structure. Within
CLB CLB
the CLBs are logic modules Logic module Logic module

joined by local interconnects. Logic module Logic module

Generally, the logic modules Logic module Logic module

are composed of a look-up Local

interconnect
Local
interconnect
table (LUT), a flip-flop, and a
Logic module Logic module
MUX that can be used to
bypass the flip-flop for
strictly combinational logic. Global column Global row
interconnect interconnect

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 FPGAs

Logic modules can be configured for combinational logic,

registered logic, or a combination of both. The global
interconnects distribute signals (including the clock) to
various CLBs.

FPGAs may also have a

CLB CLB
hard core portion of logic Logic module Logic module

that is put in by the Logic module Logic module

manufacturer and cannot Logic module Logic module

be reprogrammed by the Local

interconnect
Local
interconnect
user. These FPGAs are
Logic module Logic module
useful in commonly used
functions such as I/O
interfaces. Global column Global row
interconnect interconnect

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 Programmable Logic Software
All manufacturers of programmable logic provide software
to support their products. The process is illustrated in the
flowchart.

Design entry
The first step is to enter Schematic
the logic design into HDL
a computer. It is done Synthesis
in one of two ways:
Timing
1) Schematic entry Functional simulation
2) Hardware description simulation
language (HDL).
Implementation
Device
programming
(downloading)

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 Programmable Logic Software
In schematic entry, the design is drawn on a computer screen by
placing components and connecting then with simulated wires. You do
not need to know the details of an HDL. After drawing the schematic,
it can be reduced to a single block symbol:

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 Programmable Logic Software

In text entry, the design is entered via a hardware

description language such as VHDL or Verilog.

VHDL has two key parts: the entity and A

the architecture. The entity section LED 1
describes the inputs, outputs, and
variables. The architecture section
describes the relationships between B
variables using Boolean equations. The
VHDL equation can be understood, even
if you do not know VHDL.
C
D

For example, the VHDL expression for LED1 is written as

LED1 <= ((D XOR C) XOR B) XOR A;

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 Programmable Logic Software

VHDL allows you to describe components in one

program and then use them in another program.
For example, an active-LOW S-R latch can be drawn as

S Q Q
A

Q QNot
B R

The complete VHDL program for this component is shown on the

following slide…..

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 Programmable Logic Software
S Q
A Q

Q QNot
B R

Entity entity S_RLatch is

section port (A, B: in bit; Q, QNot: inout bit);
end entity S_RLatch; Input and output variable
names and types

Architecture architecture Behavior of S_RLatch is

section begin
Q <= not A or not QNot;
QNot <= not B or not Q;
} Boolean descriptions
of circuit
end architecture Behavior;
Assigns expression on
right to variable on left
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 Functional Simulation

After entering the circuit into an HDL (such as VHDL),

the circuit is tested in a functional simulation. The
functional simulation is part of the HDL. You can test
the circuit with waveforms to verify the operation.
The following shows the functional test of a counter
using a waveform editor:

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 Synthesis
After the simulation, the computer program optimizes
the logic by eliminating redundant terms and generating
a netlist, (a connection list) that is a complete
description of the circuit.
net1
net2 net5
net3 and1
Netlist (Logic3)
net4 net<name>: instance<name>, <from>; <to>;
net6 instances: and1, and2, and3, and4, and5, or1, inv2,
and2 net10
inv3, inv4;Netlist
net7
Input/outputs: I1, I2, I3, I4, O1;
net9 net8 net1: and1, inport1; I1;
net11 net2: and1, inport2; I2;
inv1 O1
I1 net12 and3 net15 or1 Z net3: and1, inport3; I3;
net14 net26 net4: and1, inport4; I4;
A0
net13 net5: and1, outport1; or1, inport1;
inv2 net6: and2, inport1; I1;
I2 net16
net17 net20 net7: and2, inport2; I3;
A1 net18 and4 net8: and2, inport3; inv2,outport1
inv3 net19 net9: and2, inport4; inv4,outport1
I3 net10: and2, outport1; or1,inport2;
net23
A2 net11: and3, inport1; inv2,outport1
net21 net12: and3, inport2; inv3,outport1
inv4 net22 and5 net25 net13: and3, inport3; I4;
I4
A3 net14: and3, inport4; I1;
net24
5: and3

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 Implementation

The computer next “maps” the design from the netlist to

fit it to a target device. Data for all potential target
devices are in a software library. The computer must
account for the I/O pins and fit the logic to the target
device.

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 Timing Simulation
After implementation, a timing simulation is done that
takes into account the specific delays in the target device
and verifies that there no problems with the timing. As in
the case of the functional simulation, the waveform editor
can be used to review final timing.

Waveform Editor

Name: 1 s 4 s 8 s 12 s 16 s
If a problem is revealed, it is
A0 0
not too late to correct it A1 0

before downloading the file. A2 0

A3 0
Glitch
Z X

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 Device Programming

The final step is to send the programming file from the

computer to the target device and test the implementation.

A PLDT-2 prototyping board

that has an Altera PLD as the
target device is shown.
Connections are added to the
board from a pulse generator
and oscilloscope to test the
actual circuit in a laboratory
environment. The prototyping
board has built-in power
supplies, interfacing, I/O, and
more.

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