Review of digital electronics


Storage units

Sequential circuits

Counters

Shifters
 Counting in Binary

A counter can form the same pattern of 0’s and 1’s with
logic levels. The first stage in the counter represents the
least significant bit – notice that these waveforms
follow the same pattern as counting in binary.

LSB 0 1 0 1 0 1 0 1 0

0 0 1 1 0 0 1 1 0

MSB 0 0 0 0 1 1 1 1 0

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 Latches

A latch is a temporary storage device that has two stable

states (bistable). It is a basic form of memory.
The S-R (Set-Reset) latch is the most basic type. It can be constructed
from NOR gates or NAND gates. With NOR gates, the latch responds
to active-HIGH inputs; with NAND gates, it responds to active-LOW
inputs.
R S
Q Q

Q Q
S R

NOR Active-HIGH Latch NAND Active-LOW Latch

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 Latches

The active-HIGH S-R latch is in a stable (latched) condition

when both inputs are LOW.
0 R 0
Assume the latch is initially RESET Q
(Q = 0) and the inputs are at their Latch
inactive level (0). To SET the latch initially
(Q = 1), a momentary HIGH signal RESET
is applied to the S input while the R Q
0 S
remains LOW. 1

To RESET the latch (Q = 0), a

momentary HIGH signal is
applied to the R input while the S
remains LOW.

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 Latches

The active-LOW S-R latch is available as the 74LS279A IC.

It features four internal latches with (2)
1S1
two having two S inputs. To SET any (3) (4) 1Q
1S2
of the latches, the S line is pulsed low. (1)
1R
It is available in several packages. (6)
2S (7)
S-R latches are frequently used for 2Q
(5)
2R
switch debounce circuits as shown:
VCC (11)
3S1
(12) (9) 3Q
3S2
(10)
3R
(15)
2 S Q 4S (13)
S (14)
4Q
4R
R R Position Position
1 1 to 2 2 to 1
74LS279A

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 Latches

A gated latch is a variation on the basic latch.

The gated latch has an additional S
Q
input, called enable (EN) that must
be HIGH in order for the latch to
EN
respond to the S and R inputs.
Show the Q output with Q
relation to the input signals. R
Assume Q starts LOW.
Keep in mind that S and R are only active when EN is HIGH.
S
R
EN
Q

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 Latches

The D latch is an variation of the S-R latch but combines

the S and R inputs into a single D input as shown:

D D Q
Q
EN EN
Q
Q

A simple rule for the D latch is:

Q follows D when the Enable is active.

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 Latches

The truth table for the D latch summarizes its operation. If

EN is LOW, then there is no change in the output and it is
latched.

Inputs Outputs
D EN Q Q Comments
0 1 0 1 RESET
1 1 1 0 SET
X 0 Q0 Q0 No change

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 Latches

D Q

EN
Determine the Q output for the
Q
D latch, given the inputs shown.

EN

Notice that the Enable is not active during these times, so

the output is latched.

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 Flip-flops

A flip-flop differs from a latch in the manner it changes

states. A flip-flop is a clocked device, in which only the
clock edge determines when a new bit is entered.
The active edge can be positive or negative.
D Q D Q

C C

Dynamic Q Q
input
(a) Positive edge­triggered (b) Negative edge­triggered
indicator

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 Flip-flops

The truth table for a positive-edge triggered D flip-flop

shows an up arrow to remind you that it is sensitive to its
D input only on the rising edge of the clock; otherwise it is
latched. The truth table for a negative-edge triggered D
flip-flop is identical except for the direction of the arrow.

Inputs Outputs Inputs Outputs

D CLK Q Q Comments D CLK Q Q Comments

1 1 0 SET 1 1 0 SET
0 0 1 RESET 0 0 1 RESET

(a) Positive-edge triggered (b) Negative-edge triggered

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 Flip-flops

The J-K flip-flop is more versatile than the D flip flop. In

addition to the clock input, it has two inputs, labeled J and
K. When both J and K = 1, the output changes states
(toggles) on the active clock edge (in this case, the rising
edge).
Inputs Outputs
J K CLK Q Q Comments
0 0 Q0 Q0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q0 Q0 Toggle

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 Flip-flops

J Q

CLK
Determine the Q output for the J-K
flip-flop, given the inputs shown. K Q

Notice that the outputs change on the leading edge of the clock.

Set Toggle Set Latch

CLK

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 Flip-flop Characteristics

Propagation delay time is specified for the rising and

falling outputs. It is measured between the 50% level of the
clock to the 50% level of the output transition.
50% point on triggering edge

CLK CLK 50% point

Q 50% point on LOW-to- Q 50% point on HIGH-to-

HIGH transition of Q LOW transition of Q

tPLH tPHL

The typical propagation delay time for the 74AHC family (CMOS)
is 4 ns. Even faster logic is available for specialized applications.

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 Flip-flop Characteristics

Set-up time and hold time are times required before and
after the clock transition that data must be present to be
reliably clocked into the flip-flop.
D
Setup time is the minimum
time for the data to be present CLK
before the clock.
Set-up time, ts

D
Hold time is the minimum
time for the data to remain after CLK
the clock.

Hold time, tH

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 Flip-flop Applications

Output
lines
Q0
Principal flip-flop applications are for
D

temporary data storage, as frequency R

dividers, and in counters (which are D Q1

covered in detail in Chapter 8). C

Q2
Typically, for data storage applications, D

a group of flip-flops are connected to Parallel data

C

parallel data lines and clocked together. input lines R

Data is stored until the next clock pulse. D Q3

Clock C

R
Clear

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 Flip-flop Applications

For frequency division, it is simple to use a flip-flop in

the toggle mode or to chain a series of toggle flip flops to
continue to divide by two. HIGH HIGH

One flip-flop will divide fin

J QA J QB fout
by 2, two flip-flops will
divide fin by 4 (and so on). fin CLK CLK
A side benefit of frequency
division is that the output K K
has an exact 50% duty fin
cycle.
Waveforms:
fout

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 Counting in Binary

A counter can form the same pattern of 0’s and 1’s with
logic levels. The first stage in the counter represents the
least significant bit – notice that these waveforms
follow the same pattern as counting in binary.

LSB 0 1 0 1 0 1 0 1 0

0 0 1 1 0 0 1 1 0

MSB 0 0 0 0 1 1 1 1 0

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 Three bit Asynchronous Counter

In an asynchronous counter, the clock is applied only to

the first stage. Subsequent stages derive the clock from
the previous stage.
The three-bit asynchronous counter shown is typical. It uses J-K
flip-flops in the toggle mode.

HIGH

J0 Q0 J1 Q1 J2 Q2

CLK C C C
Q0 Q1
K0 K1 K2

Waveforms are on the following slide…

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 Asynchronous Decade Counter

This counter uses partial decoding to recycle the count

sequence to zero after the 1001 state. The flip-flops are
trailing-edge triggered, so clocks are derived from the
Q outputs. Other truncated sequences can be obtained
using a similar technique.
CLR
HIGH

Q0 Q1 Q2 Q3
J0 J1 J2 J3

CLK C C C C

K0 K1 K2 K3

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 Asynchronous Decade Counter

When Q1 and Q3 are HIGH together, the counter is

cleared by a “glitch” on the CLR line.
1 2 3 4 5 6 7 8 9 10
CLK
Q0

Q1 Glitch
Glitch

Q2

Q3

CLR
Glitch
Glitch

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 Synchronous Counters

In a synchronous counter all flip-flops are clocked

together with a common clock pulse. Synchronous
counters overcome the disadvantage of accumulated
propagation delays, but generally they require more
circuitry to control states changes.
HIGH Q0
This 3-bit binary
Q0Q1
synchronous counter Q0 Q1 Q2
J0 J1 J2
has the same count
sequence as the 3-bit C C C

asynchronous counter K0 K1 K2

shown previously. CLK

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 Analysis of Synchronous Counters

A tabular technique for analysis is illustrated for the counter on the

previous slide. Start by setting up the outputs as shown, then write
the logic equation for each input. This has been done for the counter.
1. Put the counter in an 2. Use the new inputs to 3. Set up the next
arbitrary state; then determine determine the next state: Q2 and group of inputs from
the inputs for this state. Q1 will latch and Q0 will toggle. the current output.

Outputs Logic for inputs

Q2 Q1 Q0 J2 = Q0Q1 K2 = Q0Q1 J1 = Q0 K1 = Q0 J0 = 1 K0 = 1
0 0 0 0 0 0 0 1 1
0 0 1 0 0 1 1 1 1
0 1 0
4. Q2 will latch again but both Q1 and Q0 will toggle.

Continue like this, to complete the table.

The next slide shows the completed table…

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 Analysis of Synchronous Counters

Outputs Logic for inputs

Q2 Q1 Q0 J2 = Q0Q1 K2 = Q0Q1 J1 = Q0 K1 = Q0 J0 = 1 K0 = 1
0 0 0 0 0 0 0 1 1
0 0 1 0 0 1 1 1 1
0 1 0 0 0 0 0 1 1
0 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1 1
1 0 1 0 0 1 1 1 1

1 1 0 0 0 0 0 1 1
1 1 1 1 1 1 1 1 1
0 0 0
At this points all states have been accounted
for and the counter is ready to recycle…

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 Serial-in/Serial out Shift Register

Shift registers are available in IC form or can be

constructed from discrete flip-flops as is shown here with a
five-bit serial-in serial-out register.
Each clock pulse will move an input bit to the next flip-
flop. For example, a 1 is shown as it moves across.

FF0 FF1 FF2 FF3 FF4

Serial
data
1 D0 Q0
1 D1 Q1
1 D2 Q2
1 D3 Q3
1 D4 Q4
1 Serial
data
input output

C C C C C

CLK
CLK

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 A Basic Application

An application of shift registers is conversion of serial

data to parallel form.
For example, assume the binary number 1011 is loaded
sequentially, one bit at each clock pulse.
After 4 clock pulses, the data is available at the parallel output.

FF0
FF0
FF0 FF1
FF1 FF2
FF2
FF2 FF3
FF3
FF3
Serial
Serial
Serial 0
1 0
1 10 1
data
data
data D
D
D00 Q00
Q
Q D
D
D11 Q11
Q
Q D22
D
D Q22
Q
Q D33
D
D Q33
Q
Q
input
input
input
C
C C
C CC C
CC

CLK
CLK
CLK
CLK

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 The 74HC164A Shift Register

The 74HC164A is a CMOS 8-bit serial in/parallel out shift

register. VCC can be from +2.0 V to +6.0 V.
(9)
CLR
(8)
CLK
(1)
Serial A
R R R R R R R R
B (2)
inputs C C C C C C C C

S S S S S S S S

(3) (4) (5) (6) (10) (11) (12) (13)

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

One of the two serial data inputs may be used as an active HIGH
enable to gate the other input. If no enable is needed, the other serial
input can be connected to VCC. The 74HC164A has an active LOW
asynchronous clear. Data is entered on the leading-edge of the clock.

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 Parallel in/Serial out Shift Register

Shift registers can be used to convert parallel data to serial

form. A logic diagram for this type of register is shown:
D0 D1 D2 D3

SHIFT/LOAD

G1 G5 G2 G6 G3 G7 G4

Serial
D D D D
Q0 Q1 Q2 Q3 data out
C C C C

FF0 FF1 FF2 FF3

CLK

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 The 74HC165 Shift Register

The 74HC165 is a CMOS 8-bit parallel in/serial out shift

register. The logic symbol is shown:
D0 D1 D2 D3 D4 D5 D6 D7
(11) (12) (13) (14) (3) (4) (5) (6)
(1) (9)
SH/LD (10) SRG 8 Q7
SER
(15)
CLK INH (2) (7)
CLK C Q7

The clock (CLK) and clock inhibit (CLK INH) lines are connected to a
common OR gate, so either of these inputs can be used as an active-
LOW clock enable with the other as the clock input. Data is loaded
asynchronously when SH/LD is LOW and moved through the register
synchronously when SH/LD is HIGH and a rising clock pulse occurs.

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