Review of digital electronics


Digital logic fundamentals

Logic gates

Combinational circuits

System function circuits
 Binary Digits and Logic Levels

In binary, a single number is called a bit (for binary digit).

A bit can have the value of either a 0 or a 1, depending on
if the voltage is HIGH or LOW.

VH(max)
HIGH
VH(min)

Invalid
VL(max)

LOW
VL(min)

2
 Binary Digits and Logic Levels

Transistor-Transistor Logic (TTL)

5V 5V

2.2V 2.6V

0.8V 0.4V

GND GND

Input Output
3
 Binary Digits and Logic Levels

3.3v Logic

3.3V 3.3V

2V 2.4V

0.8V 0.5V

GND GND

Input Output
4
 Digital Waveforms

Digital waveforms change between the LOW and HIGH

levels. A positive going pulse is one that goes from a
normally LOW logic level to a HIGH level and then back
again. Digital waveforms are made up of a series of pulses.

HIGH HIGH

Rising or Falling or Falling or Rising or

leading edge trailing edge leading edge trailing edge

LOW LOW
t0 t1 t0 t1

(a) Positive–going pulse (b) Negative–going pulse

5
 Pulse Definitions

In addition to frequency and period, repetitive pulse waveforms

are described by the amplitude (A), pulse width (tW) and duty
cycle. Duty cycle is the ratio of tW to T.

Volts

Pulse
width
Amplitude (A) (tW)

Time
Period, T

6
 Serial and Parallel Data

Data can be transmitted by either serial transfer or parallel

transfer.
1 0 1 1 0 0 1 0
t0 t1 t2 t3 t4 t5 t6 t7
Computer Modem

1
Computer Printer
0

0
t0 t1

7
 The Inverter

A X

The inverter performs the Boolean NOT operation. When the

input is LOW, the output is HIGH; when the input is HIGH,
the output is LOW.

Input Output
A X
LOW (0) HIGH (1)
HIGH (1) LOW(0)

The NOT operation (complement) is shown with an overbar.

Thus, the Boolean expression for an inverter is X = A.

8
 The Inverter

A X

Example waveforms:
A
X
A group of inverters can be used to form the 1’s complement
of a binary number: Binary number
1 0 0 0 1 1 0 1

0 1 1 1 0 0 1 0
1’s complement

9
 The AND Gate

A A
X & X
B B

The AND gate produces a HIGH output when all inputs are
HIGH; otherwise, the output is LOW. For a 2-input gate,
the truth table is Inputs Output
A B X
0 0 0
0 1 0
1 0 0
1 1 1

The AND operation is usually shown with a dot between the

variables but it may be implied (no dot). Thus, the AND
operation is written as X = A .B or X = AB.

10
 The AND Gate

A A
X & X
B B

Example waveforms:
A
B

X
The AND operation is used in computer programming as a
selective mask. If you want to retain certain bits of a binary
number but reset the other bits to 0, you could set a mask
with 1’s in the position of the retained bits.
If the binary number 10100011 is ANDed with
the mask 00001111, what is the result? 00000011
11
 The OR Gate

A X A ≥1 X
B B

The OR gate produces a HIGH output if any input is HIGH;

if all inputs are LOW, the output is LOW. For a 2-input gate,
the truth table is Inputs Output
A B X
0 0 0
0 1 1
1 0 1
1 1 1

The OR operation is shown with a plus sign (+) between the

variables. Thus, the OR operation is written as X = A + B.

12
 The OR Gate

A X A ≥1 X
B B

Example waveforms:
A
B

X
The OR operation can be used in computer programming to set certain
bits of a binary number to 1.
ASCII letters have a 1 in the bit 5 position for lower case letters
and a 0 in this position for capitals. (Bit positions are numbered
from right to left starting with 0.) What will be the result if you
OR an ASCII letter with the 8-bit mask 00100000?
The resulting letter will be lower case.

13
 The NAND Gate

A X A & X
B B
The NAND gate produces a LOW output when all inputs
are HIGH; otherwise, the output is HIGH. For a 2-input
gate, the truth table is Inputs Output
A B X
0 0 1
0 1 1
1 0 1
1 1 0

The NAND operation is shown with a dot between the

variables and an overbar covering them. Thus, the NAND
operation is written as X = A .B (Alternatively, X = AB.)

14
 The NAND Gate

A X A & X
B B
Example waveforms:
A
B

X
The NAND gate is particularly useful because it is a
“universal” gate – all other basic gates can be constructed
from NAND gates.
How would you connect a 2-input NAND gate
to form a basic inverter?

15
 The NOR Gate

A X A ≥1 X
B B

The NOR gate produces a LOW output if any input is

HIGH; if all inputs are HIGH, the output is LOW. For a
2-input gate, the truth table is
Inputs Output
A B X
0 0 1
0 1 0
1 0 0
1 1 0
The NOR operation is shown with a plus sign (+) between
the variables and an overbar covering them. Thus, the NOR
operation is written as X = A + B.
16
 The NOR Gate

A X A ≥1 X
B B

Example waveforms:
A
B

X
The NOR operation will produce a LOW if any input is HIGH.
+5.0 V

When is the LED is ON for the circuit shown? 330 

A
The LED will be on when any of B X
C
the four inputs are HIGH. D

17
 The XOR Gate

A X A =1 X
B B

The XOR gate produces a HIGH output only when both

inputs are at opposite logic levels. The truth table is
Inputs Output
A B X
0 0 0
0 1 1
1 0 1
1 1 0

The XOR operation is written as X = AB + AB.

Alternatively, it can be written with a circled plus sign
between the variables as X = A + B.

18
 The XOR Gate

A X A =1 X
B B

Example waveforms:
A
B

X
Notice that the XOR gate will produce a HIGH only when exactly one
input is HIGH.
If the A and B waveforms are both inverted for the above
waveforms, how is the output affected?

There is no change in the output.

19
 The XNOR Gate

A X A =1 X
B B

The XNOR gate produces a HIGH output only when both

inputs are at the same logic level. The truth table is
Inputs Output
A B X
0 0 1
0 1 0
1 0 0
1 1 1

The XNOR operation shown as X = AB + AB. Alternatively,

the XNOR operation can be shown with a circled dot
between the variables. Thus, it can be shown as X = A . B.

20
 The XNOR Gate

A X A =1 X
B B

Example waveforms:
A
B

X
Notice that the XNOR gate will produce a HIGH when both inputs are the
same. This makes it useful for comparison functions.
If the A waveform is inverted but B remains the same, how is
the output affected?

The output will be inverted.

21
 Fixed Function Logic

Two major fixed function logic families are TTL and CMOS.
A third technology is BiCMOS, which combines the first
two. Packaging for fixed function logic is shown.

0.335 – 0.334 in.

0.740 – 0.770 in. 14 13 12 11 10 9 8

14 13 12 11 10 9 8

0.250  0.010 in. 0.228 – 0.244 in.

1 2 3 4 5 6 7

1 2 3 4 5 6 7
Pin no.1 Lead no.1
identifiers identifier
14
1 14
1

DIP package SOIC package

22
 Fixed Function Logic

Some common gate configurations are shown.

VCC VCC VCC VCC

14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8

1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND GND GND
'00 ' 02 '04 '08

VCC VCC VCC VCC

14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8

1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND GND GND
'10 '11 '20 '21

VCC VCC VCC VCC

14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8

1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND GND GND
'27 '30 '32 '86

23
 TTL Logic Family

There are several types of TTL logic gate available:

L-type: Low power
H-type: High speed
S-type: Schottky high speed
LS-type: Low power Schottky high speed
ALS-type: Advanced low-power Schottky high speed
F-type: Fast

24
 TTL Logic Family

Type Propagation delay (nS) Switching speed (MHz) Power (mW)

L 33 3 1
H 6 43 22
S 3 100 19
LS 10 40 2
ALS 4 50 1.3
F 3.5 100 5.4

25
 Combinational Logic Circuits

In Sum-of-Products (SOP) form, basic combinational circuits

can be directly implemented with AND-OR combinations if
the necessary complement terms are available.

Product terms
A
AB
B
C CD
D AB + CD + . . . + JK
Sum­of­products
J
JK
K
Product term

26
 Boolean Analysis of Logic Circuits

Combinational logic circuits can be analyzed by writing

the expression for each gate and combining the
expressions according to the rules for Boolean algebra.

Apply Boolean algebra to derive the expression for X.

Write the expression for each gate:

A (A + B )
C (A + B )
B
C X = C (A + B )+ D
D

Applying DeMorgan’s theorem and the distribution law:

X = C (A B) + D = A B C + D

27
 DeMorgan’s Theorem

DeMorgan’s 1st Theorem

The complement of a product of variables is
equal to the sum of the complemented variables.
AB = A + B
Applying DeMorgan’s first theorem to gates:
A A Inputs Output
AB A+B
B B
A B AB A + B
NAND Negative-OR 0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0

28
 DeMorgan’s Theorem

DeMorgan’s 2nd Theorem

The complement of a sum of variables is equal to
the product of the complemented variables.
A+B=A.B
Applying DeMorgan’s second theorem to gates:
A A Inputs Output
A+B AB
B B
A B A + B AB
NOR Negative-AND 0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0

29
 DeMorgan’s Theorem

Apply DeMorgan’s theorem to remove the

overbar covering both terms from the
expression X = C + D.

To apply DeMorgan’s theorem to the expression,

you can break the overbar covering both terms and
change the sign between the terms. This results in
=
X = C . D. Deleting the double bar gives X = C . D.

30
 SOP and POS forms

Boolean expressions can be written in the sum-of-products

form (SOP) or in the product-of-sums form (POS). These
forms can simplify the implementation of combinational
logic, particularly with PLDs. In both forms, an overbar
cannot extend over more than one variable.
An expression is in SOP form when two or more product terms are
summed as in the following examples:
ABC+AB ABC+CD CD+E
An expression is in POS form when two or more sum terms are
multiplied as in the following examples:
(A + B)(A + C) (A + B + C)(B + D) (A + B)C

31
 Half-Adder

Basic rules of binary addition are performed by a

Inputs Outputs
half adder, which has two binary inputs (A and
A B Cout 
B) and two binary outputs (Carry out and Sum). 0 0
0 0
0 1 0 1
The inputs and outputs can be summarized on a 1 0 0 1
truth table. 1 1 1 0

The logic symbol and equivalent circuit are:

 
A 
A
Cout
B Cout B

32
 Full-Adder

Inputs Outputs

By contrast, a full adder has three binary A B Cin Cout 

0 0 0 0 0
inputs (A, B, and Carry in) and two binary 0 0 1 0 1
outputs (Carry out and Sum). The truth table 0 1 0 0 1
summarizes the operation. 0 1 1 1 0
1 0 0 0 1
A full-adder can be constructed from two 1 0 1 1 0
half adders as shown: 1 1 0 1 0
1 1 1 1 1
 
A A  A  Sum

B B Cout B Cout A 
B
C
Cin Cin out

Cout Symbol

33
 Parallel Adders

Full adders are combined into parallel adders that can add binary
numbers with multiple bits. A 4-bit adder is shown.
A4 B4 A3 B3 A2 B2 A1 B1

C0

A B Cin A B Cin A B Cin A B Cin

Cout  Cout  Cout  Cout 

C4
C3 C2 C1
   

The output carry (C4) is not ready until it propagates through all of the
full adders. This is called ripple carry, delaying the addition process.

34
 Parallel Adders

The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder
includes a carry in (labeled (C0) and a Carry out (labeled C4).

1 1
Binary 2 2 4-bit
number A 3 3 sum
4 4
1
Binary 2
number B 3
4
Input Output
C0 C4
carry carry

The 74LS283 is an example. It features look-ahead carry, which adds

logic to minimize the output carry delay. For the 74LS283, the
maximum delay to the output carry is 17 ns.

35
 Comparators

The function of a comparator is to compare the magnitudes of two

binary numbers to determine the relationship between them. In the
simplest form, a comparator can test for equality using XNOR gates.
How could you test two 4-bit numbers for equality?

AND the outputs of four XNOR gates.

A1
B1
A2
B2 Output
A3
B3
A4
B4

36
 Comparators

IC comparators provide outputs to indicate which of the numbers is

larger or if they are equal. The bits are numbered starting at 0, rather
than 1 as in the case of adders. Cascading inputs are provided to
expand the comparator to larger numbers.

COMP
A0 0
A1 A
A2
A3 3
Cascading A>B A>B
A=B A=B Outputs
inputs
A<B A<B
B0 0
B1 A
The IC shown is the
B2
B3 3 4-bit 74LS85.

37
 Decoders

A decoder is a logic circuit that detects the presence of a specific

combination of bits at its input. Two simple decoders that detect the
presence of the binary code 0011 are shown. The first has an active
HIGH output; the second has an active LOW output.

A0 A0
A1 X A1 X

A2 A2

A3 A3

Active HIGH decoder for 0011 Active LOW decoder for 0011

38
 Decoders

X/Y
0
A specific integrated circuit 1
decoder is the 74HC154 (shown as 2
3
a 4-to-16 decoder). It includes two 4

active LOW chip select lines which A0 1

5
6
must be at the active level to enable A1 2 7
A2
the outputs. These lines can be used A3
4
8
8
9
to expand the decoder to larger 10
11
inputs. 12
13
14
CS1 & 15
CS2 EN
74HC154

39
 BCD Decoder/Driver

Here the 7447A is an connected to an LED seven segment

display. Notice the current limiting resistors, required to
prevent overdriving the LED display.
+5.0 V
1.0 k
+5.0 V
74LS47 16
R's = MAN72
BCD/7-seg
3 VCC 330  3, 9, 14
LT a 13 1 a
4
BI/RBO b 12 13 b
5 RBI 11 10
c c
6 A 10 8
d d
2 B e 9 7 e
BCD
input 1 C f 15 2 f
g 14 11 g
7
D
GND
8

40
 BCD Decoder/Driver

The 74LS47 features leading zero suppression, which

blanks unnecessary leading zeros but keeps significant
zeros as illustrated here. The BI/RBO output is connected
to the RBI input of the next decoder.
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0

RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1

74LS47 74LS47 74LS47 74LS47

g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO

Blanked Blanked Depending on the display type, current

limiting resistors may be required.

41
 Encoders

An encoder accepts an active logic level on one of its

inputs and converts it to a coded output, such as BCD or
binary.
1
The decimal to BCD is an encoder A0
with an input for each of the ten 2

decimal digits and four outputs that 3

A1
represent the BCD code for the active
4
digit. The basic logic diagram is 5 A2
6
shown. There is no zero input 7
because the outputs are all LOW 8
A3
when the input is zero. 9

42
 Encoders

Show how the decimal-to-BCD encoder converts the

decimal number 3 into a BCD 0011.
The top two OR gates have ones as indicated with
the red lines. Thus the output is 0111.

1 0 1
A0
2 0
1
3 1
A1
4 0
5 0 0
6
0
0 A2
7
8 0 0
A3
0
9

43
 Encoders

The 74HC147 is an example of an IC encoder. It is has ten

active-LOW inputs and converts the active input to an
active-LOW BCD output. V CC

(16)
This device is offers additional (11)
HPRI/BCD
1
flexibility in that it is a priority (12)
2
(13)
encoder. This means that if more (1)
3
1 (9)
4 (7)
than one input is active, the one Decimal (2)
5
2
(6)
BCD
input (3) 4 output
with the highest order decimal (4)
6
8
(14)
7
digit will be active. (5) 8
(10) 9
(8)
74HC147
The next slide shows an application … GND

44
 Encoders

VCC

R7 R8 R9

Keyboard
7 8 9
encoder HPRI/BCD
1
R4 R5 R6 2
3
1
4 2
5 4 BCD complement of
6
4 5 6 7
8 key press
8
9

R1 R2 R3 74HC147

1 2 3

R0
The zero line is not needed by the
0 encoder, but may be used by other
circuits to detect a key press.

45
 Multiplexers

A multiplexer (MUX) selects one data line from two or

more input lines and routes data from the selected line to
the output. The particular data line that is selected is
determined by the select inputs.
MUX
Two select lines are shown 0
S0 0
Data 1
here to choose any of the select S1
1
four data inputs.
D0 0 Data
D 1 output
Data D1
2
inputs D2
Which data line is selected 3 3
if S1S0 = 10?D2

46
 Demultiplexers

A demultiplexer (DEMUX) performs the opposite function

from a MUX. It switches data from one input line to two or
more data lines depending on the select inputs.
The 74LS138 was introduced
DEMUX
previously as a decoder but can also A0
Y
0
Data
serve as a DEMUX. When select A1
Y
1

Y
connected as a DEMUX, data is lines A2 2

Data
Y
applied to one of the enable inputs, 3

Y
outputs
and routed to the selected output Enable G1 4

Y
G2A
5

line depending on the select inputs

G2B
Y
6

variables. Note that the outputs are Y

7

active-LOW as illustrated in the 74LS138

following example…

47