TABLE OF CONTENTS

Total pages = 28

Sr. No. Title

1 Write a VHDL program to implement 3:8 decoder

Write a VHDL program to implement 8:1 multiplexer using

2
behavioral modeling.

Write a VHDL program to implement a 1:8 Demultiplexer using

3
behavioral modelling

4 Write a VHDL program to implement 4-bit addition

5 Write a program to implement 4- bit Comparator

6 Write a program to implement mod 10 - Upcounter

7 Write a VHDL Program to generate the 1010 sequence detector

Write a VHDL code to implement serial to Parallel of 4 bit binary

8
number

Write a VHDL code to implement Parallel to Serial of 4 bit binary

9
number

Write a program to design a 2 bit ALU containing 4 arithmetic & 4

10
logic operations
 EXPERIMENT – 1
Objective: Write a VHDL program to implement 3:8 decoder
Requirement: Computer Software Requirement: XILINX VIVADO 2014.1 Software
Theory:
Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2n output lines. One of
these outputs will be active High based on the combination of inputs present, when the decoder is
enabled. That means decoder detects a particular code.

Circuit Diagram:

Fig. Implementation of 3:8 Decoder

Truth Table:

Boolean Expression:

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity decoder_38 is
Port ( a : in STD_LOGIC_VECTOR(2 DOWNTO 0);
a1 : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end decoder_38;

architecture Behavioral of decoder_38 is

begin
process(a)
begin
case a is
when "000"=>a1<="10000000";
when "001"=>a1<="01000000";
when "010"=>a1<="00100000";
when "011"=>a1<="00010000";
when "100"=>a1<="00001000";
when "101"=>a1<="00000100";
when "110"=>a1<="00000010";
when "111"=>a1<="00000001";
 when others=>null;
end case;
end process;
end Behavioral;

Output:

Results: VHDL codes of 3:8 decoder is simulated successfully.

 EXPERIMENT –2
Objective: Write a VHDL program to implement 8:1 multiplexer using behavioral modelling
Requirement: Computer Software Requirement: XILINX Vivado 2014.1 Software.
Theory:
In electronics, a multiplexer, also known as a data selector, is a device that selects between several
analog or digital input signals and forwards it to a single output line. A multiplexer of inputs has
select lines, which are used to select which input line to send to the output.

Circuit:

Fig. Implementation of 8:1 Multiplexer

Truth Table:

Boolean Expression:

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_8to1 is
Port ( s : in STD_LOGIC_VECTOR (2 downto 0);
x : in STD_LOGIC_VECTOR (7 downto 0);
y : out STD_LOGIC);
end mux_8to1;

architecture Behavioral of mux_8to1 is

begin
process (x,s)
begin
case s is
when "000"=>y<=x(0);
when "001"=>y<=x(1);
when "010"=>y<=x(2);
when "011"=>y<=x(3);
when "100"=>y<=x(4);
when "101"=>y<=x(5);
when "110"=>y<=x(6);
when "111"=>y<=x(7);
when others=> null;
end case;
end process;
end Behavioral;

Output:

Results: VHDL codes of 8:1 Multiplexer is simulated & synthesized

 EXPERIMENT–3
Objective: Write a VHDL program to implement 1:8 Demultiplexer using behavioral modelling
Requirement: Computer Software Requirement: XILINX 8.2 Software
Theory:
A demultiplexer (or demux) is a device that takes a single input line and routes it to one of several
digital output lines. A demultiplexer of 2n outputs has n select lines, which are used to select which
output line to send the input. A demultiplexer is also called a data distributor.
Circuit:

Fig. Implementation of 1:8 Demultiplexer

Truth Table:

VHDL Code:

Behavioral Modelling

library ieee;
use ieee.std_logic_1164.all;

entity demux is
port(x:IN STD_LOGIC;
s:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end demux;

architecture Behavioral of demux is

begin
process (x,s)
begin
case s is

WHEN "000" => y<="0000000"&x;

WHEN "001" => y<="000000"&x&"0";
WHEN "010" => y<="00000"&x&"00";
WHEN "011" => y<="0000"&x&"000";
WHEN "100" => y<="000"&x&"0000";
WHEN "101" => y<="00"&x&"00000";
WHEN "110" => y<="0"&x&"000000";
WHEN "111" => y<=x&"0000000";
WHEN OTHERS=>NULL;
end case;
end process;

end Behavioral;
Output:

Results: VHDL codes of 1:8 Demultiplexer is simulated.

 EXPERIMENT-4
Objective: Write a VHDL program to implement 4 bit addition.

Resources Required:
Hardware Requirement: Computer
Software Requirement: GHDL, GTKwave, Notepad++
Theory:
A full adder is a combinational circuit that forms the arithmetic sum of three bits. It consists of three inputs and
two outputs. Two of the inputs variables represent the two significant bits to be added. The third input
represents the carry from the previous lower significant position. The two outputs are designated by the symbols
S for sum and C for carry. The binary variable S gives the value of the least significant bit of the sum. The
binary variable C gives the output carry. The output variables are determined from the arithmetic sum of the
input bits. A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adder connected in cascade, the output carry from each full adder connected to the input
carry of the next full adder in the chain. Figure below shows the interconnection of four full adder (FA) circuits
to provide a 4-bit binary ripple carry adder. The augend bits of A and addend bits of B are designated by
subscript numbers from right to left, with subscript 0denoting the least significant bit. The carries are connected
in the chain through the full adders. The input carry to the adder is C0 and it ripples through the full adder to the
output carry C4.The S output generate the required sum bits.

Fig. Bit Adder

The 4 bit adder is a typical example of a standard component. It can be used in many applications involving
arithmetic operations. Observe that the design of this circuit by the classical method would require a truth table
with 29 = 512 entries, since there are nine inputs to the circuit. By using an iterative method of cascading a
standard function, it is possible to obtain a simple and straightforward implementation.

Application:
1) The ALU (arithmetic logic circuitry) of a computer uses half adder to compute the binary addition operation
on two bits.
2) Half adder is used to make full adder as a full adder requires 3 inputs, the third input being an input carry i.e.
we will be able to cascade the carry bit from one adder to the other.
3) Ripple carry adder is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each
full adder inputs a C(in), which is the C(out) of the previous adder. This kind of adder is called RIPPLE
CARRY ADDER, since each carry bit "ripples" to the next full adder. Note that the first full adder (and only the
first) may be replaced by a half adder.

VHDL Code:

Behavioral Modelling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_adder_vhdl_code is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end full_adder_vhdl_code;

architecture gate_level of full_adder_vhdl_code is

begin

S <= A XOR B XOR Cin ;

Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;

end gate_level;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Ripple_Adder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end Ripple_Adder;

architecture Behavioral of Ripple_Adder is

component full_adder_vhdl_code
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;

signal c1,c2,c3: STD_LOGIC;

begin
FA1: full_adder_vhdl_code port map( A(0), B(0), Cin, S(0), c1);
FA2: full_adder_vhdl_code port map( A(1), B(1), c1, S(1), c2);
FA3: full_adder_vhdl_code port map( A(2), B(2), c2, S(2), c3);
FA4: full_adder_vhdl_code port map( A(3), B(3), c3, S(3), Cout);

end Behavioral;

Output:

Results: VHDL codes of implement 4 bit addition/subtraction is simulated & verified.

 EXPERIMENT–5
Objective: Write a program to implement 4- bit Comparator
Resources Required:
Hardware Requirement: Computer
Software Requirement: GHDL, GTKwave, Notepad++
Theory:
A digital comparator is a hardware electronic device that takes two numbers as input in binary form and
determines whether one number is greater than, less than or equal to the other number.

Fig. Logical Diagram of 4 bit Comparator

Truth Table:

It can be used to compare two four-bit words. The two 4-bit numbers are A = A3 A2 A1 A0 and B3 B2 B1 B0
where A3 and B3 are the most significant bits.
It compares each of these bits in one number with bits in that of other number and produces one of the
following outputs as A = B, A < B and A>B. The output logic statements of this converter are

Boolean Expression
• If A3 = 1 and B3 = 0, then A is greater than B (A>B). Or
• If A3 and B3 are equal, and if A2 = 1 and B2 = 0, then A > B. Or
• If A3 and B3 are equal & A2 and B2 are equal, and if A1 = 1, and B1 = 0, then A>B. Or
• If A3 and B3 are equal, A2 and B2 are equal and A1 and B1 are equal, and if A0 = 1 and B0 = 0, then A
> B.
• the output A > B logic expression can be written as

• The equal output is produced when all the individual bits of one number are exactly coincides with
corresponding bits of another number. Then the logical expression for A=B output can be written as
• E = (A3 Ex-NOR B3) (A2 Ex-NOR B2) (A1 Ex-NOR B1) (A0 Ex-NOR B0)

Application: Comparators are used in central processing unit s (CPUs) and microcontrollers (MCUs).
Examples of digital comparator include the CMOS 4063 and 4585 and the TTL 7485 and 74682-'89.

VHDL Code:
Behavioral Modelling

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity COMPARATOR_SOURCE is
port ( A,B : in std_logic_vector(3 downto 0);
greater, equal, smaller : out std_logic);
end COMPARATOR_SOURCE ;
architecture bhv of COMPARATOR_SOURCE is
begin
greater <= '1' when (A > B)
else '0';
equal <= '1' when (A = B)
else '0';
smaller <= '1' when (A < B)
else '0';
end bhv;

Output:

Result: VHDL codes of 4- bit Comparator is simulated & verified.

 EXPERIMENT-6
Objective: To write a VHDL program to implement Up Counter

Resource Required:
Hardware Requirement: Computer
Software Requirement: GHDL, GTKwave, Notepad++
Theory:
Counters are sequential logic devices that follow a predetermined sequence of counting states which are
triggered by an external clock (CLK) signal. The number of states or counting sequences through which a
particular counter advances before returning once again back to its original first state is called
the modulus (MOD). In other words, the modulus (or just modulo) is the number of states the counter counts
and is the dividing number of the counter. The decade counter has four outputs producing a 4-bit binary
number, it receives an input clock pulse, one by one, and counts up from 0 to 9 repeatedly.

Application: It suitable for human interfacing where a digital display is required.

VHDL code:

Behavioral Modelling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity upcounter is
Port ( clk : in STD_LOGIC;
C : inout integer:=0);
end upcounter;

architecture Behavioral of upcounter is

begin
process (clk)
begin
if(clk'event and clk='1')then
if (C<9)
then C<=C+1;
else if(c=9)
then C<=0;
end if;
end if;
end if;
end process;
end Behavioral;
Output:

Result: VHDL codes of Mod-10 up counter is simulated & verified.

 EXPERIMENT-7
Objective: Write a VHDL Program to generate the 1010 sequence detector. The overlapping patterns are
allowed.

Resources Required:
Hardware Requirement: Computer
Software Requirement: GHDL, GTKwave, Notepad++
Theory:
The objective of this experiment is to introduce the use of sequential logic. The sequence is a sequential circuit.
In sequential logic the output depends on the current input values and also the previous inputs. When describing
the behaviour of a sequential logic circuit we talk about the state of the circuit. The state of a sequential circuit
is a result of all previous inputs and determines the circuit’s output and future behaviour. This is why sequential
circuits are often referred to as state machines. Most sequential circuits (including our sequence detector) use a
clock signal to control when the circuit changes states. The inputs of the circuit along with the circuit’s current
state provide the information to determine the circuit’s next state. The clock signal then controls the passing of
this information to the state memory. The output depends only on the circuit’s state, this is known as a Moore
Machine. Figure 7.1 shows the schematic of a Moore Machine.

Fig. Schematic of a clocked synchronous state machine (Moore Machine).

A sequential circuit’s behaviour can be shown in a state diagram. The state diagram for our sequence detector is
shown in figure 7.2. Each circle represents a state and the arrows show the transitions to the next state. Inside
each circle are the state name and the value of the output. Along each arrow is the input value that corresponds
to that transition.

State Diagram:
1/0
0/0 1/0

0/0 1/0
S0 S1 S2 S3
1/0

0/1
0/0
Fig. Sequence Detector state diagram.
A sequence detector accepts as input a string of bits: either 0 or 1. Its output goes to 1 when a target sequence
has been detected. There are two basic types: overlap and non-overlap. In a sequence detector that allows
overlap, the final bits of one sequence can be the start of another sequence.
Example:
11011 detector with overlap X 11011011011
Z 00001001001
11011 detector with no overlap Z 00001000001

Applications:
In a computer network like Ethernet, digital data is sent one bit at a time, at a very high rate. Such a movement
of data is commonly called a bit stream. One characteristic is unfortunate, particularly that any one bit in a bit
stream looks identical to many other bits. Clearly it is important that a receiver can identify important features
in a bit stream. As an example, it is important to identify the beginning and ending of a message. This is the
job of special bit sequences called flags. A flag is simply a bit sequence that serves as a marker in the bit
stream. To detect a flag in a bit stream a sequence detector is used.

VHDL code:

Behavioral Modelling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity seq_det is
port( clk : in std_logic;
reset : in std_logic;
input : in std_logic; --input bit sequence
output : out std_logic );
end seq_det;

architecture Behavioral of seq_det is

type state_type is (s0,s1,s2,s3);
signal state : state_type := s0;
begin
process(clk, reset)
begin
if( reset = '1' ) then
output <= '0';
state <= s0;
elsif ( clk' event and clk='1' )then
case state is
when s0 =>
output <= '0';
if ( input = '0' ) then
state <= s0;
else
state <= s1;
end if;
when s1 =>
 if ( input = '0' ) then
state <= s2; output<='0';
else
state <= s1; output<='0';
end if;
when s2 =>
if ( input = '0' ) then
state <= s0; output<='0';
else
state <= s3; output<='0';
end if;
when s3 =>
if ( input = '0' ) then
state <= s2;
output<='1';
else
state <= s1;
output <= '0';
end if;
when others => NULL;
end case;
end if;
end process;
end Behavioral;

Output:

Results: Thus, the VHDL code for the 1010 sequence detector circuit was simulated and verified.
 EXPERIMENT - 8
Objective: Write a VHDL code to implement serial to parallel of 4-bit binary number.

Resources Required:
Hardware Requirement: Computer
Software Requirement: GHDL, GTKwave, Notepad++
Theory:

Figure 8.1 4-bit Serial-in to Parallel-out Shift Register

The operation is as follows. Let’s assume that all the flip-flops ( FFA to FFD ) have just been RESET ( CLEAR
input ) and that all the outputs QA to QD are at logic level “0” i.e., no parallel data output.
If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the output of FFA and
therefore the resulting QA will be set HIGH to logic “1” with all the other outputs still remaining LOW at logic
“0”. Assume now that the DATA input pin of FFA has returned LOW again to logic “0” giving us one data
pulse or 0-1-0.
The second clock pulse will change the output of FFA to logic “0” and the output of FFB and QB HIGH to logic
“1” as its input D has the logic “1” level on it from QA. The logic “1” has now moved or been “shifted” one
place along the register to the right as it is now at QA.
When the third clock pulse arrives this logic “1” value moves to the output of FFC ( QC ) and so on until the
arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic level “0” because the input
to FFA has remained constant at logic level “0”.
The effect of each clock pulse is to shift the data contents of each stage one place to the right, and this is shown
in the following table until the complete data value of 0-0-0-1is stored in the register. This data value can now
be read directly from the outputs of QA to QD.
Then the data has been converted from a serial data input signal to a parallel data output. The truth table and
following waveforms show the propagation of the logic “1” through the register from left to right as follows.
Basic Data Movement through a Shift Register:
Clock Pulse No QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 0 0 0 0

Note that after the fourth clock pulse has ended the 4-bits of data ( 0-0-0-1 ) are stored in the register and will
remain there provided clocking of the register has stopped. In practice the input data to the register may consist
of various combinations of logic “1” and “0”. Commonly available SIPO IC’s include the standard 8-bit
74LS164.
VHDL Code:
Behavioral Modelling
library ieee;
use ieee.std_logic_1164.all;
entity sipo is
port( res: in std_logic;
sin: in std_logic;
clk: in std_logic;
pout: out std_logic_vector(3 downto 0));
end sipo;
architecture beh of sipo is
signal temp: std_logic_vector( 3 downto 0);
begin
process( clk, res) begin
if(res='1') then
temp<="0000";
elsif (clk'event and clk ='1') then
temp(3)<=sin;
temp(2)<=temp(3);
temp(1)<=temp(2);
temp(0)<=temp(1);
end if;
end process;
pout<=temp;
end beh;

Output:

Results: VHDL code to implement serial to parallel of 4 bit binary number is simulated and verified.
 EXPERIMENT-9
Objective: Write a VHDL program to perform parallel to serial transfer of 4 bit binary number

Resources Required:
Hardware Requirement: Computer
Software Requirement: GHDL, GTKwave, Notepad++
Theory:
Parallel-in/ serial-out shift registers do everything that the previous serial-in/ serial-out shift registers do plus
input data to all stages simultaneously. The parallel-in/ serial-out shift register stores data, shifts it on a clock
by clock basis, and delays it by the number of stages times the clock period. In addition, parallel-in/ serial-out
really means that we can load data in parallel into all stages before any shifting ever begins. This is a way to
convert data from a parallel format to a serial format. By parallel format we mean that the data bits are
present simultaneously on individual wires, one for each data bit as shown below. By serial format we mean
that the data bits are presented sequentially in time on a single wire or circuit as in the case of the “data out”
on the block diagram below.

.
Application:
1. Bit serial operations can be performed quickly through device iteration
2. Iteration (a purely combinational approach) is expensive (in terms of # of transistors, chip area, power,
etc).
3. A sequential approach allows the reuse of combinational functional units throughout the multi-cycle
operation

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity piso is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
load : in STD_LOGIC;
din : in STD_LOGIC_VECTOR(3 downto 0);
dout : out STD_LOGIC);
end piso;
architecture piso_arc of piso is
begin
 piso1 : process (clk,reset,load,din) is
variable temp : std_logic_vector (din'range);
begin
if (reset='1') then
temp := (others=>'0');
elsif (load='1') then
if (rising_edge (clk)) then
temp := din ;
end if;
elsif (rising_edge (clk)) then
dout <= temp(3);
temp(3 downto 1) := temp(2 downto 0);
end if;
end process piso1;
end piso_arc;

Output:

Results: VHDL program to perform parallel to serial transfer of 4 bit binary number is simulated and verified.
 EXPERIMENT–10
Objective: Write a program to design a 2-bit ALU containing 4 arithmetic & 4 logic operations.

Resources Required:
Hardware Requirement: Computer
Software Requirement: GHDL, GTKwave, Notepad++
Theory:
An ALU stands for arithmetic logic unit ALU is a digital circuit used to perform arithmetic and logic
operations. It represents the fundamental building block of the central processing unit of CPU. Modern CPUs
contains very powerful and complex ALUs. In some processors ALU is divided into two units an arithmetic unit
and a logic unit.

VHDL Code:

Behavioral Modelling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU is
port(
inputA,inputB:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
output:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
sel:IN STD_LOGIC_VECTOR(2 DOWNTO 0)
);
end ALU;

architecture alu of ALU is

begin
process(inputA,inputB,sel)
begin
case sel is
when "000" => output<=inputA+inputB;
when "001" => output<=inputA-inputB;
when "010" => output<=inputA-1;
when "011" => output<=inputA+1;
when "100" => output<=inputA and inputB;
when "101" => output<=inputA or inputB;
when "110" => output<=not inputA;
when "111" => output<=inputA xor inputB;
 when others => output<="0000";
end case;
end process;
end alu;

Output:

Results: Design of 2-bit ALU containing 4 arithmetic & 4 logic operations is simulated and verified.