ST62T18C/E18C

8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD

TIMER, UART, OSG, SAFE RESET AND 20-PIN PACKAGE

■ 3.0 to 6.0V Supply Operating Range

■ 8 MHz Maximum Clock Frequency
■ -40 to +125°C Operating Temperature Range
■ Run, Wait and Stop Modes
■ 5 Interrupt Vectors
■ Look-up Table capability in Program Memory
■ Data Storage in Program Memory:
User selectable size
■ Data RAM: 192 bytes
■ User Programmable Options PDIP20
■ 12 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
■ 5 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
■ 8-bit Timer/Counter with 7-bit programmable PSO20
prescaler
■ 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
■ Digital Watchdog
■ 8-bit A/D Converter with 7 analog inputs
■ 8-bit Asynchronous Peripheral Interface
(UART)
■ On-chip Clock oscillator can be driven by Quartz
Crystal or Ceramic resonator CDIP20W
■ Oscillator Safe Guard
■ Low Voltage Detector for safe Reset
(See end of Datasheet for Ordering Information)
■ One external Non-Maskable Interrupt
■ ST623x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
OTP EPROM
DEVICE I/O Pins
(Bytes) (Bytes)
ST62T18C 7948 - 12
ST62E18C 7948 12

Rev. 2.5

November 1999 1/82

1
 Table of Contents Document
Page
ST62T18C/E18C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.6 Data RAM Bank Register (DRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4.1 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 16
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.2 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.3 Oscillator Safe Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.4 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.5 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.6 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4 IINTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.1 Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4.4 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.3 ARTimer alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.4 UART alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.5 I/O Port Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.6 I/O Port Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.7 I/O Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.1 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3.1 AR Timer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3.3 AR Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.5 U. A. R. T. (UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER) . . . . . . . . . . . 53
4.5.1 Ports Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.5.2 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.5.3 Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.5.4 Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.5.5 Interrupt Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.5.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.8 ARTIMER ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

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Page
ST62P18C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.2.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

ST6218C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.3 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.4 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.4.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.4.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

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 ST62T18C/E18C

1 GENERAL DESCRIPTION

1.1 INTRODUCTION
The ST62T18C and ST62E18C devices are low common core is surrounded by a number of on-
cost members of the ST62xx 8-bit HCMOS family chip peripherals.
of microcontrollers, which are targeted at low to
medium complexity applications. All ST62xx de- The ST62E18C is the erasable EPROM version of
vices are based on a building block approach: a the ST62T18C device, which may be used to em-
ulate the ST62T18C device, as well as the respec-
tive ST6218C ROM devices.
Figure 1. Block Diagram

PA1 / 20 mA Sink
8-BIT PORT A PA2/ARTIMout / 20 mA Sink
PA3/ARTIMin/ 20 mA Sink
A/D CONVERTER PA4..PA 5/20 mA Sink
TEST/VPP TEST

PORT B PB4..PB6/Ain
NMI INTERRUPT
DATA ROM
USER PD4/Ain/RXD1
SELECTABLE PD5/Ain/TXD1
PORT D
PROGRAM PD6,PD7/Ain
Memory DATA RAM
7948 bytes 192 Bytes
UART

AUTORELOAD
TIMER

PC

STACK LEVEL 1 TIMER TIMER

STACK LEVEL 2
STACK LEVEL 3 8 BIT CORE
STACK LEVEL 4
STACK LEVEL 5
DIGITAL
STACK LEVEL 6 WATCHD OG

POWER OSCILLATOR RESET

SUPPLY

VDD VSS OSCin OSCout RESET

VR01823F
(VPP on EPROM/OTP versions only)

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ST62T18C/E18C

INTRODUCTION (Cont’d)
OTP and EPROM devices are functionally identi- Figure 2. ST62T18C/E18C Pin Configuration
cal. The ROM based versions offer the same func-
tionality selecting as ROM options the options de- These compact low-cost devices feature a Timer
fined in the programmable option byte of the OTP/
EPROM versions.OTP devices offer all the advan- VDD 1 20 VSS
tages of user programmability at low cost, which TIMER 2 19 PA1*
make them the ideal choice in a wide range of ap- OSCin 3 18 PA2/ARTIMout*
plications where frequent code changes, multiple
OSCout 4 17 PA3/ARTIMin*
code versions or last minute programmability are
required. NMI 5 16 PA4*
TEST/VPP(1) 6 15 PA5*
RESET 7 14 PD4/Ain/RXD1
Ain/PB6 8 13 PD5/Ain/TXD1
Ain/PB5 9 12 PD6/Ain
Ain/PB4 10 11 PD7/Ain

(1) V on EPROM/OTP only

PP
(*) 20 mA Sink

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 ST62T18C/E18C

1.2 PIN DESCRIPTIONS

VDD and VSS. Power is supplied to the MCU via PA3/ARTIMout and PA4/ARTIMin can be used re-
these two pins. VDD is the power connection and spectively as output and input pins for the embed-
VSS is the ground connection. ded 8-bit Auto-Reload Timer.
OSCin and OSCout. These pins are internally In addition, PA1-PA5 can sink 20mA for direct LED
connected to the on-chip oscillator circuit. A quartz or TRIAC drive.
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins. PB4...PB6. These 3 lines are organised as one I/O
The OSCin pin is the input pin, the OSCout pin is port (B). Each line may be configured under soft-
the output pin. ware control as inputs with or without internal pull-
up resistors, input with interrupt generation and
RESET. The active-low RESET pin is used to re- pull-up resistor, open-drain or push-pull outputs,
start the microcontroller. analog inputs for the A/D converter.
TEST/VPP. The TEST must be held at VSS for nor- PD4...PD7. These 4 lines are organised as one I/O
mal operation. If TEST pin is connected to a port (portD). Each line may be configured under
+12.5V level during the reset phase, the EPROM/ software control as input with or without internal
OTP programming Mode is entered. pull-up resistor, input with interrupt generation and
NMI. The NMI pin provides the capability for asyn- pull-up resistor, analog input open-drain or push-
chronous interruption, by applying an external non pull output. In addition, the pins PD5/TXD1 and
maskable interrupt to the MCU. The NMI input is PD4/RXD1 can be used as UART output (PD5/
falling edge sensitive with Schmitt trigger charac- TXD1) or UART input (PD4/RXD1).
teristics. The user can select as option the availa-
TIMER. This is the TIMER 1 I/O pin. In input mode,
bility of an on-chip pull-up at this pin.
it is connected to the prescaler and acts as ex-
PA1-PA5. These 5 lines are organised as one I/O ternal timer clock or as control gate for the internal
port (A). Each line may be configured under soft- timer clock. In output mode, the TIMER pin outputs
ware control as inputs with or without internal pull- the data bit when a time-out occurs.The user can
up resistors, input with interrupt generation and select as option the availability of an on-chip pull-
pull-up resistor, open-drain or push-pull outputs. up at this pin.

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ST62T18C/E18C

1.3 MEMORY MAP

1.3.1 Introduction (STATIC) 2K page is available all the time for inter-
rupt vectors and common subroutines, independ-
The MCU operates in three separate memory ently of the PRPR register content. This “STATIC”
spaces: Program space, Data space, and Stack page is directly addressed in the 0800h-0FFFh by
space. Operation in these three memory spaces is the MSB of the Program Counter register PC 11.
described in the following paragraphs. Note this page can also be addressed in the 000-
7FFh range. It is two different ways of addressing
Briefly, Program space contains user program the same physical memory.
code in Program memory and user vectors; Data
space contains user data in RAM and in Program Jump from a dynamic page to another dynamic
memory, and Stack space accommodates six lev- page is achieved by jumping back to the static
els of stack for subroutine and interrupt service page, changing contents of PRPR and then jump-
routine nesting. ing to the new dynamic page.
1.3.2 Program Space
Figure 3. 8Kbytes Program Space Addressing
Program Space comprises the instructions to be
executed, the data required for immediate ad- ROM SPACE
dressing mode instructions, the reserved factory PC
test area and the user vectors. Program Space is SPACE 0000h 1FFFh
addressed via the 12-bit Program Counter register
(PC register). 000h Page 1
Page 0 Static Page 2 Page 3
Program Space is organised in 4K pages. 4 of 7FFh Page
them are addressed in the 000h-7FFh locations of 800h Page 1
the Program Space by the Program Counter and Static
by writing the appropriate code in the Program FFFh Page
ROM Page Register (PRPR register). A common
Figure 4. Memory Addressing Diagram

PROGRAM SPACE DATA SPACE

0000h 000h

RAM / EEPROM
BANKING AREA

0-63 03Fh
040h
DATA READ-ONLY
PROGRAM MEMORY WINDOW
MEMORY 07Fh
080h X REGISTER
081h Y REGISTER
082h V REGISTER
083h W REGISTER
084h
RAM

0C0h DATA READ-ONLY

MEMORY
0FF0h WINDOW SELECT
DATA RAM
INTERRUPT & BANK SELECT
RESET VECTORS
0FFFh 0FFh ACCUMULATOR
VR01568

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 ST62T18C/E18C

MEMORY MAP (Cont’d)

Table 1. ST62E18C/T18C Program Memory Map Program ROM Page Register (PRPR)
ROM Page Device Address Description Address: CAh — Write Only
0000h-007Fh Reserved 7 0
Page 0
0080h-07FFh User ROM
- - - - - - PRPR1 PRPR0
0800h-0F9Fh User ROM
0FA0h-0FEFh Reserved
Page 1 0FF0h-0FF7h Interrupt Vectors
“STATIC” 0FF8h-0FFBh Reserved Bits 2-7= Not used.
0FFCh-0FFDh NMI Vector
0FFEh-0FFFh Reset Vector Bit 5-0 = PRPR1-PRPR0: Program ROM Select.
These two bits select the corresponding page to
Page 2
0000h-000Fh Reserved be addressed in the lower part of the 4K program
0010h-07FFh User ROM address space as specified in Table 2.
0000h-000Fh Reserved This register is undefined on Reset. Neither read
Page 3
0010h-07FFh User ROM nor single bit instructions may be used to address
this register.
Note: OTP/EPROM devices can be programmed
Table 2. 6Kbytes Program ROM Page Register
with the development tools available from STMicro- Coding
electronics (ST62E2XC-EPB or ST622XC-KIT).
PRPR1 PRPR0 PC bit 11 Memory Page
X X 1 Static Page (Page 1)
1.3.2.1 Program ROM Page Register (PRPR)
0 0 0 Page 0
The PRPR register can be addressed like a RAM 0 1 0 Page 1 (Static Page)
location in the Data Space at the address CAh;
nevertheless it is a write only register that cannot 1 0 0 Page 2
be accessed with single-bit operations. This regis- 1 1 0 Page 3
ter is used to select the 2-Kbyte ROM bank of the
Program Space that will be addressed. The 1.3.2.2 Program Memory Protection
number of the page has to be loaded in the PRPR
register. Refer to the Program Space description The Program Memory in OTP or EPROM devices
for additional information concerning the use of can be protected against external readout of mem-
this register. The PRPR register is not modified ory by selecting the READOUT PROTECTION op-
when an interrupt or a subroutine occurs. tion in the option byte.

Care is required when handling the PRPR register In the EPROM parts, READOUT PROTECTION
as it is write only. For this reason, it is not allowed option can be disactivated only by U.V. erasure
to change the PRPR contents while executing in- that also results into the whole EPROM context
terrupt service routine, as the service routine erasure.
cannot save and then restore its previous content.
Note: Once the Readout Protection is activated, it
This operation may be necessary if common rou-
is no longer possible, even for STMicroelectronics,
tines and interrupt service routines take more than
to gain access to the Program memory contents.
2K bytes; in this case it could be necessary to di- Returned parts with a protection set can therefore
vide the interrupt service routine into a (minor) part not be accepted.
in the static page (start and end) and to a second
(major) part in one of the dynamic pages. If it is im-
possible to avoid the writing of this register in inter-
rupt service routines, an image of this register
must be saved in a RAM location, and each time
the program writes to the PRPR it must write also
to the image register. The image register must be
written before PRPR, so if an interrupt occurs be-
tween the two instructions the PRPR is not af-
fected.

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ST62T18C/E18C

MEMORY MAP (Cont’d) Table 4. ST62T18C/E18C Data Memory Space

1.3.3 Data Space 000h
DATA RAM BANKS
03Fh
Data Space accommodates all the data necessary 040h
DATA ROM WINDOW AREA
for processing the user program. This space com- 07Fh
X REGISTER 080h
prises the RAM resource, the processor core and
Y REGISTER 081h
peripheral registers, as well as read-only data
V REGISTER 082h
such as constants and look-up tables in Program
W REGISTER 083h
memory.
084h
DATA RAM
1.3.3.1 Data ROM 0BFh
PORT A DATA REGISTER 0C0h
All read-only data is physically stored in program PORT B DATA REGISTER 0C1h
memory, which also accommodates the Program RESERVED 0C2h
Space. The program memory consequently con- PORT D DATA REGISTE R 0C3h
tains the program code to be executed, as well as PORT A DIRECTION REGISTE R 0C4h
the constants and look-up tables required by the PORT B DIRECTION REGISTE R 0C5h
application. RESERVED 0C6h
PORT D DIRECT ION REGISTE R 0C7h
The Data Space locations in which the different INTERRUPT OPTION REGISTER 0C8h*
constants and look-up tables are addressed by the DATA ROM WIND OW REGISTE R 0C9h*
processor core may be thought of as a 64-byte ROM BANK SELECT REGISTE R 0CAh*
window through which it is possible to access the RAM BANK SELECT REGISTE R 0CBh*
read-only data stored in Program memory. PORT A OPTION REGISTER 0CCh
1.3.3.2 Data RAM PORT B OPTION REGISTER 0CDh
RESERVED 0CEh
In ST62T18C and ST62E18C devices, the data PORT D OPTION REGISTER 0CFh
space includes 60 bytes of RAM, the accumulator A/D DATA REGISTER 0D0h
(A), the indirect registers (X), (Y), the short direct A/D CONTROL REGISTER 0D1h
registers (V), (W), the I/O port registers, the pe- TIMER 1 PRESCALE R REGISTER 0D2h
ripheral data and control registers, the interrupt TIMER 1 COUNTE R REGISTER 0D3h
option register and the Data ROM Window register TIMER 1 STATUS/CONTROL REGISTER 0D4h
(DRW register). RESERVED 0D5h
Additional RAM pages can also be addressed us- UART DATA SHIFT REGISTER 0D6h
ing banks of 64 bytes located between addresses UART STATUS CONTROL REGISTER 0D7h
00h and 3Fh. WATCHDOG REGISTER 0D8h
RESERVED 0D9h
I/O INTER RUPT POLARITY REGISTER 0DAh
1.3.4 Stack Space
RESERVED 0DCh*
Stack space consists of six 12-bit registers which RESERVED 0DDh
are used to stack subroutine and interrupt return 0DEh
RESERVED
addresses, as well as the current program counter 0E4h
ARTIMER MODE/CONTROL REGISTER 0E5h
contents.
ARTIME R STATUS/CONTROL REGISTER ARSC0 0E6h
Table 3. Additional RAM Banks ARTIME R STATUS/CONTROL REGISTER ARSC1 0E7h
RESERVED 0E8h
Device RAM ARTIMER RELOAD/CAPTURE REGIST ER 0E9h
ARTIMER COMPARE REGISTER 0EAh
ST62T18C/E18C 2 x 64 bytes
. ARTIMER LOAD REGISTER 0EBh
RESERVED 0ECh
ACCUMULATOR OFFh
* WRIT E ONLY REGISTER

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 ST62T18C/E18C

MEMORY MAP (Cont’d)

1.3.5 Data Window Register (DWR) Data Window Register (DWR)
The Data read-only memory window is located from Address: 0C9h — Write Only
address 0040h to address 007Fh in Data space. It
allows direct reading of 64 consecutive bytes locat- 7 0
ed anywhere in program memory, between ad-
dress 0000h and 1FFFh (top memory address de- - DWR6 DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
pends on the specific device). All the program
memory can therefore be used to store either in-
structions or read-only data. Indeed, the window Bits 7 = Not used.
can be moved in steps of 64 bytes along the pro-
gram memory by writing the appropriate code in the Bit 6-0 = DWR6-DWR0: Data read-only memory
Data Window Register (DWR). Window Register Bits. These are the Data read-
only memory Window bits that correspond to the
The DWR can be addressed like any RAM location upper bits of the data read-only memory space.
in the Data Space, it is however a write-only regis-
ter and therefore cannot be accessed using single- Caution: This register is undefined on reset. Nei-
bit operations. This register is used to position the ther read nor single bit instructions may be used to
64-byte read-only data window (from address 40h address this register.
to address 7Fh of the Data space) in program Note: Care is required when handling the DWR
memory in 64-byte steps. The effective address of register as it is write only. For this reason, the
the byte to be read as data in program memory is DWR contents should not be changed while exe-
obtained by concatenating the 6 least significant cuting an interrupt service routine, as the service
bits of the register address given in the instruction routine cannot save and then restore the register’s
(as least significant bits) and the content of the previous contents. If it is impossible to avoid writ-
DWR register (as most significant bits), as illustrat- ing to the DWR during the interrupt service routine,
ed in Figure 5 below. For instance, when address- an image of the register must be saved in a RAM
ing location 0040h of the Data Space, with 00h location, and each time the program writes to the
loaded in the DWR register, the physical location DWR, it must also write to the image register. The
addressed in program memory is 00h. The DWR image register must be written first so that, if an in-
register is not cleared on reset, therefore it must terrupt occurs between the two instructions, the
be written to prior to the first access to the Data DWR is not affected.
read-only memory window area.
Figure 5. Data read-only memory Window Memory Addressing

DATA ROM 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROGRAM SPACE ADDRESS

WINDOW REGISTER 7 READ
6 5 4 3 2 1 0
CONTENTS
5 4 3 2 1 0 DATA SPACE ADDRESS
(DWR)
0 1 40h-7Fh
IN INSTRUCTION

Example:
DWR=28h 0 1 0 1 0 0 0
DATA SPACE ADDRESS
0 1 0 1 1 0 0 1 59h

ROM
0 1 0 1 0 0 0 0 1 1 0 0 1
ADDRESS:A19h
VR01573A

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ST62T18C/E18C

MEMORY MAP (Cont’d)

1.3.6 Data RAM Bank Register (DRBR) the Data Space description for additional informa-
Address: CBh — Write only tion. The DRBR register is not modified when an
interrupt or a subroutine occurs.
7 0 Notes:
- - - DRBR4 DRBR3 - - -
Care is required when handling the DRBR register
as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in-
terrupt service routine, as the service routine can-
Bit 7-5 = These bits are not used not save and then restore its previous content. If it
Bit 4 - DRBR4. This bit, when set, selects RAM is impossible to avoid the writing of this register in
Page 2. interrupt service routine, an image of this register
Bit 3 - DRBR3. This bit, when set, selects RAM must be saved in a RAM location, and each time
Page 1. the program writes to DRBR it must write also to
the image register. The image register must be
Bit 2.0 These bits are not used. written first, so if an interrupt occurs between the
The selection of the bank is made by programming two instructions the DRBR is not affected.
the Data RAM Bank Switch register (DRBR regis- In DRBR Register, only 1 bit must be set. Other-
ter) located at address CBh of the Data Space ac- wise two or more pages are enabled in parallel,
cording to Table 1. No more than one bank should producing errors.
be set at a time.
The DRBR register can be addressed like a RAM Table 5. Data RAM Bank Register Set-up
Data Space location at the address CBh; never-
DRBR ST62T18C/E18C
theless it is a write only register that cannot be ac-
cessed with single-bit operations. This register is 00h None
used to select the desired 64-byte RAM bank of 01h Reserved
the Data Space. The number of banks has to be
loaded in the DRBR register and the instruction 02h Reserved
has to point to the selected location as if it was in 08h RAM Page 1
bank 0 (from 00h address to 3Fh address). 10h RAM Page 2
This register is not cleared during the MCU initiali- other Reserved
zation, therefore it must be written before the first
access to the Data Space bank region. Refer to

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 ST62T18C/E18C

1.4 PROGRAMMING MODES

1.4.1 Option Bytes EXTCNTL is low, STOP mode is not available with
The two Option Bytes allow configuration capabili- the watchdog active.
ty to the MCUs. Option byte’s content is automati- LVD. LVD RESET enable.When this bit is set, safe
cally read, and the selected options enabled, when RESET is performed by MCU when the supply
the chip reset is activated. voltage is too low. When this bit is cleared, only
It can only be accessed during the programming power-on reset or external RESET are active.
mode. This access is made either automatically PROTECT. Readout Protection. This bit allows the
(copy from a master device) or by selecting the protection of the software contents against piracy.
OPTION BYTE PROGRAMMING mode of the pro- When the bit PROTECT is set high, readout of the
grammer. OTP contents is prevented by hardware.. When
The option bytes are located in a non-user map. this bit is low, the user program can be read.
No address has to be specified. OSCIL. Oscillator selection. When this bit is low,
the oscillator must be controlled by a quartz crys-
tal, a ceramic resonator or an external frequency.
EPROM Code Option Byte (LSB) When it is high, the oscillator must be controlled by
an RC network, with only the resistor having to be
7 0
externally provided.
PRO- PORT NMI TIM OS-
TECT
OSCIL
PULL
-
PULL PULL
WDACT
GEN D5. Port Pull. This bit must be set high to have
pull-up input state at reset on the I/O port. When
this bit is low, I/O ports are in input without pull-up
(high impedance state at reset).
EPROM Code Option Byte (MSB)
D4. Reserved. Must be set to 1.
15 8 NMI PULL. NMI Pull-Up. This bit must be set high
ADC UART EXTC- to configure the NMI pin with a pull-up resistor.
- - - - LVD When it is low, no pull-up is provided.
SYNCHRO FRAME NTL
TIM PULL.TIM Pull-Up. This bit must be set high
D15-D13. Reserved. Must be cleared. to configure the TIMER pin with a pull-up resistor.
ADC SYNCHRO. When set, an A/D conversion is When it is low, no pull-up is provided.
started upon WAIT instruction execution, in order WDACT. This bit controls the watchdog activation.
to reduce supply noise. When this bit is low, an A/ When it is high, hardware activation is selected.
D conversion is started as soon as the STA bit of The software activation is selected when WDACT
the A/D Converter Control Register is set. is low.
D11. UART Frame. When set, UART transmission OSGEN. Oscillator Safe Guard. This bit must be
and reception are based on a 11-bit frame. When set high to enable the Oscillator Safe Guard.
cleared, a 10-bit frame is used. When this bit is low, the OSG is disabled.
D10. Reserved. This bit must be cleared The Option byte is written during programming ei-
EXTCNTL. External STOP MODE control.. When ther by using the PC menu (PC driven Mode) or
EXTCNTL is high, STOP mode is available with automatically (stand-alone mode).
watchdog active by setting NMI pin to one. When

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ST62T18C/E18C

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the Indirect Registers (X, Y). These two indirect reg-
I/O or Memory configuration. As such, it may be isters are used as pointers to memory locations in
thought of as an independent central processor Data space. They are used in the register-indirect
communicating with on-chip I/O, Memory and Pe- addressing mode. These registers can be ad-
ripherals via internal address, data, and control dressed in the data space as RAM locations at ad-
buses. In-core communication is arranged as dresses 80h (X) and 81h (Y). They can also be ac-
shown in Figure 6; the controller being externally cessed with the direct, short direct, or bit direct ad-
linked to both the Reset and Oscillator circuits, dressing modes. Accordingly, the ST6 instruction
while the core is linked to the dedicated on-chip pe- set can use the indirect registers as any other reg-
ripherals via the serial data bus and indirectly, for ister of the data space.
interrupt purposes, through the control registers. Short Direct Registers (V, W). These two regis-
ters are used to save a byte in short direct ad-
2.2 CPU REGISTERS dressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
The ST6 Family CPU core features six registers and
three pairs of flags available to the programmer. 83h (W). They can also be accessed using the di-
These are described in the following paragraphs. rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis-
Accumulator (A). The accumulator is an 8-bit ters as any other register of the data space.
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula- Program Counter (PC). The program counter is a
12-bit register which contains the address of the
tions. The accumulator can be addressed in Data
next ROM location to be processed by the core.
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any This ROM location may be an opcode, an oper-
other register in Data space. and, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.
Figure 6. ST6 Core Block Diagram
0,01 TO 8MHz
RESET
OSCin OSCout

INTERRUPTS
CONTROLLER
DATA SPACE

CONTROL
FLAG SIGNALS DATA
OPCODE VALUES ADDRESS /READ LINE
2 RAM/EEPR OM

PROGRAM
DATA
ROM/EPRO M ADDRESS 256
DECODER ROM/EPROM

A-DATA B-DATA
DEDICAT IONS

ACCUMULATOR
Program Counter
12 and FLAGS
6 LAYER STACK ALU
RESULTS TO DATA SPACE (WRITE LINE)
VR01811

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 ST62T18C/E18C

CPU REGISTERS (Cont’d)

However, if the program space contains more than automatically selected after the reset of the MCU,
4096 bytes, the additional memory in program the ST6 core uses at first the NMI flags.
space can be addressed by using the Program Stack. The ST6 CPU includes a true LIFO hard-
Bank Switch register. ware stack which eliminates the need for a stack
The PC value is incremented after reading the ad- pointer. The stack consists of six separate 12-bit
dress of the current instruction. To execute relative RAM locations that do not belong to the data
jumps, the PC and the offset are shifted through space RAM area. When a subroutine call (or inter-
the ALU, where they are added; the result is then rupt request) occurs, the contents of each level are
shifted back into the PC. The program counter can shifted into the next higher level, while the content
be changed in the following ways: of the PC is shifted into the first level (the original
- JP (Jump) instructionPC=Jump address contents of the sixth stack level are lost). When a
subroutine or interrupt return occurs (RET or RETI
- CALL instructionPC= Call address instructions), the first level register is shifted back
- Relative Branch Instruction.PC= PC +/- offset into the PC and the value of each level is popped
back into the previous level. Since the accumula-
- Interrupt PC=Interrupt vector
tor, in common with all other data space registers,
- Reset PC= Reset vector is not stored in this stack, management of these
- RET & RETI instructionsPC= Pop (stack) registers should be performed within the subrou-
tine. The stack will remain in its “deepest” position
- Normal instructionPC= PC + 1 if more than 6 nested calls or interrupts are execut-
Flags (C, Z). The ST6 CPU includes three pairs of ed, and consequently the last return address will
flags (Carry and Zero), each pair being associated be lost. It will also remain in its highest position if
with one of the three normal modes of operation: the stack is empty and a RET or RETI is executed.
Normal mode, Interrupt mode and Non Maskable In this case the next instruction will be executed.
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used lFigure 7. ST6 CPU Programming Mode
during Normal operation, another pair is used dur-
ing Interrupt mode (CI, ZI), and a third pair is used
b7 X REG. POINTER b0
in the Non Maskable Interrupt mode (CNMI, ZN- INDEX SHORT
MI). REGISTER DIRECT
b7 Y REG. POINTER b0
ADDRESSING
The ST6 CPU uses the pair of flags associated MODE
b7 V REGISTER b0
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6 b7 W REGISTER b0
CPU uses the Interrupt flags (resp. the NMI flags) b7 ACCUM ULATO R b0
instead of the Normal flags. When the RETI in-
struction is executed, the previously used set of
b11 PROGRAM COUNTER b0
flags is restored. It should be noted that each flag
set can only be addressed in its own context (Non
Maskable Interrupt, Normal Interrupt or Main rou-
tine). The flags are not cleared during context
switching and thus retain their status. SIX LEVELS
STACK REGISTER
The Carry flag is set when a carry or a borrow oc-
curs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction; it also partici-
NORMAL FLAGS C Z
pates in the rotate left instruction.
The Zero flag is set if the result of the last arithme- INTERRUPT FLAGS C Z
tic or logical operation was equal to zero; other-
wise it is cleared. NMI FLAGS C Z
Switching between the three sets of flags is per- VA000423
formed automatically when an NMI, an interrupt or
a RETI instructions occurs. As the NMI mode is

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ST62T18C/E18C

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES

3.1 CLOCK SYSTEM

The MCU features a Main Oscillator which can be Figure 8. Oscillator Configurations
driven by an external clock, or used in conjunction
with an AT-cut parallel resonant crystal or a suita- CRYSTAL/RES ONATOR CLOCK
ble ceramic resonator, or with an external resistor CRYSTAL/RESON ATOR option
(RNET). In addition, a Low Frequency Auxiliary Os-
cillator (LFAO) can be switched in for security rea-
sons, to reduce power consumption, or to offer the ST6xxx
benefits of a back-up clock system.
The Oscillator Safeguard (OSG) option filters OSCin OSCout
spikes from the oscillator lines, provides access to
the LFAO to provide a backup oscillator in the
event of main oscillator failure and also automati-
cally limits the internal clock frequency (f INT) as a
function of VDD, in order to guarantee correct oper- CL1n C L2
ation. These functions are illustrated in Figure 2,
Figure 3, Figure 4 and Figure 5.
Figure 1 illustrates various possible oscillator con- EXTERNAL CLOCK
figurations using an external crystal or ceramic res- CRYSTAL/RESON ATOR option
onator, an external clock input, an external resistor
(RNET), or the lowest cost solution using only the
ST6xxx
LFAO. CL1 an CL2 should have a capacitance in the
range 12 tST6_CLK1o 22 pF for an oscillator fre-
quency in the 4-8 MHz range. OSCin OSCout
The internal MCU clock frequency (fINT) is divided
by 12 to drive the Timer, the A/D converter and the NC
Watchdog timer, and by 13 to drive the CPU core,
as may be seen in Figure 4.
With an 8MHz oscillator frequency, the fastest ma- RC NETW ORK
RC NETW ORK option
chine cycle is therefore 1.625µs.
A machine cycle is the smallest unit of time needed
to execute any operation (for instance, to increment ST6xxx
the Program Counter). An instruction may require
two, four, or five machine cycles for execution. OSCin OSCout
3.1.1 Main Oscillator
NC
The oscillator configuration may be specified by se-
lecting theappropriate option.When the CRYSTAL/ RNET
RESONATORoption isselected, itmustbeusedwith
a quartz crystal, a ceramic resonator or an external
signal providedonthe OSCinpin.When theRC NET-
WORK option is selected, the system clock is gen- INTEGRA TED CLOCK
erated by an external resistor. CRYSTAL/RESON ATOR option
OSG ENABLED option
The main oscillator can be turned off (when the
OSG ENABLED option is selected) by setting the
OSCOFF bit of the ADC Control Register. The ST6xxx
Low Frequency Auxiliary Oscillator is automatical-
ly started. OSCin OSCout

NC

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 ST62T18C/E18C

CLOCK SYSTEM (Cont’d)

Turning on the main oscillator is achieved by re- tions: it filters spikes from the oscillator lines which
setting the OSCOFF bit of the A/D Converter Con- would result in over frequency to the ST62 CPU; it
trol Register or by resetting the MCU. Restarting gives access to the Low Frequency Auxiliary Os-
the main oscillator implies a delay comprising the cillator (LFAO), used to ensure minimum process-
oscillator start up delay period plus the duration of ing in case of main oscillator failure, to offer re-
the software instruction at fLFAO clock frequency. duced power consumption or to provide a fixed fre-
3.1.2 Low Frequency Auxiliary Oscillator quency low cost oscillator; finally, it automatically
(LFAO) limits the internal clock frequency as a function of
supply voltage, in order to ensure correct opera-
The Low Frequency Auxiliary Oscillator has three tion even if the power supply should drop.
main purposes. Firstly, it can be used to reduce
power consumption in non timing critical routines. The OSG is enabled or disabled by choosing the
Secondly, it offers a fully integrated system clock, relevant OSG option. It may be viewed as a filter
without any external components. Lastly, it acts as whose cross-over frequency is device dependent.
a safety oscillator in case of main oscillator failure. Spikes on the oscillator lines result in an effectively
This oscillator is available when the OSG ENA- increased internal clock frequency. In the absence
BLED option is selected. In this case, it automati- of an OSG circuit, this may lead to an over fre-
cally starts one of its periods after the first missing quency for a given power supply voltage. The
edge from the main oscillator, whatever the reason OSG filters out such spikes (as illustrated in Figure
(main oscillator defective, no clock circuitry provid- 2). In all cases, when the OSG is active, the maxi-
ed, main oscillator switched off...). mum internal clock frequency, fINT, is limited to
fOSG, which is supply voltage dependent. This re-
User code, normal interrupts, WAIT and STOP in- lationship is illustrated in Figure 5.
structions, are processed as normal, at the re-
duced fLFAO frequency. The A/D converter accura- When the OSG is enabled, the Low Frequency
cy is decreased, since the internal frequency is be- Auxiliary Oscillator may be accessed. This oscilla-
low 1MHz. tor starts operating after the first missing edge of
the main oscillator (see Figure 3).
At power on, the Low Frequency Auxiliary Oscilla-
tor starts faster than the Main Oscillator. It there- Over-frequency, at a given power supply level, is
fore feeds the on-chip counter generating the POR seen by the OSG as spikes; it therefore filters out
delay until the Main Oscillator runs. some cycles in order that the internal clock fre-
quency of the device is kept within the range the
The Low Frequency Auxiliary Oscillator is auto- particular device can stand (depending on VDD),
matically switched off as soon as the main oscilla- and below fOSG: the maximum authorised frequen-
tor starts. cy with OSG enabled.
ADCR Note. The OSG should be used wherever possible
Address: 0D1h — Read/Write as it provides maximum safety. Care must be tak-
en, however, as it can increase power consump-
7 0 tion and reduce the maximum operating frequency
ADCR ADCR ADCR ADCR ADCR OSC ADCR ADCR to fOSG.
7 6 5 4 3 OFF 1 0 Warning: Care has to be taken when using the
OSG, as the internal frequency is defined between
Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0: a minimum and a maximum value and is not accu-
ADC Control Register . These bits are not used. rate.
Bit 2 = OSCOFF. When low, this bit enables main For precise timing measurements, it is not recom-
oscillator to run. The main oscillator is switched off mended to use the OSG and it should not be ena-
when OSCOFF is high. bled in applications that use the SPI or the UART.
3.1.3 Oscillator Safe Guard It should also be noted that power consumption in
The Oscillator Safe Guard (OSG) affords drastical- Stop mode is higher when the OSG is enabled
ly increased operational integrity in ST62xx devic- (around 50µA at nominal conditions and room
es. The OSG circuit provides three basic func- temperature).

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ST62T18C/E18C

CLOCK SYSTEM (Cont’d)

Figure 9. OSG Filtering Principle

(1)

(2)

(3)

(4)

(1) Maximum Frequency for the device to work correctly

(2) Actual Quartz Crystal Frequency at OSCin pin
(3) Noise from OSCin
(4) Resulting Internal Frequency VR001932

Figure 10. OSG Emergency Oscillator Principle

Main
Oscillator

Emergency
Oscillator

Internal
Frequency

VR001933

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 ST62T18C/E18C

CLOCK SYSTEM (Cont’d)

Figure 11. Clock Circuit Block Diagram

POR

: 13 Core
OSG

TIMER 1

MAIN M fINT Watchdog

OSCILLATOR U : 12
X

LFAO

:1

Main Oscillator off

Figure 12. Maximum Operating Frequency (fMAX) versus Supply Voltage (VDD)

Maximum FREQU ENCY (MHz)

7 4
FUNCTIONALITY IS NOT

3
6
fOSG
GUARANTEED
IN THIS AREA

5
fOSG Min (at 85°C)
4 2

3
fOSG Min (at 125°C)
2
1
1
2.5 3 3.6 4 4.5 5 5.5 6

SUPPLY VOLTAGE (VDD )

VR01807J

Notes:
1. In this area, operation is guaranteed at the area is guaranteed at the quartz crystal frequency.
quartz crystal frequency. When the OSG is enabled, access to this area is
2. When the OSG is disabled, operation in this prevented. The internal frequency is kept a fOSG.
area is guaranteed at the crystal frequency. When 4. When the OSG is disabled, operation in this
the OSG is enabled, operation in this area is guar- area is not guaranteed
anteed at a frequency of at least fOSG Min. When the OSG is enabled, access to this area is
3. When the OSG is disabled, operation in this prevented. The internal frequency is kept at fOSG.

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ST62T18C/E18C

3.2 RESETS
The MCU can be reset in four ways: is executed immediately following the internal de-
– by the external Reset input being pulled low; lay.
– by Power-on Reset; To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a suffi-
– by the digital Watchdog peripheral timing out. cient level for the chosen frequency (see recom-
– by Low Voltage Detection (LVD) mended operation) before the reset signal is re-
3.2.1 RESET Input leased. In addition, supply rising must start from
0V.
The RESET pin may be connected to a device of
the application board in order to reset the MCU if As a consequence, the POR does not allow to su-
required. The RESET pin may be pulled low in pervise static, slowly rising, or falling, or noisy
RUN, WAIT or STOP mode. This input can be (presenting oscillation) VDD supplies.
used to reset the MCU internal state and ensure a An external RC network connected to the RESET
correct start-up procedure. The pin is active low pin, or the LVD reset can be used instead to get
and features a Schmitt trigger input. The internal the best performances.
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on Figure 13. Reset and Interrupt Processing
the RESET pin are acceptable, provided VDD has
completed its rising phase and that the oscillator is RESET
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset state as long as the
RESET pin is held low.
NMI MASK SET
If RESET activation occurs in the RUN or WAIT INT LATCH CLEARED
( IF PRESENT )
modes, processing of the user program is stopped
(RUN mode only), the Inputs and Outputs are con-
figured as inputs with pull-up resistors and the
main Oscillator is restarted. When the level on the SELECT
NMI MODE FLAGS
RESET pin then goes high, the initialization se-
quence is executed following expiry of the internal
delay period.
If RESET pin activation occurs in the STOP mode, PUT FFEH
ON ADDRESS BUS
the oscillator starts up and all Inputs and Outputs
are configured as inputs with pull-up resistors.
When the level of the RESET pin then goes high,
the initialization sequence is executed following
expiry of the internal delay period. YES
IS RESET STILL
3.2.2 Power-on Reset PRESENT?

The function of the POR circuit consists in waking

up the MCU by detecting around 2V a dynamic NO
(rising edge) variation of the VDD Supply. At the
beginning of this sequence, the MCU is configured LOAD PC
FROM RESET LOCATIONS
in the Reset state: all I/O ports are configured as FFE/FFF
inputs with pull-up resistors and no instruction is
executed. When the power supply voltage rises to
a sufficient level, the oscillator starts to operate,
whereupon an internal delay is initiated, in order to FETCH INSTRUCTION
allow the oscillator to fully stabilize before execut-
ing the first instruction. The initialization sequence VA000427

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 ST62T18C/E18C

RESETS (Cont’d)
3.2.3 Watchdog Reset ues, allowing hysteresis effect. Reference value in
The MCU provides a Watchdog timer function in case of voltage drop has been set lower than the
order to ensure graceful recovery from software reference value for power-on in order to avoid any
upsets. If the Watchdog register is not refreshed parasitic Reset when MCU start’s running and
before an end-of-count condition is reached, the sinking current on the supply.
internal reset will be activated. This, amongst oth- As long as the supply voltage is below the refer-
er things, resets the watchdog counter. ence value, there is a internal and static RESET
command. The MCU can start only when the sup-
The MCU restarts just as though the Reset had ply voltage rises over the reference value. There-
been generated by the RESET pin, including the fore, only two operating mode exist for the MCU:
built-in stabilisation delay period. RESET active below the voltage reference, and
3.2.4 LVD Reset running mode over the voltage reference as
shown on the Figure 14, that represents a power-
The on-chip Low Voltage Detector, selectable as up, power-down sequence.
user option, features static Reset when supply
voltage is below a reference value. Thanks to this Note: When the RESET state is controlled by one
feature, external reset circuit can be removed of the internal RESET sources (Low Voltage De-
while keeping the application safety. This SAFE tector, Watchdog, Power on Reset), the RESET
RESET is effective as well in Power-on phase as pin is tied to low logic level.
in power supply drop with different reference val-
Figure 14. LVD Reset on Power-on and Power-down (Brown-out)

VDD

VUp

Vdn

RESET
RESET

time
VR02106A

3.2.5 Application Notes

No external resistor is required between VDD and Direct external connection of the pin RESET to
the Reset pin, thanks to the built-in pull-up device. VDD must be avoided in order to ensure safe be-
haviour of the internal reset sources (AND.Wired
structure).

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ST62T18C/E18C

RESETS (Cont’d)
3.2.6 MCU Initialization Sequence Figure 15. Reset and Interrupt Processing
When a reset occurs the stack is reset, the PC is
RESET
loaded with the address of the Reset Vector (locat-
ed in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the In- JP JP:2 BYTES/4 CYCLES
terrupt flag is automatically set, so that the CPU is RESET
in Non Maskable Interrupt mode; this prevents the VECTOR

initialisation routine from being interrupted. The in-

itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. If no pending interrupt
is present at the end of the initialisation routine, the INITIALIZATION
MCU will continue by processing the instruction ROUTINE RETI: 1 BYTE/2 CYCLES
immediately following the RETI instruction. If, how- RETI
ever, a pending interrupt is present, it will be serv-
iced. VA00181

Figure 16. Reset Block Diagram

VDD
ST6
fOSC CK INTERNA L
RESET

RPU COUNTER
AND. Wired
RESD1)
RESET RESET
RESET

POWER ON RESET
WATCHD OG RESET
LVD RESET

VR02107A

1) Resistive ESD protection. Value not guaranteed.

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 ST62T18C/E18C

RESETS (Cont’d)
Table 6. Register Reset Status
Register Address(es) Status Comment
Port Data Registers 0C0h, 0C1h, 0C3h I/O are Input with or without pull-up
Port Direction Register 0C4h, 0C5h, 0C7h depending on PORT PULL option
Port Option Register 0CCh, 0CDh, 0CFh
Interrupt Option Register 0C8h Interrupt disabled
TIMER Status/Control 0D4h 00h TIMER disabled

AR TIMER Mode/Control Register 0E5h AR TIMER disabled

AR TIMER Status/Control Register 0 0E6h
AR TIMER Status/Control Register 1 0E7h
X, Y, V, W, Register 080H TO 083H
Accumulator 0FFh
Data RAM 084h to 0BFh
Data RAM Page Register 0CBh
Data ROM Window Register 0C9h Undefined
A/D Result Register 0D0h
ARTIMER Reload/Capture Register 0E9h
ARTIMER Compare Registers 0EAh
ARTIMER Load Registers 0EBh
TIMER Counter Register 0D3h FFh
TIMER Prescaler Register 0D2h 7Fh Max count loaded
Watchdog Counter Register 0D8h FEh
A/D Control Register 0D1h 40h A/D in Stand-by
UART Status Control 0D7h UART disabled

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ST62T18C/E18C

3.3 DIGITAL WATCHDOG

The digital Watchdog consists of a reloadable When the Watchdog is disabled, low power Stop
downcounter timer which can be used to provide mode is available. Once activated, the Watchdog
controlled recovery from software upsets. cannot be disabled, except by resetting the MCU.
The Watchdog circuit generates a Reset when the In the HARDWARE option, the Watchdog is per-
downcounter reaches zero. User software can manently enabled. Since the oscillator will run con-
prevent this reset by reloading the counter, and tinuously, low power mode is not available. The
should therefore be written so that the counter is STOP instruction is interpreted as a WAIT instruc-
regularly reloaded while the user program runs tion, and the Watchdog continues to countdown.
correctly. In the event of a software mishap (usual- However, when the EXTERNAL STOP MODE
ly caused by externally generated interference), CONTROL option has been selected low power
the user program will no longer behave in its usual consumption may be achieved in Stop Mode.
fashion and the timer register will thus not be re-
loaded periodically. Consequently the timer will Execution of the STOP instruction is then gov-
decrement down to 00h and reset the MCU. In or- erned by a secondary function associated with the
der to maximise the effectiveness of the Watchdog NMI pin. If a STOP instruction is encountered
function, user software must be written with this when the NMI pin is low, it is interpreted as WAIT,
concept in mind. as described above. If, however, the STOP in-
struction is encountered when the NMI pin is high,
Watchdog behaviour is governed by two options, the Watchdog counter is frozen and the CPU en-
known as “WATCHDOG ACTIVATION” (i.e. ters STOP mode.
HARDWARE or SOFTWARE) and “EXTERNAL
STOP MODE CONTROL” (see Table 7). When the MCU exits STOP mode (i.e. when an in-
terrupt is generated), the Watchdog resumes its
In the SOFTWARE option, the Watchdog is disa- activity.
bled until bit C of the DWDR register has been set.

Table 7. Recommended Option Choices

Functions Required Recommended Options
Stop Mode & Watchdog “EXTERNAL STOP MODE” & “HARDWARE WATCHDOG”
Stop Mode “SOFTWARE WATCHDOG”
Watchdog “HARDWARE WATCHDOG”

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 ST62T18C/E18C

DIGITAL WATCHDOG (Cont’d)

The Watchdog is associated with a Data space Figure 17. Watchdog Counter Control
register (Digital WatchDog Register, DWDR, loca-
tion 0D8h) which is described in greater detail in
Section 3.3.1 Digital Watchdog Register (DWDR).
This register is set to 0FEh on Reset: bit C is
cleared to “0”, which disables the Watchdog; the D0 C
timer downcounter bits, T0 to T5, and the SR bit
are all set to “1”, thus selecting the longest Watch-
dog timer period. This time period can be set to the D1 SR

WATCHDOG CONTROL REGISTER

user’s requirements by setting the appropriate val-
ue for bits T0 to T5 in the DWDR register. The SR

WATCHDOG COUNTER
RESET
bit must be set to “1”, since it is this bit which gen- D2 T5
erates the Reset signal when it changes to “0”;
clearing this bit would generate an immediate Re-
set. D3 T4
It should be noted that the order of the bits in the
DWDR register is inverted with respect to the as-
sociated bits in the down counter: bit 7 of the D4 T3
DWDR register corresponds, in fact, to T0 and bit
2 to T5. The user should bear in mind the fact that
these bits are inverted and shifted with respect to D5 T2
the physical counter bits when writing to this regis-
ter. The relationship between the DWDR register
bits and the physical implementation of the Watch- D6 T1
dog timer downcounter is illustrated in Figure 17.
Only the 6 most significant bits may be used to de- D7 T0
fine the time period, since it is bit 6 which triggers
the Reset when it changes to “0”. This offers the
user a choice of 64 timed periods ranging from
3,072 to 196,608 clock cycles (with an oscillator ÷28 OSC ÷12
frequency of 8MHz, this is equivalent to timer peri-
ods ranging from 384µs to 24.576ms). VR02068A

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ST62T18C/E18C

DIGITAL WATCHDOG (Cont’d)

3.3.1 Digital Watchdog Register (DWDR) 3.3.2 Application Notes
Address: 0D8h — Read/Write The Watchdog plays an important supporting role
Reset status: 1111 1110b in the high noise immunity of ST62xx devices, and
should be used wherever possible. Watchdog re-
7 0 lated options should be selected on the basis of a
trade-off between application security and STOP
T0 T1 T2 T3 T4 T5 SR C mode availability.
When STOP mode is not required, hardware acti-
Bit 0 = C: Watchdog Control bit vation without EXTERNAL STOP MODE CON-
If the hardware option is selected, this bit is forced TROL should be preferred, as it provides maxi-
high and the user cannot change it (the Watchdog mum security, especially during power-on.
is always active). When the software option is se- When STOP mode is required, hardware activa-
lected, the Watchdog function is activated by set- tion and EXTERNAL STOP MODE CONTROL
ting bit C to 1, and cannot then be disabled (save should be chosen. NMI should be high by default,
by resetting the MCU). to allow STOP mode to be entered when the MCU
When C is kept low the counter can be used as a is idle.
7-bit timer. The NMI pin can be connected to an I/O line (see
This bit is cleared to “0” on Reset. Figure 18) to allow its state to be controlled by soft-
ware. The I/O line can then be used to keep NMI
Bit 1 = SR: Software Reset bit low while Watchdog protection is required, or to
This bit triggers a Reset when cleared. avoid noise or key bounce. When no more
processing is required, the I/O line is released and
When C = “0” (Watchdog disabled) it is the MSB of the device placed in STOP mode for lowest power
the 7-bit timer. consumption.
This bit is set to “1” on Reset. When software activation is selected and the
Bits 2-7 = T5-T0: Downcounter bits Watchdog is not activated, the downcounter may
be used as a simple 7-bit timer (remember that the
It should be noted that the register bits are re-
bits are in reverse order).
versed and shifted with respect to the physical
counter: bit-7 (T0) is the LSB of the Watchdog The software activation option should be chosen
downcounter and bit-2 (T5) is the MSB. only when the Watchdog counter is to be used as
a timer. To ensure the Watchdog has not been un-
These bits are set to “1” on Reset.
expectedly activated, the following instructions
should be executed within the first 27 instructions:
jrr 0, WD, #+3
ldi WD, 0FDH

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 ST62T18C/E18C

DIGITAL WATCHDOG (Cont’d)

These instructions test the C bit and Reset the Figure 18. A typical circuit making use of the
MCU (i.e. disable the Watchdog) if the bit is set EXERNAL STOP MODE CONTROL feature
(i.e. if the Watchdog is active), thus disabling the
Watchdog.
In all modes, a minimum of 28 instructions are ex-
ecuted after activation, before the Watchdog can
SWITCH
generate a Reset. Consequently, user software
should load the watchdog counter within the first NMI
27 instructions following Watchdog activation
(software mode), or within the first 27 instructions
executed following a Reset (hardware activation).
I/O
It should be noted that when the GEN bit is low (in-
terrupts disabled), the NMI interrupt is active but
cannot cause a wake up from STOP/WAIT modes.

VR02002

Figure 19. Digital Watchdog Block Diagram

RESET

Q
RSFF -27 -2 8 -12
S R DB 1.7 LOAD SET SET

OSCILLATOR
8 CLOCK
DB0

WRITE
RESET
DATA BUS
VA00010

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ST62T18C/E18C

3.4 IINTERRUPTS
The CPU can manage four Maskable Interrupt ically reset by the core at the beginning of the non-
sources, in addition to a Non Maskable Interrupt maskable interrupt service routine.
source (top priority interrupt). Each source is asso- Interrupt request from source #1 can be config-
ciated with a specific Interrupt Vector which con- ured either as edge or level sensitive by setting ac-
tains a Jump instruction to the associated interrupt cordingly the LES bit of the Interrupt Option Regis-
service routine. These vectors are located in Pro- ter (IOR).
gram space (see Table 8).
Interrupt request from source #2 are always edge
When an interrupt source generates an interrupt sensitive. The edge polarity can be configured by
request, and interrupt processing is enabled, the setting accordingly the ESB bit of the Interrupt Op-
PC register is loaded with the address of the inter- tion Register (IOR).
rupt vector (i.e. of the Jump instruction), which
then causes a Jump to the relevant interrupt serv- Interrupt request from sources #3 & #4 are level
ice routine, thus servicing the interrupt. sensitive.
Interrupt sources are linked to events either on ex- In edge sensitive mode, a latch is set when a edge
ternal pins, or on chip peripherals. Several events occurs on the interrupt source line and is cleared
can be ORed on the same interrupt source, and when the associated interrupt routine is started.
relevant flags are available to determine which So, the occurrence of an interrupt can be stored,
event triggered the interrupt. until completion of the running interrupt routine be-
fore being processed. If several interrupt requests
The Non Maskable Interrupt request has the high- occurs before completion of the running interrupt
est priority and can interrupt any interrupt routine routine, only the first request is stored.
at any time; the other four interrupts cannot inter-
rupt each other. If more than one interrupt request Storage of interrupt requests is not available in lev-
is pending, these are processed by the processor el sensitive mode. To be taken into account, the
core according to their priority level: source #1 has low level must be present on the interrupt pin when
the higher priority while source #4 the lower. The the MCU samples the line after instruction execu-
priority of each interrupt source is fixed. tion.
At the end of every instruction, the MCU tests the
Table 8. Interrupt Vector Map interrupt lines: if there is an interrupt request the
Interrupt Source Priority Vector Address next instruction is not executed and the appropri-
ate interrupt service routine is executed instead.
Interrupt source #0 1 (FFCh-FFDh)
Interrupt source #1 2 (FF6h-FF7h) Table 9. Interrupt Option Register Description
Interrupt source #2 3 (FF4h-FF5h)
SET Enable all interrupts
Interrupt source #3 4 (FF2h-FF3h) GEN
CLEARED Disable all interrupts
Interrupt source #4 5 (FF0h-FF1h)
Rising edge mode on inter-
SET
rupt source #2
3.4.1 Interrupt request ESB
Falling edge mode on inter-
CLEARED
All interrupt sources but the Non Maskable Inter- rupt source #2
rupt source can be disabled by setting accordingly Level-sensitive mode on in-
SET
the GEN bit of the Interrupt Option Register (IOR). terrupt source #1
LES
This GEN bit also defines if an interrupt source, in- Falling edge mode on inter-
cluding the Non Maskable Interrupt source, can re- CLEARED
rupt source #1
start the MCU from STOP/WAIT modes. OTHERS NOT USED
Interrupt request from the Non Maskable Interrupt
source #0 is latched by a flip flop which is automat-

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 ST62T18C/E18C

INTERRUPTS (Cont’d)
3.4.2 Interrupt Procedure MCU
The interrupt procedure is very similar to a call pro- – Automatically the MCU switches back to the nor-
cedure, indeed the user can consider the interrupt mal flag set (or the interrupt flag set) and pops
as an asynchronous call procedure. As this is an the previous PC value from the stack.
asynchronous event, the user cannot know the The interrupt routine usually begins by the identify-
context and the time at which it occurred. As a re- ing the device which generated the interrupt re-
sult, the user should save all Data space registers quest (by polling). The user should save the regis-
which may be used within the interrupt routines. ters which are used within the interrupt routine in a
There are separate sets of processor flags for nor- software stack. After the RETI instruction is exe-
mal, interrupt and non-maskable interrupt modes, cuted, the MCU returns to the main routine.
which are automatically switched and so do not
need to be saved. Figure 20. Interrupt Processing Flow Chart
The following list summarizes the interrupt proce- INS TRU CTION
dure:
MCU
FETCH
– The interrupt is detected. INS TRU CTION

– The C and Z flags are replaced by the interrupt

flags (or by the NMI flags).
EXEC UTE
– The PC contents are stored in the first level of IN STRUC TION
the stack.
– The normal interrupt lines are inhibited (NMI still LOAD PC FROM
active). WAS
NO INT ERR UP T VEC TOR
THE INS TRU CTION (FFC/FFD)
– The first internal latch is cleared. A RE TI ?

– Theassociated interrupt vectoris loaded inthe PC. YES

WARNING: In some circumstances, when a YES

IS THE CORE
ALREADY IN
SET
INTER RU PT MASK
?
maskable interrupt occurs while the ST6 core is in NORMAL MODE?

NORMAL mode and especially during the execu- NO

tion of an ”ldi IOR, 00h” instruction (disabling all C LEAR PUSH THE
maskable interrupts): if the interrupt arrives during INT ERR UP T MASK
PC IN TO THE STACK
the first 3 cycles of the ”ldi” instruction (which is a
4-cycle instruction) the core will switch to interrupt
mode BUT the flags CN and ZN will NOT switch to SELECT
PROGRAM FLAGS
the interrupt pair CI and ZI. SELECT
IN TER NA L MODE FLAG

User
– User selected registers are saved within the in- ”POP”
THE STACK ED PC
terrupt service routine (normally on a software
stack).
– The source of the interrupt is found by polling the NO C HEC K IF THER E IS
AN IN TER RUP T R EQUEST
?
interrupt flags (if more than one source is associ- AN D INTE RRU PT MASK

ated with the same vector). YES

VA000014
– The interrupt is serviced.
– Return from interrupt (RETI)

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ST62T18C/E18C

INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR) Bit 5 = ESB: Edge Selection bit.
The Interrupt Option Register (IOR) is used to en- The bit ESB selects the polarity of the interrupt
able/disable the individual interrupt sources and to source #2.
select the operating mode of the external interrupt Bit 4 = GEN: Global Enable Interrupt. When this bit
inputs. This register is write-only and cannot be is set to one, all interrupts are enabled. When this
accessed by single-bit operations. bit is cleared to zero all the interrupts (excluding
Address: 0C8h — Write Only NMI) are disabled.
Reset status: 00h When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
7 0 modes.
- LES ESB GEN - - - - This register is cleared on reset.
3.4.4 Interrupt sources
Bit 7, Bits 3-0 = Unused. Interrupt sources available on the ST62E18C/
T18C are summarized in the Table 10 with associ-
Bit 6 = LES: Level/Edge Selection bit. ated mask bit to enable/disable the interrupt re-
When this bit is set to one, the interrupt source #1 quest.
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Table 10. Interrupt Requests and Mask Bits
Address Interrupt
Peripheral Register Mask bit Masked Interrupt Source
Register source
GENERAL IOR C8h GEN All Interrupts, excluding NMI All
TIMER TSCR1 D4h ETI TMZ: TIMER Overflow source 4
A/D CONVERTER ADCR D1h EAI EOC: End of Conversion source 4
RXIEN RXRDY: Byte received
UART UARTCR D7h source 4
TXIEN TXMT: Byte sent
OVIE OVF: ARTIMER Overflow
ARTIMER ARMC E5h CPIE CPF: Successful compare source 3
EIE EF: Active edge on ARTIMin
SPI SIDR DCh ALL End of Transmission source 1
Port PAn ORPA-DRPA C0h-C4h ORPAn-DRPAn PAn pin source 1
Port PBn ORPB-DRPB C1h-C5h ORPBn-DRPBn PBn pin source 2
Port PDn ORPD-DRPD C3h-C7h ORPDn-DRPDn PDn pin source 2

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 ST62T18C/E18C

INTERRUPTS (Cont’d)
Interrupt Polarity Register (IPR) generates interrupt on rising edge. At reset, IPR is
cleared and all port interrupts are not inverted (e.g.
Address: DAh — Read/Write Port C generates interrupts on falling edges).
7 0 Bit 7 - Bit 4 = Unused.
- - - - PortD - PortA PortB Bit 3 = Port D Interrupt Polarity.
Bit 2 = Unused.
In conjunction with I/O register ESB bit, the polarity Bit 1= Port A Interrupt Polarity.
of I/O pins triggered interrupts can be selected by
setting accordingly the Interrupt Polarity Register Bit 0 = Port B Interrupt Polarity.
(IPR). If a bit in IPR is set to one the corresponding
port interrupt is inverted (e.g. IPR bit 2 = A; port C
Tables 11. I/O Interrupts selections according to IPR, IOR programming
Interrupt
GEN IPR3 IPR0 IOR5 Port B occurrence Port D occurrence
source
1 0 0 0 falling edge falling edge
1 0 0 1 rising edge rising edge
1 0 1 0 rising edge falling edge
1 0 1 1 falling edge rising edge
1 1 0 0 falling edge rising edge 2
1 1 0 1 rising edge falling edge
1 1 1 0 rising edge rising edge
1 1 1 1 falling edge falling edge
0 X X X Disabled Disabled

Interrupt
GEN IPR1 IOR6 Port A occurrence
source
1 0 0 falling edge
1 0 1 low level
1 1 0 rising edge 1
1 1 1 high level
0 X X Disabled

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ST62T18C/E18C

INTERRUPTS (Cont’d)
Figure 21. Interrupt Block Diagram

FF
NMI INT #0 NMI (FFC,D))
CLK Q
CLR
FROM REGIST ER PORT A,B,D
SINGLE BIT ENABLE I0 Start

PBE

VDD

IPR Bit 1
FF
PORT A CLK Q 0
Bits CLR
MUX INT #1 (FF6,7)
I1 Start

IOR bit 6 (LES)

RESTART
FROM
IPR Bit 0 STOP/WAIT
FF
PORT B PBE CLK Q INT #2 (FF4,5)
Bits CLR

I2 Start
IOR bit 5 (ESB)
IPR Bit 3

PORT D PBE
Bits
OVF
OVIE

ARTIMER CPF INT #3 (FF2,3)

CPIE

EF
EIE

TMZ
ETI
TIMER 1
EAI INT #4 (FF0,1)
EOC
RXRDY
RXIEN
UART
TXMT IOR bit 4(GEN)
TXIEN

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 ST62T18C/E18C

3.5 POWER SAVING MODES

The WAIT and STOP modes have been imple- of the processor core prior to the WAIT instruction,
mented in the ST62xx family of MCUs in order to but also on the kind of interrupt request which is
reduce the product’s electrical consumption during generated. This is described in the following para-
idle periods. These two power saving modes are graphs. The processor core does not generate a
described in the following paragraphs. delay following the occurrence of the interrupt, be-
3.5.1 WAIT Mode cause the oscillator clock is still available and no
stabilisation period is necessary.
The MCU goes into WAIT mode as soon as the 3.5.2 STOP Mode
WAIT instruction is executed. The microcontroller
can be considered as being in a “software frozen” If the Watchdog is disabled, STOP mode is availa-
state where the core stops processing the pro- ble. When in STOP mode, the MCU is placed in
gram instructions, the RAM contents and peripher- the lowest power consumption mode. In this oper-
al registers are preserved as long as the power ating mode, the microcontroller can be considered
supply voltage is higher than the RAM retention as being “frozen”, no instruction is executed, the
voltage. In this mode the peripherals are still ac- oscillator is stopped, the RAM contents and pe-
tive. ripheral registers are preserved as long as the
power supply voltage is higher than the RAM re-
WAIT mode can be used when the user wants to tention voltage, and the ST62xx core waits for the
reduce the MCU power consumption during idle occurrence of an external interrupt request or a
periods, while not losing track of time or the capa- Reset to exit the STOP state.
bility of monitoring external events. The active os-
cillator is not stopped in order to provide a clock If the STOP state is exited due to a Reset (by acti-
signal to the peripherals. Timer counting may be vating the external pin) the MCU will enter a nor-
enabled as well as the Timer interrupt, before en- mal reset procedure. Behaviour in response to in-
tering the WAIT mode: this allows the WAIT mode terrupts depends on the state of the processor
to be exited when a Timer interrupt occurs. The core prior to issuing the STOP instruction, and
same applies to other peripherals which use the also on the kind of interrupt request that is gener-
clock signal. ated.
If the WAIT mode is exited due to a Reset (either This case will be described in the following para-
by activating the external pin or generated by the graphs. The processor core generates a delay af-
Watchdog), the MCU enters a normal reset proce- ter occurrence of the interrupt request, in order to
dure. If an interrupt is generated during WAIT wait for complete stabilisation of the oscillator, be-
mode, the MCU’s behaviour depends on the state fore executing the first instruction.

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ST62T18C/E18C

POWER SAVING MODE (Cont’d)

3.5.3 Exit from WAIT and STOP Modes tered will be completed, starting with the
execution of the instruction which follows the
The following paragraphs describe how the MCU STOP or the WAIT instruction, and the MCU is
exits from WAIT and STOP modes, when an inter- still in the interrupt mode. At the end of this rou-
rupt occurs (not a Reset). It should be noted that tine pending interrupts will be serviced in accord-
the restart sequence depends on the original state
of the MCU (normal, interrupt or non-maskable in- ance with their priority.
terrupt mode) prior to entering WAIT or STOP – In the event of a non-maskable interrupt, the
mode, as well as on the interrupt type. non-maskable interrupt service routine is proc-
essed first, then the routine in which the WAIT or
Interrupts do not affect the oscillator selection. STOP mode was entered will be completed by
3.5.3.1 Normal Mode executing the instruction following the STOP or
WAIT instruction. The MCU remains in normal
If the MCU was in the main routine when the WAIT interrupt mode.
or STOP instruction was executed, exit from Stop
or Wait mode will occur as soon as an interrupt oc- Notes:
curs; the related interrupt routine is executed and,
on completion, the instruction which follows the To achieve the lowest power consumption during
STOP or WAIT instruction is then executed, pro- RUN or WAIT modes, the user program must take
viding no other interrupts are pending. care of:
3.5.3.2 Non Maskable Interrupt Mode – configuring unused I/Os as inputs without pull-up
(these should be externally tied to well defined
If the STOP or WAIT instruction has been execut- logic levels);
ed during execution of the non-maskable interrupt
routine, the MCU exits from the Stop or Wait mode – placing all peripherals in their power down
as soon as an interrupt occurs: the instruction modes before entering STOP mode;
which follows the STOP or WAIT instruction is ex-
ecuted, and the MCU remains in non-maskable in- When the hardware activated Watchdog is select-
terrupt mode, even if another interrupt has been ed, or when the software Watchdog is enabled, the
generated. STOP instruction is disabled and a WAIT instruc-
tion will be executed in its place.
3.5.3.3 Normal Interrupt Mode
If all interrupt sources are disabled (GEN low), the
If the MCU was in interrupt mode before the STOP MCU can only be restarted by a Reset. Although
or WAIT instruction was executed, it exits from setting GEN low does not mask the NMI as an in-
STOP or WAIT mode as soon as an interrupt oc- terrupt, it will stop it generating a wake-up signal.
curs. Nevertheless, two cases must be consid-
ered: The WAIT and STOP instructions are not execut-
– If the interrupt is a normal one, the interrupt rou- ed if an enabled interrupt request is pending.
tine in which the WAIT or STOP mode was en-

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 ST62T18C/E18C

4 ON-CHIP PERIPHERALS

4.1 I/O PORTS

The MCU features Input/Output lines which may be also written by user software, in conjunction
be individually programmed as any of the following with the related option registers, to select the dif-
input or output configurations: ferent input mode options.
– Input without pull-up or interrupt Single-bit operations on I/O registers are possible
– Input with pull-up and interrupt but care is necessary because reading in input
mode is done from I/O pins while writing will direct-
– Input with pull-up, but without interrupt ly affect the Port data register causing an unde-
– Analog input sired change of the input configuration.
– Push-pull output The Data Direction registers (DDRx) allow the
data direction (input or output) of each pin to be
– Open drain output
set.
The lines are organised as bytewise Ports.
The Option registers (ORx) are used to select the
Each port is associated with 3 registers in Data different port options available both in input and in
space. Each bit of these registers is associated output mode.
with a particular line (for instance, bits 0 of Port A
All I/O registers can be read or written to just as
Data, Direction and Option registers are associat-
ed with the PA0 line of Port A). any other RAM location in Data space, so no extra
RAM cells are needed for port data storage and
The DATA registers (DRx), are used to read the manipulation. During MCU initialization, all I/O reg-
voltage level values of the lines which have been isters are cleared and the input mode with pull-ups
configured as inputs, or to write the logic value of and no interrupt generation is selected for all the
the signal to be output on the lines configured as pins, thus avoiding pin conflicts.
outputs. The port data registers can be read to get
the effective logic levels of the pins, but they can
Figure 22. I/O Port Block Diagram

RESET VDD
SIN CONTROLS

DATA VDD
DIRECTION
REGISTE R

INPUT /OUTPUT

DATA
REGISTE R
SHIFT
REGIST ER

OPTION
REGISTE R

SOUT
TO INTERRU PT

TO ADC
VA00413

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ST62T18C/E18C

I/O PORTS (Cont’d)

4.1.1 Operating Modes 4.1.1.2 Interrupt Options
Each pin may be individually programmed as input All input lines can be individually connected by
or output with various configurations. software to the interrupt system by programming
This is achieved by writing the relevant bit in the the OR and DR registers accordingly. The inter-
Data (DR), Data Direction (DDR) and Option reg- rupt trigger modes (falling edge, rising edge and
isters (OR). Table 12 illustrates the various port low level) can be configured by software as de-
configurations which can be selected by user soft- scribed in the Interrupt Chapter for each port.
ware. 4.1.1.3 Analog Input Options
4.1.1.1 Input Options Some pins can be configured as analog inputs by
Pull-up, High Impedance Option. All input lines programming the OR and DR registers according-
can be individually programmed with or without an ly. These analog inputs are connected to the on-
internal pull-up by programming the OR and DR chip 8-bit Analog to Digital Converter. ONLY ONE
registers accordingly. If the pull-up option is not pin should be programmed as an analog input at
selected, the input pin will be in the high-imped- any time, since by selecting more than one input
ance state. simultaneously their pins will be effectively short-
ed.
Table 12. I/O Port Option Selection
DDR OR DR Mode Optio n
0 0 0 Input With pull-up, no interrupt
0 0 1 Input No pull-up, no interrupt
0 1 0 Input With pull-up and with interrupt
0 1 1 Input Analog input (when available)
1 0 X Output Open-drain output (20mA sink when available)
1 1 X Output Push-pull output (20mA sink when available)

Note: X = Don’t care

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 ST62T18C/E18C

I/O PORTS (Cont’d)

4.1.2 Safe I/O State Switching Sequence outputs, it is advisable to keep a copy of the data
Switching the I/O ports from one state to another register in RAM. Single bit instructions may then
should be done in a sequence which ensures that be used on the RAM copy, after which the whole
no unwanted side effects can occur. The recom- copy register can be written to the port data regis-
mended safe transitions are illustrated in Figure ter:
23. All other transitions are potentially risky and SET bit, datacopy
should be avoided when changing the I/O operat- LD a, datacopy
ing mode, as it is most likely that undesirable side- LD DRA, a
effects will be experienced, such as spurious inter-
rupt generation or two pins shorted together by the Warning: Care must also be taken to not use in-
analog multiplexer. structions that act on a whole port register (INC,
Single bit instructions (SET, RES, INC and DEC) DEC, or read operations) when all 8 bits are not
should be used with great caution on Ports Data available on the device. Unavailable bits must be
registers, since these instructions make an implicit masked by software (AND instruction).
read and write back of the entire register. In port
input mode, however, the data register reads from
The WAIT and STOP instructions allow the
the input pins directly, and not from the data regis-
ST62xx to be used in situations where low power
ter latches. Since data register information in input
mode is used to set the characteristics of the input consumption is needed. The lowest power con-
sumption is achieved by configuring I/Os in input
pin (interrupt, pull-up, analog input), these may be
unintentionally reprogrammed depending on the mode with well-defined logic levels.
state of the input pins. As a general rule, it is better The user must take care not to switch outputs with
to limit the use of single bit instructions on data heavy loads during the conversion of one of the
registers to when the whole (8-bit) port is in output analog inputs in order to avoid any disturbance to
mode. In the case of inputs or of mixed inputs and the conversion.

Figure 23. Diagram showing Safe I/O State Transitions

Interrupt Input
pull-up 010* 011 Analog

Input
pull-up (Reset 000 001 Input
state)

Output 100 101

Output
Open Drain Open Drain

Output 110 111

Output
Push-pull Push-pull
Note *. xxx = DDR, OR, DR Bits respectively

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ST62T18C/E18C

I/O PORTS (Cont’d)

Table 13. I/O Port configuration for the ST62T18C/E18C

MODE AVAILABLE ON(1) SCHEMATIC

PA1-PA5
Input
PB4-PB6
(Reset state if PORT
PULL option disabled) Data in
PD4-PD7
Interrupt

Input PA1-PA5
with pull up PB4-PB6
(Reset state if PORT Data in
PULL option enabled) PD4-PD7
Interrupt

PA1-PA5
Input
PB4-PB6
with pull up
Data in
with interrupt
PD4-PD7
Interrupt

PA4-PA5
PB4-PB6
Analog Input
ADC
PD4-PD7

Open drain output PB4-PB6

5mA
PD4-PD7
Data out

Open drain output PA1-PA5

20mA

Push-pull output PB4-PB6

5mA
PD4-PD7
Data out

Push-pull output PA1-PA5

20mA VR01992A

Note 1. Provided the correct configuration has been selected.

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 ST62T18C/E18C

I/O PORTS (Cont’d)

4.1.3 ARTimer alternate functions 4.1.4 UART alternate functions
When bit PWMOE of register ARMC is low, pin AR- PD4/RXD1 pin must be configured as input
TIMout/PA2 is configured as any standard pin of through the DDR and OR registers to be used as
port B through the port registers. When PWMOE is reception line for the UART. All input modes are
high, ARTIMout/PA2 is the PWM output, independ- available and PD4 can be read independently of
ently of the port registers configuration. ARTIMin/ the UART at any time.
PA3 is connected through the port registers as any
standard pin of port B. To use PARTIMin/PA3 as PD5/TXD1 pin must be configured as output
AR Timer input, it must be configured as input through the DDR and OR registers to be used as
though DDRB. transmission line for the UART. Value present on
the pin in output mode is the Data register content
as long as no transmission is active.

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ST62T18C/E18C

I/O PORTS (Cont’d)

Figure 24. Peripheral Interface Configuration of UART and AR Timer

VDD

PID
RXD

PD4/RXD1 DR
UART

IARTOE
PID
0 DR
PD5/TXD1 MUX
1 TXD

PID

ARTIMin
PA3/ARTIMin DR

ARTIMER
PID
OR
PWMOE
PA2/ARTIMout 1 ARTI Mout
MUX
0 DR

VR01661I

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 ST62T18C/E18C

I/O PORTS (Cont’d)

4.1.5 I/O Port Option Registers 4.1.7 I/O Port Data Registers
ORA/B/D (CCh PA, CDh PB, CFh PD) DRA/B/D (C0h PA, C1h PB, C3h PD)
Read/Write Read/Write
7 0 7 0

Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0 Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0

Bit 7-0 = Px7 - Px0: Port A, B, and D Option Reg- Bit 7-0 = Px7 - Px0: Port A, B, and D Data Regis-
ister bits. ters bits.
4.1.6 I/O Port Data Direction Registers
DDRA/B/D (C4h PA, C5h PB, C7h PD)
Read/Write
7 0

Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0

Bit 7-0 = Px7 - Px0: Port A, B, and D Data Direc-

tion Registers bits.

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ST62T18C/E18C

4.2 TIMER
The MCU features an on-chip Timer peripheral, The prescaler input can be the internal frequency
consisting of an 8-bit counter with a 7-bit program- fINT divided by 12 or an external clock applied to
mable prescaler, giving a maximum count of 215. the TIMER pin. The prescaler decrements on the
The peripheral may be configured in three different rising edge. Depending on the division factor pro-
operating modes. grammed by PS2, PS1 and PS0 bits in the TSCR.
Figure 1 shows the Timer Block Diagram. The ex- The clock input of the timer/counter register is mul-
ternal TIMER pin is available to the user. The con- tiplexed to different sources. For division factor 1,
tent of the 8-bit counter can be read/written in the the clock input of the prescaler is also that of timer/
Timer/Counter register, TCR, while the state of the counter; for factor 2, bit 0 of the prescaler register
7-bit prescaler can be read in the PSC register. is connected to the clock input of TCR. This bit
The control logic device is managed in the TSCR changes its state at half the frequency of the pres-
register as described in the following paragraphs. caler input clock. For factor 4, bit 1 of the PSC is
connected to the clock input of TCR, and so forth.
The 8-bit counter is decremented by the output The prescaler initialize bit, PSI, in the TSCR regis-
(rising edge) coming from the 7-bit prescaler and ter must be set to “1” to allow the prescaler (and
can be loaded and read under program control. hence the counter) to start. If it is cleared to “0”, all
When it decrements to zero then the TMZ (Timer the prescaler bits are set to “1” and the counter is
Zero) bit in the TSCR is set to “1”. If the ETI (Ena- inhibited from counting. The prescaler can be
ble Timer Interrupt) bit in the TSCR is also set to loaded with any value between 0 and 7Fh, if bit
“1”, an interrupt request is generated as described PSI is set to “1”. The prescaler tap is selected by
in the Interrupt Chapter. The Timer interrupt can means of the PS2/PS1/PS0 bits in the control reg-
be used to exit the MCU from WAIT mode. ister.
Figure 2 illustrates the Timer’s working principle.
Figure 25. Timer Block Diagram

DATABUS 8

8
8 8
6 b5 b1 b0
b7 b6 b4 b3 b2
5 8-BIT
COUNTER STATUS/CONTROL
4 SELECT
PSC 3 REGISTER
1 OF 7 TMZ ETI TOUT DOUT PSI PS2 PS1 PS0
2
1
0

TIMER
INTERRUPT
LINE

SYNCHRONIZATION LATCH
LOGIC

fOSC :12
VA00009

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 ST62T18C/E18C

TIMER (Cont’d)
4.2.1 Timer Operating Modes The user can select the desired prescaler division
There are three operating modes, which are se- ratio through the PS2, PS1, PS0 bits. When the
lected by the TOUT and DOUT bits (see TSCR TCR count reaches 0, it sets the TMZ bit in the
register). These three modes correspond to the TSCR. The TMZ bit can be tested under program
two clocks which can be connected to the 7-bit control to perform a timer function whenever it
prescaler (fINT ÷ 12 or TIMER pin signal), and to goes high. The low-to-high TMZ bit transition is
the output mode. used to latch the DOUT bit of the TSCR and trans-
fer it to the TIMER pin. This operating mode allows
4.2.1.1 Gated Mode external signal generation on the TIMER pin.
(TOUT = “0”, DOUT = “1”)
Table 14. Timer Operating Modes
In this mode the prescaler is decremented by the
Timer clock input (f INT ÷ 12), but ONLY when the TOUT DOUT Timer Pin Timer Function
signal on the TIMER pin is held high (allowing 0 0 Input Event Counter
pulse width measurement). This mode is selected 0 1 Input Gated Input
by clearing the TOUT bit in the TSCR register to 1 0 Output Output “0”
“0” (i.e. as input) and setting the DOUT bit to “1”.
1 1 Output Output “1”
4.2.1.2 Event Counter Mode
(TOUT = “0”, DOUT = “0”) 4.2.2 Timer Interrupt
In this mode, the TIMER pin is the input clock of When the counter register decrements to zero with
the prescaler which is decremented on the rising the ETI (Enable Timer Interrupt) bit set to one, an
edge. interrupt request is generated as described in the
4.2.1.3 Output Mode Interrupt Chapter. When the counter decrements
(TOUT = “1”, DOUT = data out) to zero, the TMZ bit in the TSCR register is set to
one.
The TIMER pin is connected to the DOUT latch,
hence the Timer prescaler is clocked by the pres-
caler clock input (fINT ÷ 12).
Figure 26. Timer Working Principle

7-BIT PRESCALER

CLOCK BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6

0 1 2 3 4 5 6 7 PS0
8-1 MULTIPLEXER PS1
PS2

BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7

8-BIT COUNTER

VA00186

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ST62T18C/E18C

TIMER (Cont’d)
4.2.3 Application Notes Bit 4 = DOUT: Data Output
TMZ is set when the counter reaches zero; howev- Data sent to the timer output when TMZ is set high
er, it may also be set by writing 00h in the TCR (output mode only). Input mode selection (input
register or by setting bit 7 of the TSCR register. mode only).
The TMZ bit must be cleared by user software Bit 3 = PSI: Prescaler Initialize Bit
when servicing the timer interrupt to avoid unde- Used to initialize the prescaler and inhibit its count-
sired interrupts when leaving the interrupt service ing. When PSI=“0” the prescaler is set to 7Fh and
routine. After reset, the 8-bit counter register is the counter is inhibited. When PSI=“1” the prescal-
loaded with 0FFh, while the 7-bit prescaler is load- er is enabled to count downwards. As long as
ed with 07Fh, and the TSCR register is cleared. PSI=“0” both counter and prescaler are not run-
This means that the Timer is stopped (PSI=“0”) ning.
and the timer interrupt is disabled. Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Se-
If the Timer is programmed in output mode, the lect. These bits select the division ratio of the pres-
DOUT bit is transferred to the TIMER pin when caler register.
TMZ is set to one (by software or due to counter
decrement). When TMZ is high, the latch is trans- Table 15. Prescaler Division Factors
parent and DOUT is copied to the timer pin. When PS2 PS1 PS0 Divided by
TMZ goes low, DOUT is latched. 0 0 0 1
A write to the TCR register will predominate over 0 0 1 2
the 8-bit counter decrement to 00h function, i.e. if a 0 1 0 4
write and a TCR register decrement to 00h occur
simultaneously, the write will take precedence, 0 1 1 8
and the TMZ bit is not set until the 8-bit counter 1 0 0 16
reaches 00h again. The values of the TCR and the 1 0 1 32
PSC registers can be read accurately at any time. 1 1 0 64
4.2.4 Timer Registers 1 1 1 128
Timer Status Control Register (TSCR)
Address: 0D4h — Read/Write
Timer Counter Register TCR
7 0
Address: 0D3h — Read/Write
TMZ ETI TOUT DOUT PSI PS2 PS1 PS0
7 0

D7 D6 D5 D4 D3 D2 D1 D0
Bit 7 = TMZ: Timer Zero bit
A low-to-high transition indicates that the timer
count register has decrement to zero. This bit must Bit 7-0 = D7-D0: Counter Bits.
be cleared by user software before starting a new
count.
Prescaler Register PSC
Bit 6 = ETI: Enable Timer Interrupt
Address: 0D2h — Read/Write
When set, enables the timer interrupt request. If
ETI=0 the timer interrupt is disabled. If ETI=1 and 7 0
TMZ=1 an interrupt request is generated.
Bit 5 = TOUT: Timers Output Control D7 D6 D5 D4 D3 D2 D1 D0

When low, this bit selects the input mode for the
TIMER pin. When high the output mode is select- Bit 7 = D7: Always read as “0”.
ed.
Bit 6-0 = D6-D0: Prescaler Bits.

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 ST62T18C/E18C

4.3 AUTO-RELOAD TIMER

The Auto-Reload Timer (AR Timer) on-chip pe- the prescaler and counter contents are frozen.
ripheral consists of an 8-bit timer/counter with When TEN is set, the AR counter runs at the rate
compare and capture/reload capabilities and of a of the selected clock source. The counter is
7-bit prescaler with a clock multiplexer, enabling cleared on system reset.
the clock input to be selected as f INT, fINT/3 or an The AR counter may also be initialized by writing
external clock source. A Mode Control Register, to the ARLR load register, which also causes an
ARMC, two Status Control Registers, ARSC0 and immediate copy of the value to be placed in the AR
ARSC1, an output pin, ARTIMout, and an input counter, regardless of whether the counter is run-
pin, ARTIMin, allow the Auto-Reload Timer to be ning or not. Initialization of the counter, by either
used in 4 modes: method, will also clear the ARPSC register, where-
– Auto-reload (PWM generation), upon counting will start from a known value.
– Output compare and reload on external event 4.3.2 Timer Operating Modes
(PLL), Four different operating modes are available for
– Input capture and output compare for time meas- the AR Timer:
urement. Auto-reload Mode with PWM Generation. This
– Input capture and output compare for period mode allows a Pulse Width Modulated signal to be
measurement. generated on the ARTIMout pin with minimum
The AR Timer can be used to wake the MCU from Core processing overhead.
WAIT mode either with an internal or with an exter- The free running 8-bit counter is fed by the pres-
nal clock. It also can be used to wake the MCU caler’s output, and is incremented on every rising
from STOP mode, if used with an external clock edge of the clock signal.
signal connected to the ARTIMin pin. A Load reg- When a counter overflow occurs, the counter is
ister allows the program to read and write the automatically reloaded with the contents of the Re-
counter on the fly. load/Capture Register, ARCC, and ARTIMout is
4.3.1 AR Timer Description set. When the counter reaches the value con-
The AR COUNTER is an 8-bit up-counter incre- tained in the compare register (ARCP), ARTIMout
mented on the input clock’s rising edge. The coun- is reset.
ter is loaded from the ReLoad/Capture Register, On overflow, the OVF flag of the ARSC0 register is
ARRC, for auto-reload or capture operations, as set and an overflow interrupt request is generated
well as for initialization. Direct access to the AR if the overflow interrupt enable bit, OVIE, in the
counter is not possible; however, by reading or Mode Control Register (ARMC), is set. The OVF
writing the ARLR load register, it is possible to flag must be reset by the user software.
read or write the counter’s contents on the fly. When the counter reaches the compare value, the
The AR Timer’s input clock can be either the inter- CPF flag of the ARSC0 register is set and a com-
nal clock (from the Oscillator Divider), the internal pare interrupt request is generated, if the Compare
clock divided by 3, or the clock signal connected to Interrupt enable bit, CPIE, in the Mode Control
the ARTIMin pin. Selection between these clock Register (ARMC), is set. The interrupt service rou-
sources is effected by suitably programming bits tine may then adjust the PWM period by loading a
CC0-CC1 of the ARSC1 register. The output of the new value into ARCP. The CPF flag must be reset
AR Multiplexer feeds the 7-bit programmable AR by user software.
Prescaler, ARPSC, which selects one of the 8 The PWM signal is generated on the ARTIMout
available taps of the prescaler, as defined by pin (refer to the Block Diagram). The frequency of
PSC0-PSC2 in the AR Mode Control Register. this signal is controlled by the prescaler setting
Thus the division factor of the prescaler can be set and by the auto-reload value present in the Re-
to 2n (where n = 0, 1,..7). load/Capture register, ARRC. The duty cycle of
The clock input to the AR counter is enabled by the the PWM signal is controlled by the Compare Reg-
TEN (Timer Enable) bit in the ARMC register. ister, ARCP.
When TEN is reset, the AR counter is stopped and

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ST62T18C/E18C

AUTO-RELOAD TIMER (Cont’d)

Figure 27. AR Timer Block Diagram
DATA BUS
DDRA2

DRA2

AR COMPARE
REGISTER

8
PA2/
ARTIMout
CPF
COMPARE R

S
8
PWMOE

f INT OVF OVF

M
7-Bit 8-Bit OVIE
f INT /3 U
AR PRESCALER AR COUNTER LOAD
X TCLD

CC0-CC1 PS0-PS2 EIE

EF
AR TIMER
8
INTERRUPT
CPF
CPIE

8 8

PA3/
ARTIMin
SL0-SL1
AR AR
EF
SYNCHRO RELOAD/CAPTURE LOAD
REGISTER REGISTER

8 8

DATA BUS

VR01660B

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 ST62T18C/E18C

AUTO-RELOAD TIMER (Cont’d)

It should be noted that the reload values will also The ARTC counter is initialized by writing to the
affect the value and the resolution of the duty cycle ARRC register and by then setting the TCLD (Tim-
of PWM output signal. To obtain a signal on ARTI- er Load) and the TEN (Timer Clock Enable) bits in
Mout, the contents of the ARCP register must be the Mode Control register, ARMC.
greater than the contents of the ARRC register. Enabling and selection of the clock source is con-
The maximum available resolution for the ARTI- trolled by the CC0, CC1, SL0 and SL1 bits in the
Mout duty cycle is: Status Control Register, ARSC1. The prescaler di-
Resolution = 1/[255-(ARRC)] vision ratio is selected by the PS0, PS1 and PS2
bits in the ARSC1 register.
Where ARRC is the content of the Reload/Capture
register. The compare value loaded in the Com- In Auto-reload Mode, any of the three available
pare Register, ARCP, must be in the range from clock sources can be selected: Internal Clock, In-
(ARRC) to 255. ternal Clock divided by 3 or the clock signal
present on the ARTIMin pin.
Figure 28. Auto-reload Timer PWM Function
COUNTER

255
COMPARE
VALUE

RELOAD
REGISTER
000
t

PWM OUTPUT

t
VR001852

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ST62T18C/E18C

AUTO-RELOAD TIMER (Cont’d)

Capture Mode with PWM Generation. In this the count is incremented on every clock rising
mode, the AR counter operates as a free running edge.
8-bit counter fed by the prescaler output. The Each counter overflow sets the ARTIMout pin. A
counter is incremented on every clock rising edge. match between the counter and ARCP (Compare
An 8-bit capture operation from the counter to the Register) resets the ARTIMout pin and sets the
ARRC register is performed on every active edge compare flag, CPF. A compare interrupt request is
on the ARTIMin pin, when enabled by Edge Con- generated if the related compare interrupt enable
trol bits SL0, SL1 in the ARSC1 register. At the bit, CPIE, is set. A PWM signal is generated on
same time, the External Flag, EF, in the ARSC0 ARTIMout. The CPF flag must be reset by user
register is set and an external interrupt request is software.
generated if the External Interrupt Enable bit, EIE, Initialization of the counter is as described in the
in the ARMC register, is set. The EF flag must be previous paragraph. In addition, if the external AR-
reset by user software. TIMin input is enabled, an active edge on the input
Each ARTC overflow sets ARTIMout, while a pin will copy the contents of the ARRC register into
match between the counter and ARCP (Compare the counter, whether the counter is running or not.
Register) resets ARTIMout and sets the compare Notes:
flag, CPF. A compare interrupt request is generat-
ed if the related compare interrupt enable bit, The allowed AR Timer clock sources are the fol-
CPIE, is set. A PWM signal is generated on ARTI- lowing:
Mout. The CPF flag must be reset by user soft- AR Timer Mode Clock Sources
ware.
Auto-reload mode fINT, fINT/3, ARTIMin
The frequency of the generated signal is deter- Capture mode fINT, fINT/3
mined by the prescaler setting. The duty cycle is
Capture/Reset mode fINT, fINT/3
determined by the ARCP register.
External Load mode fINT, fINT/3
Initialization and reading of the counter are identi-
cal to the auto-reload mode (see previous descrip- The clock frequency should not be modified while
tion). the counter is counting, since the counter may be
Enabling and selection of clock sources is control- set to an unpredictable value. For instance, the
led by the CC0 and CC1 bits in the AR Status Con- multiplexer setting should not be modified while
trol Register, ARSC1. the counter is counting.
The prescaler division ratio is selected by pro- Loading of the counter by any means (by auto-re-
gramming the PS0, PS1 and PS2 bits in the load, through ARLR, ARRC or by the Core) resets
ARSC1 Register. the prescaler at the same time.
In Capture mode, the allowed clock sources are Care should be taken when both the Capture inter-
the internal clock and the internal clock divided by rupt and the Overflow interrupt are used. Capture
3; the external ARTIMin input pin should not be and overflow are asynchronous. If the capture oc-
used as a clock source. curs when the Overflow Interrupt Flag, OVF, is
high (between counter overflow and the flag being
Capture Mode with Reset of counter and pres-
caler, and PWM Generation. This mode is identi- reset by software, in the interrupt routine), the Ex-
cal to the previous one, with the difference that a ternal Interrupt Flag, EF, may be cleared simul-
capture condition also resets the counter and the taneusly without the interrupt being taken into ac-
count.
prescaler, thus allowing easy measurement of the
time between two captures (for input period meas- The solution consists in resetting the OVF flag by
urement on the ARTIMin pin). writing 06h in the ARSC0 register. The value of EF
is not affected by this operation. If an interrupt has
Load on External Input. The counter operates as
a free running 8-bit counter fed by the prescaler. occured, it will be processed when the MCU exits
from the interrupt routine (the second interrupt is
latched).

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 ST62T18C/E18C

AUTO-RELOAD TIMER (Cont’d)

4.3.3 AR Timer Registers ARSC0 register is also set, an interrupt request is
AR Mode Control Register (ARMC) generated.
Address: E5h — Read/Write Bit 1-0 = ARMC1-ARMC0: Mode Control Bits 1-0.
These are the operating mode control bits. The fol-
Reset status: 00h lowing bit combinations will select the various op-
erating modes:
7 0
ARMC1 ARMC0 Operating Mode
TCLD TEN PWMOE EIE CPIE OVIE ARMC1 ARMC0
0 0 Auto-reload Mode
0 1 Capture Mode
The AR Mode Control Register ARMC is used to Capture Mode with Reset
program the different operating modes of the AR 1 0
of ARTC and ARPSC
Timer, to enable the clock and to initialize the Load on External Edge
counter. It can be read and written to by the Core 1 1
Mode
and it is cleared on system reset (the AR Timer is
disabled).
AR Timer Status/Control Registers ARSC0 &
Bit 7 = TLCD: Timer Load Bit. This bit, when set, ARSC1. These registers contain the AR Timer sta-
will cause the contents of ARRC register to be tus information bits and also allow the program-
loaded into the counter and the contents of the ming of clock sources, active edge and prescaler
prescaler register, ARPSC, are cleared in order to multiplexer setting.
initialize the timer before starting to count. This bit ARSC0 register bits 0,1 and 2 contain the interrupt
is write-only and any attempt to read it will yield a
flags of the AR Timer. These bits are read normal-
logical zero.
ly. Each one may be reset by software. Writing a
Bit 6 = TEN: Timer Clock Enable. This bit, when one does not affect the bit value.
set, allows the timer to count. When cleared, it will
AR Status Control Register 0 (ARSC0)
stop the timer and freeze ARPSC and ARTSC.
Address: E6h — Read/Clear
Bit 5 = PWMOE: PWM Output Enable. This bit,
when set, enables the PWM output on the ARTI- 7 0
Mout pin. When reset, the PWM output is disabled.
Bit 4 = EIE: External Interrupt Enable. This bit, D7 D6 D5 D4 D3 EF CPF OVF
when set, enables the external interrupt request.
When reset, the external interrupt request is Bits 7-3 = D7-D3: Unused
masked. If EIE is set and the related flag, EF, in
Bit 2 = EF: External Interrupt Flag. This bit is set by
the ARSC0 register is also set, an interrupt re-
quest is generated. any active edge on the external ARTIMin input pin.
The flag is cleared by writing a zero to the EF bit.
Bit 3 = CPIE: Compare Interrupt Enable. This bit,
when set, enables the compare interrupt request. Bit 1 = CPF: Compare Interrupt Flag. This bit is set
if the contents of the counter and the ARCP regis-
If CPIE is reset, the compare interrupt request is
ter are equal. The flag is cleared by writing a zero
masked. If CPIE is set and the related flag, CPF, in
to the CPF bit.
the ARSC0 register is also set, an interrupt re-
quest is generated. Bit 0 = OVF: Overflow Interrupt Flag. This bit is set
by a transition of the counter from FFh to 00h
Bit 2 = OVIE: Overflow Interrupt. This bit, when
set, enables the overflow interrupt request. If OVIE (overflow). The flag is cleared by writing a zero to
the OVF bit.
is reset, the compare interrupt request is masked.
If OVIE is set and the related flag, OVF in the

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ST62T18C/E18C

AUTO-RELOAD TIMER (Cont’d)

AR Status Control Register 1(ARSC1) AR Load Register ARLR. The ARLR load register
Address: E7h — Read/Write is used to read or write the ARTC counter register
“on the fly” (while it is counting). The ARLR regis-
7 0 ter is not affected by system reset.
AR Load Register (ARLR)
PS2 PS1 PS0 D4 SL1 SL0 CC1 CC0
Address: EBh — Read/Write
Bist 7-5 = PS2-PS0: Prescaler Division Selection 7 0
Bits 2-0. These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by D7 D6 D5 D4 D3 D2 D1 D0
these bits. The prescaler division ratio is listed in the
following table: Bit 7-0 = D7-D0: Load Register Data Bits. These
are the load register data bits.
Table 16. Prescaler Division Ratio Selection
PS2 PS1 PS0 ARPSC Division Ratio
AR Reload/Capture Register. The ARRC reload/
0 0 0 1 capture register is used to hold the auto-reload
0 0 1 2 value which is automatically loaded into the coun-
0 1 0 4 ter when overflow occurs.
0 1 1 8 AR Reload/Capture (ARRC)
1 0 0 16 Address: E9h — Read/Write
1 0 1 32
7 0
1 1 0 64
1 1 1 128 D7 D6 D5 D4 D3 D2 D1 D0

Bit 4 = D4: Reserved. Must be kept reset.

Bit 3-2 = SL1-SL0: Timer Input Edge Control Bits 1- Bit 7-0 = D7-D0: Reload/Capture Data Bits. These
0. These bits control the edge function of the Timer are the Reload/Capture register data bits.
input pinfor external synchronization. If bit SL0 is re-
set, edge detection is disabled; if set edge detection AR Compare Register. The CP compare register
is enabled. If bit SL1 is reset, the AR Timer input pin is used to hold the compare value for the compare
is rising edge sensitive; if set, it is falling edge sen- function.
sitive.
AR Compare Register (ARCP)
SL1 SL0 Edge Detection
Address: EAh — Read/Write
X 0 Disabled
0 1 Rising Edge 7 0
1 1 Falling Edge
D7 D6 D5 D4 D3 D2 D1 D0

Bit 1-0 = CC1-CC0: Clock Source Select Bit 1-0.

These bits select the clock source for the AR Timer Bit 7-0 = D7-D0: Compare Data Bits. These are
through the AR Multiplexer. The programming of the Compare register data bits.
the clocksources is explained in the following Table
17:
Table 17. Clock Source Selection.
CC1 CC0 Clock Source
0 0 Fint
0 1 Fint Divided by 3
1 0 ARTIMin Input Clock
1 1 Reserved

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 ST62T18C/E18C

4.4 A/D CONVERTER (ADC)

The A/D converter peripheral is an 8-bit analog to one instruction before the beginning of the conver-
digital converter with analog inputs as alternate I/O sion to allow stabilisation of the A/D converter.
functions (the number of which is device depend- This action is also needed before entering WAIT
ent), offering 8-bit resolution with a typical conver- mode, since the A/D comparator is not automati-
sion time of 70us (at an oscillator clock frequency cally disabled in WAIT mode.
of 8MHz). During Reset, any conversion in progress is
The ADC converts the input voltage by a process stopped, the control register is reset to 40h and the
of successive approximations, using a clock fre- ADC interrupt is masked (EAI=0).
quency derived from the oscillator with a division
factor of 12 or 6. After Reset, division by 12 is used Figure 29. ADC Block Diagram
by default to insure compatibility with other mem-
bers of the ST62 MCU family. With an oscillator
clock frequency less than 1.2MHz, conversion ac-
INTERRUPT
curacy is decreased. CLOCK
Selection of the input pin is done by configuring Ain CONVERTER RESET
the related I/O line as an analog input via the Op- AVSS
tion and Data registers (refer to I/O ports descrip- AVDD
tion for additional information). Only one I/O line
must be configured as an analog input at any time.
The user must avoid any situation in which more
CONTROL REGISTER RESULT REGISTER
than one I/O pin is selected as an analog input si-
multaneously, to avoid device malfunction.
8 8
The ADC uses two registers in the data space: the
ADC data conversion register, ADR, which stores CORE CORE
the conversion result, and the ADC control regis- CONTROL SIGNALS VA00418
ter, ADCR, used to program the ADC functions.
A conversion is started by writing a “1” to the Start
bit (STA) in the ADC control register. This auto- 4.4.1 Application Notes
matically clears (resets to “0”) the End Of Conver-
sion Bit (EOC). When a conversion is complete, The A/D converter does not feature a sample and
the EOC bit is automatically set to “1”, in order to hold circuit. The analog voltage to be measured
flag that conversion is complete and that the data should therefore be stable during the entire con-
in the ADC data conversion register is valid. Each version cycle. Voltage variation should not exceed
conversion has to be separately initiated by writing ±1/2 LSB for the optimum conversion accuracy. A
to the STA bit. low pass filter may be used at the analog input
pins to reduce input voltage variation during con-
The STA bit is continuously scanned so that, if the version.
user sets it to “1” while a previous conversion is in
progress, a new conversion is started before com- When selected as an analog channel, the input pin
pleting the previous one. The start bit (STA) is a is internally connected to a capacitor Cad of typi-
write only bit, any attempt to read it will show a log- cally 12pF. For maximum accuracy, this capacitor
ical “0”. must be fully charged at the beginning of conver-
sion. In the worst case, conversion starts one in-
The A/D converter features a maskable interrupt struction (6.5 µs) after the channel has been se-
associated with the end of conversion. This inter- lected. In worst case conditions, the impedance,
rupt is associated with interrupt vector #4 and oc- ASI, of the analog voltage source is calculated us-
curs when the EOC bit is set (i.e. when a conver- ing the following formula:
sion is completed). The interrupt is masked using
the EAI (interrupt mask) bit in the control register. 6.5µs = 9 x Cad x ASI
The power consumption of the device can be re- (capacitor charged to over 99.9%), i.e. 30 kΩ in-
duced by turning off the ADC peripheral. This is cluding a 50% guardband. ASI can be higher if Cad
done by setting the PDS bit in the ADC control reg- has been charged for a longer period by adding in-
ister to “0”. If PDS=“1”, the A/D is powered and en- structions before the start of conversion (adding
abled for conversion. This bit must be set at least more than 26 CPU cycles is pointless).

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ST62T18C/E18C

A/D CONVERTER (Cont’d)

Since the ADC is on the same chip as the micro- achieved by setting ADC SYNC option. This way,
processor, the user should not switch heavily load- ADC conversion starts in effective WAIT for maxi-
ed output signals during conversion, if high preci- mum accuracy.
sion is required. Such switching will affect the sup- Note: With this extra option, it is mandatory to ex-
ply voltages used as analog references. ecute WAIT instruction just after ADC start instruc-
The accuracy of the conversion depends on the tion. Insertion of any extra instruction may cause
quality of the power supplies (V DD and VSS). The spurious interrupt request at ADC interrupt vector.
user must take special care to ensure a well regu- A/D Converter Control Register (ADCR)
lated reference voltage is present on the VDD and
VSS pins (power supply voltage variations must be Address: 0D1h — Read/Write
less than 5V/ms). This implies, in particular, that a 7 0
suitable decoupling capacitor is used at the VDD
pin. OSC
EAI EOC STA PDS CLSEL D1 D0
OFF
The converter resolution is given by:
Bit 7 = EAI: Enable A/D Interrupt. If this bit is set to
V DD – V SS “1” the A/D interrupt is enabled, when EAI=0 the
----------------------
------ interrupt is disabled.
256
The Input voltage (Ain) which is to be converted Bit 6 = EOC: End of conversion. Read Only. This
must be constant for 1µs before conversion and read only bit indicates when a conversion has
remain constant during conversion. been completed. This bit is automatically reset to
“0” when the STA bit is written. If the user is using
Conversion resolution can be improved if the pow- the interrupt option then this bit can be used as an
er supply voltage (VDD ) to the microcontroller is interrupt pending bit. Data in the data conversion
lowered. register are valid only when this bit is set to “1”.
In order to optimise conversion resolution, the user Bit 5 = STA: Start of Conversion. Write Only. Writ-
can configure the microcontroller in WAIT mode, ing a “1” to this bit will start a conversion on the se-
because this mode minimises noise disturbances lected channel and automatically reset to “0” the
and power supply variations due to output switch- EOC bit. If the bit is set again when a conversion is
ing. Nevertheless, the WAIT instruction should be in progress, the present conversion is stopped and
executed as soon as possible after the beginning a new one will take place. This bit is write only, any
of the conversion, because execution of the WAIT attempt to read it will show a logical zero.
instruction may cause a small variation of the VDD
voltage. The negative effect of this variation is min- Bit 4 = PDS: Power Down Selection. This bit acti-
imized at the beginning of the conversion when the vates the A/D converter if set to “1”. Writing a “0” to
converter is less sensitive, rather than at the end this bit will put the ADC in power down mode (idle
of conversion, when the less significant bits are mode).
determined. Bit 3= CLSEL: Clock Selection. When set, the
The best configuration, from an accuracy stand- ADC is driven by the MCU internal clock divided by
point, is WAIT mode with the Timer stopped. In- 6, and typical conversion time at 8MHz is 35µs.
deed, only the ADC peripheral and the oscillator When cleared (Reset state), MCU clock divided by
are then still working. The MCU must be woken up 12 is used with a typical 70µs conversion time at
from WAIT mode by the ADC interrupt at the end 8MHz.
of the conversion. It should be noted that waking Bit 2 = OSCOFF. When low, this bit enables main
up the microcontroller could also be done using oscillator to run. The main oscillator is switched off
the Timer interrupt, but in this case the Timer will when OSCOFF is high.
be working and the resulting noise could affect Bit 1-0: Reserved. Must be kept cleared.
conversion accuracy.
A/D Converter Data Register (ADR)
One extra feature is available in the ADC to get a
better accuracy. In fact, each ADC conversion has Address: 0D0h — Read only
to be followed by a WAIT instruction to minimize 7 0
the noise during the conversion. But the first con-
version step is performed before the execution of D7 D6 D5 D4 D3 D2 D1 D0
the WAIT when most of clocks signals are still en-
abled . The key is to synchronize the ADC start Bit 7-0 = D7-D0: 8 Bit A/D Conversion Result.
with the effective execution of the WAIT. This is

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 ST62T18C/E18C

4.5 U. A. R. T. (Universal Asynchronous Receiver/Transmitter)

The UART provides the basic hardware for asyn- 4.5.1 Ports Interfacing
chronous serial communication which, combined RXD reception line and TXD emission line are
with an appropriate software routine, gives a serial sharing the same external pins as two I/O lines.
interface providing communication with common Therefore, UART configuration requires to set
baud rates (up to 76,800 Baud with an 8MHz ex- these two I/O lines through the relevant ports reg-
ternal oscillator) and flexible character formats. isters. The I/O line common with RXD line must be
Operating in Half-Duplex mode only, the UART defined as input mode (with or without pull-up)
uses a 10-bit frame or a 11-bit frame according to while the I/O line common with TXD line must be
the choosen MCU option. Automatic parity bit gen- defined as output mode (Push-pull or open drain).
eration is software selectable in the 10-bit charac- In the 11-bit character format option, the transmit-
ter format allowing either 7 data bit + 1 parity bit, or ted data is inverted and can therefore use a single
8 data bit transmission. Transmitted data is sent di- transistor buffering stage. Defined as input, the
rectly, while received data is buffered allowing fur- RXD line can be read at any time as an I/O line
ther data characters to be received while the data during the UART operation. The TXD pin follows I/
is being read out of the receive buffer register. Data O port registers value when UARTOE bit is
transmit has priority over data being received. cleared, which means when no serial transmission
The UART is supplied with an MCU internal clock is in progress. As a consequence, a permanent
that isalso available in WAIT mode of the processor. high level has to be written onto the I/O port in or-
der to achieve a proper stop condition on the TXD
line when no transmission is active.
Figure 30. UART Block Diagram

START RXD1
DETECTOR

UARTOE

TXD
DIN DATA SHIFT DOUT 1

REGISTER MUX TXD1

DR
D8 D7 D6 D5 D4 D3 D2 D1 D0 0
WRIT E
CONTROL LOGIC

READ
TO CORE

RECEIV E BUFFER
REGISTER

D8
CONTROL REGIST ER
BAUD RATE
RX and TX
INTE RRUPTS

fOSC PROGRAMMABLE
DIVIDE R
BAUD RATE x 8
VR02009

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ST62T18C/E18C

U. A. R. T (Cont’d)
4.5.2 Clock Generation LSB D0 at first.. The output is then set to 1 for a
The UART contains a built-in divider of the MCU period of one bit time to generate a Stop bit, and
internal clock for most common Baud Rates as then the UARTOE signal returns the TXD1 line to
shown in Table 19. Other baud rate values can be its alternate I/O function. The end of transmission
calculated from the chosen oscillator frequency di- is flagged by setting TXMT to 1 and an interrupt is
vided by the Divisor value shown. generated if enabled. The TXMT flag is reset by
writing a 0 to the bit position, it is also cleared au-
The divided clock provides a frequency that is 8 tomatically when a new character is written to the
times the desired baud rate. This allows the Data Data Register. TXMT can be set to 1 by software
reception mechanism to provide a 2 to 1 majority to generate a software interrupt so care must be
voting system to determine the logic state of the taken in manipulating the Control Register.
asynchronous incoming serial logic bit by taking 3
timed samples within the 8 time states. 4.5.3.1 Character Format
The bits not sampled provide a buffer to compen- Once the MCU option is set as 10-bit or 11-bit
sate for frequency offsets between sender and re- frame, the frame length is fixed. Within these 8 or 9
ceiver. remaining bit, any format can be used as shown in
the Table 18. Only the even parity automatic com-
4.5.3 Data Transmission putation in the 10-bit frame is available. Any other
Whatever the format selected as MCU option, 10- parity bit can however be software computed and
bit or 11-bit frame, the start and stop bit are auto- processed as a data bit
matically generated by the UART. Only the re-
maining 8 (Resp. 9) bit in the 10-bit (Resp. 11-bit) Table 18. Character Options
frame are under control of the user. 10 bit frame
Transmission is started by writing the Data Regis- Start Bit 8 Data No Parity 1 Stop
ter, after having previously set the transmission Start Bit 7 Data 1 Even Parity (Auto) 1 Stop
software options, the baudrate and the parity ena-
Start Bit 7 Data 1 Software Parity 1 Stop
ble. In case of 11-bit frame, the 9th bit must then
11 bit frame
be set before into the LSB of the UART Control
Register. Bit 9 remains in the state programmed Start Bit 8 Data 1 Software Parity 1 Stop
for consecutive transmissions until changed by the Start Bit 9 Data No Parity 1 Stop
user or until a character is received when the state Start Bit 8 Data No Parity 2 Stop
of this bit is changed to that of the incoming bit 9. Start Bit 7 Data 1 Software Parity 2 Stop
The UARTOE signal switches the output multi-
plexer to the UART output and a start bit is sent (a
0 for one bit time) followed by the data bit with the
Figure 31. 11-bit Character Format Example Figure 32. UART Data Output
UARTOE
START STOP
BIT BIT
TXD
1
D0 D1 D7 D8
MUX TXD1
BIT 2 8 9 PORT DATA
1 10 0
POSSIBLE OUTPU T
POSITION
NEXT
VR02011
CHARACTER
START OF DATA START
VR02012

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 ST62T18C/E18C

U. A. R. T (Cont’d)
4.5.4 Data Reception If a transmission is started during the course of a
The UART continuously looks for a falling edge on reception, the transmission takes priority and the
the input pin whenever a transmission is not ac- reception is stopped to free the resources for the
tive. Once an edge is detected it waits 1 bit time (8 transmission. This implies that a handshaking sys-
states) to accommodate the Start bit, and then as- tem must be implemented, as polling of the UART
sembles the following serial data stream into the to detect reception is not available.
data register. First 8 bit are stored into the UART 4.5.5 Interrupt Capabilities
Data Register, while the additionnal 9th bit is Both reception and transmission processes can in-
stored into the LSB of the UART Control Register duce interrupt to the core as defined in the inter-
in case of the 11-bit frame MCU option has been rupt section. These interrupts are enabled by set-
selected. When the 10-bit frame option is selected, ting TXIEN and RXIEN bit in the UARTCR register,
the parity of the 8 received bit is automatically writ- and TXMT and RXRDY flags are set accordingly
ten into the LSB of the UART Control Register to the interrupt source.
(PTYEN bit).
4.5.6 Registers
After all bit have been received, the Receiver waits
for the duration of one bit (for the Stop bit) and UART Data Register (UARTDR)
then transfers the received data into the buffer reg- Address: D6h, Read/Write
ister, allowing a following character to be received. 7 0
The interrupt flag RXRDY is set to 1 as the data is
transferred to the buffer register and, if enabled, D7 D6 D5 D4 D3 D2 D1 D0
will generate an interrupt.
Figure 33. Data Sampling Points Bit7-Bit0. UART data bits. A write to this register
loads the data into the transmit shift register and
triggers the start of transmission. In addition this
1 BIT resets the transmit interrupt flag TXMT. A read of
this register returns the data from the Receive
buffer. If the automatic even parity computation is
set (Bit PTYEN set), D7 must be cleared to 0 be-
fore transmission. Only the 7 LSB D0..D6 contain
the data to be sent.
Warning. No Read/Write Instructions may be
0 1 2 3 4 5 6 7 8 used with this register as both transmit and receive
SAMPLES share the same address
VR02010

Table 19. Baudrate Selection

Baud Rate
BR2 BR1 BR0 fINT Division
f INT = 8MHz f INT = 4MHz
0 0 0 6.656 1200 600
0 0 1 3.328 2400 1200
0 1 0 1.664 4800 2400
0 1 1 832 9600 4800
1 0 0 416 19200 9600
1 0 1 256 31200 15600
1 1 0 208 38400 19200
1 1 1 104 76800 38400

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ST62T18C/E18C

U. A. R. T (Cont’d)
UART Control Register (UARTCR) Bit 4 = TXIEN. Transmit Interrupt Enable. When
Address: D7h, Read/Write this bit is set to 1, the transmit interrupt is enabled.
Writing to TXIEN does not affect the status of the
7 0 interrupt flag TXRDY.
RXRDY TXMT RXIEN TXIE N BR2 BR1 BR0 PTYEN Bit 3-1= BR2..BR0. Baudrate select. These bits
select the operating baud rate of the UART, de-
Bit 7 = RXRDY. Receiver Ready. This flag be- pending on the frequency of fOSC. Care should be
comes active as soon as a complete byte has taken not to change these bits during communica-
been received and copied into the receive buffer. It tion as writing to these bits has an immediate ef-
may be cleared by writing a zero to it. Writing a fect.
one is possible. If the interrupt enable bit RXIEN is Bit 0 = PTYEN. Parity/Data Bit 8. The function of
set to one, a software interrupt will be generated. this bit depens on the MCU option set. In 11-bit
Bit 6 = TXMT. Transmitter Empty. This flag be- frame mode, it is the 9th bit of the trasmitted/re-
comes active as soon as a complete byte has ceived character. In 10-bit frame mode, writing a 1
been sent. It may be cleared by writing a zero to it. enables the automatic even parity computation,
It is automatically cleared by the action of writing a while a read instruction after reception gives the
data value into the UART data register. parity of the whole 8 bit word received. For the
even parity, a 0 value means no parity error.
Bit 5 = RXIEN. Receive Interrupt Enable . When
this bit is set to 1, the receive interrupt is enabled. Note: As the PTYEN bit is modified in reception, it
Writing to RXIEN does not affect the status of the must be to set to 1 before transmission if a recep-
interrupt flag RXRDY. tion occured in between.

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 ST62T18C/E18C

5 SOFTWARE

5.1 ST6 ARCHITECTURE

The ST6 software has been designed to fully use bits of the opcode with the byte following the op-
the hardware in the most efficient way possible code. The instructions (JP, CALL) which use the
while keeping byte usage to a minimum; in short, extended addressing mode are able to branch to
to provide byte efficient programming capability. any address of the 4K bytes Program space.
The ST6 core has the ability to set or clear any
register or RAM location bit of the Data space with An extended addressing mode instruction is two-
a single instruction. Furthermore, the program byte long.
may branch to a selected address depending on
Program Counter Relative. The relative address-
the status of any bit of the Data space. The carry
bit is stored with the value of the bit when the SET ing mode is only used in conditional branch in-
structions. The instruction is used to perform a test
or RES instruction is processed.
and, if the condition is true, a branch with a span of
-15 to +16 locations around the address of the rel-
5.2 ADDRESSING MODES ative instruction. If the condition is not true, the in-
struction which follows the relative instruction is
The ST6 core offers nine addressing modes, executed. The relative addressing mode instruc-
which are described in the following paragraphs. tion is one-byte long. The opcode is obtained in
Three different address spaces are available: Pro- adding the three most significant bits which char-
gram space, Data space, and Stack space. Pro- acterize the kind of the test, one bit which deter-
gram space contains the instructions which are to mines whether the branch is a forward (when it is
be executed, plus the data for immediate mode in- 0) or backward (when it is 1) branch and the four
structions. Data space contains the Accumulator, less significant bits which give the span of the
the X,Y,V and W registers, peripheral and Input/ branch (0h to Fh) which must be added or sub-
Output registers, the RAM locations and Data tracted to the address of the relative instruction to
ROM locations (for storage of tables and con- obtain the address of the branch.
stants). Stack space contains six 12-bit RAM cells
used to stack the return addresses for subroutines Bit Direct. In the bit direct addressing mode, the
and interrupts. bit to be set or cleared is part of the opcode, and
the byte following the opcode points to the ad-
Immediate. In the immediate addressing mode, dress of the byte in which the specified bit must be
the operand of the instruction follows the opcode set or cleared. Thus, any bit in the 256 locations of
location. As the operand is a ROM byte, the imme- Data space memory can be set or cleared.
diate addressing mode is used to access con-
stants which do not change during program execu- Bit Test & Branch. The bit test and branch ad-
tion (e.g., a constant used to initialize a loop coun- dressing mode is a combination of direct address-
ter). ing and relative addressing. The bit test and
branch instruction is three-byte long. The bit iden-
Direct. In the direct addressing mode, the address tification and the tested condition are included in
of the byte which is processed by the instruction is the opcode byte. The address of the byte to be
stored in the location which follows the opcode. Di- tested follows immediately the opcode in the Pro-
rect addressing allows the user to directly address gram space. The third byte is the jump displace-
the 256 bytes in Data Space memory with a single ment, which is in the range of -127 to +128. This
two-byte instruction. displacement can be determined using a label,
which is converted by the assembler.
Short Direct. The core can address the four RAM
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in Indirect. In the indirect addressing mode, the byte
the short-direct addressing mode. In this case, the processed by the register-indirect instruction is at
instruction is only one byte and the selection of the the address pointed by the content of one of the in-
location to be processed is contained in the op- direct registers, X or Y (80h,81h). The indirect reg-
code. Short direct addressing is a subset of the di- ister is selected by the bit 4 of the opcode. A regis-
rect addressing mode. (Note that 80h and 81h are ter indirect instruction is one byte long.
also indirect registers).
Inherent. In the inherent addressing mode, all the
Extended. In the extended addressing mode, the information necessary to execute the instruction is
12-bit address needed to define the instruction is contained in the opcode. These instructions are
obtained by concatenating the four less significant one byte long.

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5.3 INSTRUCTION SET

The ST6 core offers a set of 40 basic instructions Load & Store. These instructions use one, two or
which, when combined with nine addressing three bytes in relation with the addressing mode.
modes, yield 244 usable opcodes. They can be di- One operand is the Accumulator for LOAD and the
vided into six different types: load/store, arithme- other operand is obtained from data memory using
tic/logic, conditional branch, control instructions, one of the addressing modes.
jump/call, and bit manipulation. The following par-
agraphs describe the different types. For Load Immediate one operand can be any of
the 256 data space bytes while the other is always
All the instructions belonging to a given type are immediate data.
presented in individual tables.
Table 20. Load & Store Instructions
Flags
Instruction Addressing Mode Bytes Cycles
Z C
LD A, X Short Direct 1 4 ∆ *
LD A, Y Short Direct 1 4 ∆ *
LD A, V Short Direct 1 4 ∆ *
LD A, W Short Direct 1 4 ∆ *
LD X, A Short Direct 1 4 ∆ *
LD Y, A Short Direct 1 4 ∆ *
LD V, A Short Direct 1 4 ∆ *
LD W, A Short Direct 1 4 ∆ *
LD A, rr Direct 2 4 ∆ *
LD rr, A Direct 2 4 ∆ *
LD A, (X) Indirect 1 4 ∆ *
LD A, (Y) Indirect 1 4 ∆ *
LD (X), A Indirect 1 4 ∆ *
LD (Y), A Indirect 1 4 ∆ *
LDI A, #N Immediate 2 4 ∆ *
LDI rr, #N Immediate 3 4 * *

Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory)
rr. Data space register
∆ . Affected
* . Not Affected

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INSTRUCTION SET (Cont’d)

Arithmetic and Logic. These instructions are tent or an immediate value in relation with the ad-
used to perform the arithmetic calculations and dressing mode. In CLR, DEC, INC instructions the
logic operations. In AND, ADD, CP, SUB instruc- operand can be any of the 256 data space ad-
tions one operand is always the accumulator while dresses. In COM, RLC, SLA the operand is always
the other can be either a data space memory con- the accumulator.
Table 21. Arithmetic & Logic Instructions
Flags
Instruction Addressing Mode Bytes Cycles
Z C
ADD A, (X) Indirect 1 4 ∆ ∆
ADD A, (Y) Indirect 1 4 ∆ ∆
ADD A, rr Direct 2 4 ∆ ∆
ADDI A, #N Immediate 2 4 ∆ ∆
AND A, (X) Indirect 1 4 ∆ ∆
AND A, (Y) Indirect 1 4 ∆ ∆
AND A, rr Direct 2 4 ∆ ∆
ANDI A, #N Immediate 2 4 ∆ ∆
CLR A Short Direct 2 4 ∆ ∆
CLR r Direct 3 4 * *
COM A Inherent 1 4 ∆ ∆
CP A, (X) Indirect 1 4 ∆ ∆
CP A, (Y) Indirect 1 4 ∆ ∆
CP A, rr Direct 2 4 ∆ ∆
CPI A, #N Immediate 2 4 ∆ ∆
DEC X Short Direct 1 4 ∆ *
DEC Y Short Direct 1 4 ∆ *
DEC V Short Direct 1 4 ∆ *
DEC W Short Direct 1 4 ∆ *
DEC A Direct 2 4 ∆ *
DEC rr Direct 2 4 ∆ *
DEC (X) Indirect 1 4 ∆ *
DEC (Y) Indirect 1 4 ∆ *
INC X Short Direct 1 4 ∆ *
INC Y Short Direct 1 4 ∆ *
INC V Short Direct 1 4 ∆ *
INC W Short Direct 1 4 ∆ *
INC A Direct 2 4 ∆ *
INC rr Direct 2 4 ∆ *
INC (X) Indirect 1 4 ∆ *
INC (Y) Indirect 1 4 ∆ *
RLC A Inherent 1 4 ∆ ∆
SLA A Inherent 2 4 ∆ ∆
SUB A, (X) Indirect 1 4 ∆ ∆
SUB A, (Y) Indirect 1 4 ∆ ∆
SUB A, rr Direct 2 4 ∆ ∆
SUBI A, #N Immediate 2 4 ∆ ∆
Notes:
X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected
# . Immediate data (stored in ROM memory)* . Not Affected
rr. Data space register

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ST62T18C/E18C

INSTRUCTION SET (Cont’d)

Conditional Branch. The branch instructions Control Instructions. The control instructions
achieve a branch in the program when the select- control the MCU operations during program exe-
ed condition is met. cution.
Bit Manipulation Instructions. These instruc- Jump and Call. These two instructions are used
tions can handle any bit in data space memory. to perform long (12-bit) jumps or subroutines call
One group either sets or clears. The other group inside the whole program space.
(see Conditional Branch) performs the bit test
branch operations.
Table 22. Conditional Branch Instructions
Flags
Instruction Branch If Bytes Cycles
Z C
JRC e C=1 1 2 * *
JRNC e C=0 1 2 * *
JRZ e Z=1 1 2 * *
JRNZ e Z=0 1 2 * *
JRR b, rr, ee Bit = 0 3 5 * ∆
JRS b, rr, ee Bit = 1 3 5 * ∆
Notes :
b. 3-bit address rr. Data space register
e. 5 bit signed displacement in the range -15 to +16<F128M> ∆ . Affected. The tested bit is shifted into carry.
ee. 8 bit signed displacement in the range -126 to +129 * . Not Affected

Table 23. Bit Manipulation Instructions

Flags
Instruction Addressing Mode Bytes Cycles
Z C
SET b,rr Bit Direct 2 4 * *
RES b,rr Bit Direct 2 4 * *
Notes:
b. 3-bit address; * . Not<M> Affected
rr. Data space register;

Table 24. Control Instructions

Flags
Instruction Addressing Mode Bytes Cycles
Z C
NOP Inherent 1 2 * *
RET Inherent 1 2 * *
RETI Inherent 1 2 ∆ ∆
STOP (1) Inherent 1 2 * *
WAIT Inherent 1 2 * *
Notes:
1. This instruction is deactivated<N>and a WAI T is automatically executed instead of a STOP if the watchdog function is selected.
∆ . Affected
*. Not Affected

Table 25. Jump & Call Instructions

Instruction Flags
Addressing Mode Bytes Cycles
Z C
CALL abc Extended 2 4 * *
JP abc Extended 2 4 * *
Notes:
abc. 12-bit address;
* . Not Affected

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Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
LOW LOW
0 1 2 3 4 5 6 7
0000 0001 0010 0011 0100 0101 0110 0111
HI HI
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD
0 e abc e b0,rr,ee e # e a,(x) 0
0000 0000
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 LDI
1 e abc e b0,rr,ee e x e a,nn 1
0001 0001
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 CP
2 e abc e b4,rr,ee e # e a,(x) 2
0010 0010
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 CPI
3 e abc e b4,rr,ee e a,x e a,nn 3
0011 0011
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 ADD
4 e abc e b2,rr,ee e # e a,(x) 4
0100 0100
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 ADDI
5 e abc e b2,rr,ee e y e a,nn 5
0101 0101
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 INC
6 e abc e b6,rr,ee e # e (x) 6
0110 0110
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC
7 e abc e b6,rr,ee e a,y e # 7
0111 0111
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD
8 e abc e b1,rr,ee e # e (x),a 8
1000 1000
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 RNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC
9 e abc e b1,rr,ee e v e # 9
1001 1001
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 AND
A e abc e b5,rr,ee e # e a,(x) A
1010 1010
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 ANDI
B e abc e b5,rr,ee e a,v e a,nn B
1011 1011
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 SUB
C e abc e b3,rr,ee e # e a,(x) C
1100 1100
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 SUBI
D e abc e b3,rr,ee e w e a,nn D
1101 1101
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 DEC
E e abc e b7,rr,ee e # e (x) E
1110 1110
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC
F e abc e b7,rr,ee e a,w e # F
1111 1111
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc

Abbreviations for Addressing Modes: Legend:

dir Direct # Indicates Ill egal Instructions Cycle
sd Short Direct e 5 Bit Displacement 2 JRC Mnemonic
imm Immediate b 3 Bit Address Operand e
inh Inherent rr 1byte dataspace address
Bytes 1 prc
ext Extended nn 1 byte immediate data
b.d Bit Direct abc 12 bit address
Addressing Mode
bt Bit Test ee 8 bit Displacement
pcr Program Counter Relative
ind Indirect

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Opcode Map Summary (Continued)

LOW LOW
8 9 A B C D E F
1000 1001 1010 1011 1100 1101 1110 1111
HI HI
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 LDI 2 JRC 4 LD
0 e abc e b0,rr e rr,nn e a,(y) 0
0000 0000
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD
1 e abc e b0,rr e x e a,rr 1
0001 0001
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 COM 2 JRC 4 CP
2 e abc e b4,rr e a e a,(y) 2
0010 0010
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 CP
3 e abc e b4,rr e x,a e a,rr 3
0011 0011
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RETI 2 JRC 4 ADD
4 e abc e b2,rr e e a,(y) 4
0100 0100
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 ADD
5 e abc e b2,rr e y e a,rr 5
0101 0101
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 STOP 2 JRC 4 INC
6 e abc e b6,rr e e (y) 6
0110 0110
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 INC
7 e abc e b6,rr e y,a e rr 7
0111 0111
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 JRC 4 LD
8 e abc e b1,rr e # e (y),a 8
1000 1000
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind
2 RNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD
9 e abc e b1,rr e v e rr,a 9
1001 1001
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 RCL 2 JRC 4 AND
A e abc e b5,rr e a e a,(y) A
1010 1010
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 AND
B e abc e b5,rr e v,a e a,rr B
1011 1011
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RET 2 JRC 4 SUB
C e abc e b3,rr e e a,(y) C
1100 1100
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 SUB
D e abc e b3,rr e w e a,rr D
1101 1101
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 WAIT 2 JRC 4 DEC
E e abc e b7,rr e e (y) E
1110 1110
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 DEC
F e abc e b7,rr e w,a e rr F
1111 1111
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

Abbreviations for Addressing Modes: Legend:

dir Direct # Indicates Ill egal Instructions Cycle
sd Short Direct e 5 Bit Displacement 2 JRC Mnemonic
imm Immediate b 3 Bit Address Operand e
inh Inherent rr 1byte dataspace address
Bytes 1 prc
ext Extended nn 1 byte immediate data
b.d Bit Direct abc 12 bit address
Addressing Mode
bt Bit Test ee 8 bit Displacement
pcr Program Counter Relative
ind Indirect

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 ST62T18C/E18C

6 ELECTRICAL CHARACTERISTICS

6.1 ABSOLUTE MAXIMUM RATINGS

This product contains devices to protect the inputs Power Considerations.The average chip-junc-
against damage due to high static voltages, how- tion temperature, Tj, in Celsius can be obtained
ever it is advisable to take normal precaution to from:
avoid application of any voltage higher than the Tj=TA + PD x RthJA
specified maximum rated voltages.
Where:TA = Ambient Temperature.
For proper operation it is recommended that VI
and VO be higher than VSS and lower than V DD. RthJA =Package thermal resistance (junc-
Reliability is enhanced if unused inputs are con- tion-to ambient).
nected to an appropriate logic voltage level (VDD PD = Pint + Pport.
or VSS).
Pint =IDD x VDD (chip internal power).
Pport =Port power dissipation (determined
by the user).

Symbol Parameter Value Unit

VDD Supply Voltage -0.3 to 7.0 V
(1)
VI Input Voltage V SS - 0.3 to VDD + 0.3 V
VO Output Voltage V SS - 0.3 to VDD + 0.3 (1) V
IV DD Total Current into VDD (source) 80 mA
IVSS Total Current out of VSS (sink) 100 mA
Tj Junction Temperature 150 °C
TSTG Storage Temperature -60 to 150 °C

Notes:
- Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
- (1) Within these limits, clamping diodes are guarantee to be not conductive. Voltages outside these limits are authorised as long as injection
current is kept within the specification.

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ST62T18C/E18C

6.2 RECOMMENDED OPERATING CONDITIONS

Value
Symbol Parameter Test Condition s Unit
Min. Typ. Max.
6 Suffix Version -40 85
TA Operating Temperature 1 Suffix Version 0 70 °C
3 Suffix Version -40 125
f OSC = 4MHz, 1 & 6 Suffix 3.0 6.0
f OSC = 4MHz, 3 Suffix 3.0 6.0
VDD Operating Supply Voltage V
fosc= 8MHz , 1 & 6 Suffix 3.6 6.0
fosc= 8MHz , 3 Suffix 4.5 6.0
V DD = 3.0V, 1 & 6 Suffix 0 4.0
2) V DD = 3.0V , 3 Suffix 0 4.0
fOSC Oscillator Frequency MHz
V DD = 3.6V , 1 & 6 Suffix 0 8.0
V DD = 3.6V , 3 Suffix 0 4.0
IINJ+ Pin Injection Current (positive) V DD = 4.5 to 5.5V +5 mA
IINJ- Pin Injection Current (negative) V DD = 4.5 to 5.5V -5 mA
Notes:
1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the
A/D conversion. For a -1mA injection, a maximum 10 KΩ is recommended.
2.An oscillator frequency above 1MHz is recommended for reliable A/D results

Figure 34. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (VDD)

Maximum FREQU ENCY (MHz)

1 & 6 Suffix version

8
FUNCTIONALITY IS NOT
3 Suffix version
7 GUARANTEED IN
THIS AREA
6

1
2.5 3 3.6 4 4.5 5 5.5 6

SUPPLY VOLTAGE (VDD)

The shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions.

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 ST62T18C/E18C

6.3 DC ELECTRICAL CHARACTERISTICS

(TA = -40 to +125°C unless otherwise specified)

Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
VIL Input Low Level Voltage
VDD x 0.3 V
All Input pins
VIH Input High Level Voltage
VDD x 0.7 V
All Input pins

Hysteresis Voltage (1) VDD= 5V 0.2

V Hys V
All Input pins VDD= 3V 0.2

Vup LVD Threshold in power-on 4.1 4.3

V dn LVD threshold in powerdown 3.5 3.8
Low Level Output Voltage VDD= 5.0V; IOL = +10µA 0.1
All Output pins VDD= 5.0V; IOL = + 3mA 0.8
VOL VDD= 5.0V; IOL = +10µA 0.1 V
Low Level Output Voltage
VDD= 5.0V; IOL = +7mA 0.8
20 mA Sink I/O pins
VDD= 5.0V; IOL = +15mA 1.3
High Level Output Voltage VDD= 5.0V; IOH = -10µA 4.9
VOH V
All Output pins VDD= 5.0V; IOH = -3.0mA 3.5
All Input pins 40 100 350
R PU Pull-up Resistance ΚΩ
RESET pin 150 350 900
Input Leakage Current VIN = VSS (No Pull-Up configured)
0.1 1.0
IIL All Input pins but RESET VIN = VDD
µA
IIH Input Leakage Current VIN = VSS -8 -16 -30
RESET pin VIN = VDD 10
Supply Current in RESET VRESET=VSS
7.0 mA
Mode fOSC=8MHz
Supply Current in
VDD=5.0V fINT=8MHz 7.0 mA
RUN Mode (2)
Supply Current in WAIT
IDD VDD=5.0V fINT=8MHz 1.5 mA
Mode (3)
Supply Current in STOP ILOAD=0mA
20 µA
Mode, with LVD disabled(3) VDD=5.0V
Supply Current in STOP ILOAD=0mA
500
Mode, with LVD enabled(3) VDD=5.0V
Retention EPROM Data Retention TA = 55°C 10 years

Notes:
(1) Hysteresis voltage between switching levels
(2) All peripherals running
(3) All peripherals in stand-by

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ST62T18C/E18C

DC ELECTRICAL CHARACTERISTICS (Cont’d)

(TA = -40 to +85°C unless otherwise specified))

Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
Vup LVD Threshold in power-on Vdn +50 mV 4.1 4.3 V
V dn LVD threshold in powerdown 3.6 3.8 Vup -50 mV V
VDD= 5.0V; IOL = +10µA 0.1
Low Level Output Voltage
VDD= 5.0V; IOL = + 5mA 0.8
All Output pins
VDD= 5.0V; IOL = + 10mAv 1.2
VOL VDD= 5.0V; IOL = +10µA 0.1 V
Low Level Output Voltage VDD= 5.0V; IOL = +10mA 0.8
20 mA Sink I/O pins VDD= 5.0V; IOL = +20mA 1.3
VDD= 5.0V; IOL = +30mA 2.0
High Level Output Voltage VDD= 5.0V; IOH = -10µA 4.9
VOH V
All Output pins VDD= 5.0V; IOH = -5.0mA 3.5
Supply Current in STOP ILOAD=0mA
IDD 10 µA
Mode, with LVD disabled(*) VDD=5.0V

Note:
(*) All Peripherals in stand-by.

6.4 AC ELECTRICAL CHARACTERISTICS

(TA = -40 to +125°C unless otherwise specified)

Symbol Value
Parameter Test Conditions Unit
Min. Typ. Max.
tREC Supply Recovery Time (1) 100 ms
fLFAO Internal frequency with LFAO active 200 400 800 kHz
VDD = 3V 1
Internal Frequency with OSG VDD = 3.6V 1
fOSG fOSC MHz
enabled 2) VDD = 4.5V 2
VDD = 6V 2
VDD=5.0V
Internal frequency with RC oscillator R=47kΩ 4 5 5.8 MHz
fRC
and OSG disabled 2) 3) R=100kΩ 2.7 3.2 3.5 MHz
R=470kΩ 800 850 900 kHz
CIN Input Capacitance All Inputs Pins 10 pF
C OUT Output Capacitance All Outputs Pins 10 pF

Notes:
1. Period for which VDD has to be connected at 0V to allow internal Reset function at next power-up.
2 An oscillator frequency above 1MHz is recommended for reliable A/D results.
3. Measure performed with OSCin pin soldered on PCB, with an around 2pF equivalent capacitance.

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 ST62T18C/E18C

6.5 A/D CONVERTER CHARACTERISTICS

(TA = -40 to +125°C unless otherwise specified)

Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
Res Resolution 8 Bit
fOSC > 1.2MHz ±2
ATOT Total Accuracy (1) (2) LSB
fOSC > 32kHz ±4
fOSC = 8MHz (TA < 85°C) 70
tC Conversion Time µs
fOSC = 4 MHz 140
Conversion result when
ZIR Zero Input Reading 00 Hex
VIN = VSS
Conversion result when
FSR Full Scale Reading FF Hex
VIN = VDD
Analog Input Current During
AD I VDD= 4.5V 1.0 µA
Conversion
ACIN Analog Input Capacitance 2 5 pF

Notes:
1. Noise at VDD, VSS <10mV
2. With oscillator frequencies less than 1MHz, the A/D Converter accuracy is decreased.

6.6 TIMER CHARACTERISTICS

(TA = -40 to +125°C unless otherwise specified)
Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.

fIN Input Frequency on TIMER Pin

IINT MHz
----------
4
VDD = 3.0V 1 µs
tW Pulse Width at TIMER Pin
VDD >4.5V 125 ns

6.7 SPI CHARACTERISTICS

(TA = -40 to +125°C unless otherwise specified)

6.8 ARTIMER ELECTRICAL CHARACTERISTICS

(TA = -40 to +125°C unless otherwise specified)

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ST62T18C/E18C

Figure 35.. RC frequency versus Vcc

10

R=47K
Frequency

] R=100K
+ 1
0 R=470K

0.1
3 3.5 4 4.5 5 5.5 6
VDD (volts)

Figure 36. LVD thresholds versus temperature

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 ST62T18C/E18C

Figure 37. Idd WAIT versus Vcc at 8 Mhz for OTP devices

1.2
Idd WAIT (mA)

1 T = -40°C
0.8
T = 25°C
0.6
0.4 T = 95°C
0.2 T = 125°C
0
3V 4V 5V 6V
Vdd

This curves represents typical variations and is given for guidance only

Figure 38. Idd STOP versus Vcc for OTP devices

8
Idd WAIT (µA)

6 T = -40°C
4 T = 25°C
2 T = 95°C
0 T = 125°C
-2
3V 4V 5V 6V
Vdd
This curves represents typical variations and is given for guidance only

Figure 39. Idd STOP versus Vcc for ROM devices

2
Idd STOP (µA)

1.5
T = -40°C
1 T = 25°C
0.5 T = 95°C
T = 125°C
0
-0.5
3V 4V 5V 6V
Vdd

This curves represents typical variations and is given for guidance only

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ST62T18C/E18C

Figure 40. Idd WAIT versus Vcc at 8Mhz for ROM devices

0.8
Idd WAIT (mA)

0.6 T= -40°C
T= 25°C
0.4
T= 95°C
0.2
T= 125°C
0
3V 4V 5V 6V
Vdd

This curves represents typical variations and is given for guidance only

Figure 41. Idd RUN versus Vcc at 8 Mhz for ROM and OTP devices

6
Idd RUN (mA)

T = -40°C
T = 25°C
4
T = 95°C
T = 125°C
2

0
3V 4V 5V 6V
Vdd
This curves represents typical variations and is given for guidance only

Figure 42. Vol versus Iol on all I/O port at Vdd=5V

6 T = -40°C
Vol (V)

T = 25°C
4
T = 95°C
2 T = 125°C

0
0 10 20 30 40
Iol (mA)
This curves represents typical variations and is given for guidance only

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 ST62T18C/E18C

Figure 43. Vol versus Iol on all I/O port at T=25°C

8
6 Vdd = 3.0V
Vol (V)

Vdd = 4.0V
4
Vdd = 5.0V
2 Vdd = 6.0V
0
0 10 20 30 40
Iol (mA)

This curves represents typical variations and is given for guidance only
Figure 44. Vol versus Iol for High sink (20mA) I/Oports at T=25°C

5
4
Vdd = 3.0V
Vol (V)

3 Vdd = 4.0V
2 Vdd = 5.0V
1 Vdd = 6.0V

0
0 10 20 30 40
Iol (mA)

Figure 45. Vol versus Iol for High sink (20mA) I/O ports at Vdd=5V

5
4
T= -40°C
Vol (V)

3 T= 25°C
2 T= 95°C
T= 125°C
1
0
0 10 20 30 40
Iol (mA)

This curves represents typical variations and is given for guidance only

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ST62T18C/E18C

Figure 46. Voh versus Ioh on all I/O port at 25°C

6
4 Vdd = 3.0V
Voh (V)

Vdd = 4.0V
2
Vdd = 5.0V
0 Vdd = 6.0V
-2
0 10 20 30 40
Ioh (mA)

Figure 47. Voh versus Ioh on all I/O port at Vdd=5V

4 T= -40°C
Voh (V)

T= 25°C
2
T= 95°C
0 T= 125°C

-2
0 10 20 30 40
Ioh (mA)

This curves represents typical variations and is given for guidance only

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 ST62T18C/E18C

7 GENERAL INFORMATION

7.1 PACKAGE MECHANICAL DATA

Figure 48. 20-Pin Plastic Dual In-Line Package, 300-mil Width

mm inches
Dim.
Min Typ Max Min Typ Max
A 5.33 0.210
A2 2.92 3.30 4.95 0.115 0.130 0.195
b 0.36 0.46 0.56 0.014 0.018 0.022
b2 1.14 1.52 1.78 0.045 0.060 0.070
c 0.20 0.25 0.36 0.008 0.010 0.014
D 24.89 26.92 0.980 1.060
e 2.54 0.100
E1 6.10 6.35 7.11 0.240 0.250 0.280
L 2.92 3.30 3.81 0.115 0.130 0.150
Number of Pins
PDIP20
N 20

Figure 49. 20-Pin Ceramic Side-Brazed Dual In-Line Package

mm inches
Dim.
Min Typ Max Min Typ Max
A 3.63 0.143
A1 0.38 0.015
B 3.56 0.46 0.56 0.140 0.018 0.022
B1 1.14 12.70 1.78 0.045 0.500 0.070
C 0.20 0.25 0.36 0.008 0.010 0.014
D 24.89 25.40 25.91 0.980 1.000 1.020
D1 22.86 0.900
E1 6.99 7.49 8.00 0.275 0.295 0.315
e 2.54 0.100
G 6.35 6.60 6.86 0.250 0.260 0.270
G1 9.47 9.73 9.98 0.373 0.383 0.393
G2 1.14 0.045
L 2.92 3.30 3.81 0.115 0.130 0.150
S 12.70 0.500
Ø 4.22 0.166
CDIP20W Number of Pins
N 20

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ST62T18C/E18C

PACKAGE MECHANICAL DATA (Cont’d)

Figure 50. 20-Pin Plastic Small Outline Package, 300-mil Width

mm inches
Dim.
Min Typ Max Min Typ Max
A 2.35 2.65 0.0926 0.1043
A1 0.10 0.0040
B 0.33 0.51 0.0130 0.0200
C 0.32 0.0125
D 4.98 13.00 0.1961 0.5118
E 7.40 7.60 0.2914 0.2992
e 1.27 0.050
H 10.01 10.64 0.394 0.419
h 0.25 0.74 0.010 0.029
K 0° 8° 0° 8°
L 0.41 1.27 0.016 0.050
G 0.10 0.004
SO20 Number of Pins
N 20

THERMAL CHARACTERISTIC
Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
PDIP20 70
RthJA Thermal Resistance °C/W
PSO20 70

7.2 ORDERING INFORMATION

Table 26. OTP/EPROM VERSION ORDERING INFORMATION

Program
Sales Type I/O Temperature Range Package
Memory (Bytes)
ST62E18CF1 7948 (EPROM) 0 to 70°C CDIP20W
ST62T18CB6 PDIP20
7948 (OTP) -40 to 85°C
ST62T18CM6 12 PSO20
ST62T18CB3 PDIP20
7948 (OTP) -40 to +125°C
ST62T18CM3 PSO20

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 ST62P18C
8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD
TIMER, UART, OSG, SAFE RESET AND 20-PIN PACKAGE

■ 3.0 to 6.0V Supply Operating Range

■ 8 MHz Maximum Clock Frequency
■ -40 to +125°C Operating Temperature Range
■ Run, Wait and Stop Modes
■ 5 Interrupt Vectors
■ Look-up Table capability in Program Memory
■ Data Storage in Program Memory:
User selectable size
■ Data RAM: 192 bytes
■ User Programmable Options PDIP20
■ 12 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
■ 5 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
■ 8-bit Timer/Counter with 7-bit programmable PSO20
prescaler
■ 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer) (See end of Datasheet for Ordering Information)
■ Digital Watchdog
■ 8-bit A/D Converter with 7 analog inputs
■ 8-bit Asynchronous Peripheral Interface
(UART)
■ On-chip Clock oscillator can be driven by Quartz
Crystal or Ceramic resonator
■ Oscillator Safe Guard
■ Low Voltage Detector for safe Reset
■ One external Non-Maskable Interrupt
■ ST623x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
ROM
DEVICE I/O Pins
(Bytes)
ST62P18C 7948 12

Rev. 2.5

November 1999 75/82

75
ST62P18C

1 GENERAL DESCRIPTION
1.1 INTRODUCTION from it. This listing refers exactly to the ROM con-
tents and options which will be used to produce
The ST62P18C are the Factory Advanced Service
the specified MCU. The listing is then returned to
Technique ROM (FASTROM) versions of the customer who must thoroughly check, com-
ST62T18C OTP devices.
plete, sign and return it to STMicroelectronics. The
They offer the same functionality as OTP devices, signed listing forms a part of the contractual agree-
selecting as FASTROM options the options de- ment for the production of the specific customer
fined in the programmable option byte of the OTP MCU.
version. The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
1.2 ORDERING INFORMATION
tractual points.
The following section deals with the procedure for
transfer of customer codes to STMicroelectronics. Table 1. ROM Memory Map for ST62P18C
1.2.1 Transfer of Customer Code ROM Page Device Address Description
Customer code is made up of the ROM contents 0000h-007Fh Reserved
and the list of the selected FASTROM options. Page 0
0080h-07FFh User ROM
The ROM contents are to be sent on diskette, or
by electronic means, with the hexadecimal file 0800h-0F9Fh User ROM
0FA0h-0FEFh Reserved
generated by the development tool. All unused
Page 1 0FF0h-0FF7h Interrupt Vectors
bytes must be set to FFh. “STATIC” 0FF8h-0FFBh Reserved
The selected options are communicated to STMi- 0FFCh-0FFDh NMI Vector
croelectronics using the correctly filled OPTION 0FFEh-0FFFh Reset Vector
LIST appended. 0000h-000Fh Reserved
Page 2
1.2.2 Listing Generation and Verification 0010h-07FFh User ROM
When STMicroelectronics receives the user’s Page 3
0000h-000Fh Reserved
ROM contents, a computer listing is generated 0010h-07FFh User ROM

Table 2. FASTROM version Ordering Information

Sales Type ROM I/O Temperature Range Package
ST62P18CB1/XXX 0 to +70°C
ST62P18CB6/XXX -40 to 85°C PDIP20
ST62P28CB3/XXX(*) -40 to + 125°C
7948 12
ST62P18CM1/XXX 0 to +70°C
ST62P18CM6/XXX -40 to 85°C PSO20
ST62P28CM3/XXX(*) -40 to + 125°C

(*) Advanced information

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 ST62P18C

ST62P18C MICROCONTROLLER OPTION LIST

Customer .. .. . .... . ... .. .. ... ... . ... .. .. .. .. . .. .. .. . . .... . ... .. .

Address .. .. . .... . ... .. .. ... ... . ... .. .. .. .. . .. .. .. . . .... . ... .. .

Contact .. .. . .... . ... .. .. ... ... . ... .. .. .. .. . .. .. .. . . .... . ... .. .

Phone No .. .. . .... . ... .. .. ... ... . ... .. .. .. .. . .. .. .. . . .... . ... .. .
Reference .. .. . .... . ... .. .. ... ... . ... .. .. .. .. . .. .. .. . . .... . ... .. .

STMicroelectronics references

Device: [ ] ST62P18C
Package: [ ] Dual in Line Plastic [ ] Small Outline Plastic
[ ] Tape & Reel [ ] Stick (Default)
Temperature Range: [ ] 0°C to + 70°C [ ] - 40°C to + 85°C [ ] - 40°C to + 125°C
Special Marking: [ ] No [ ] Yes ”_ _ _ _ _ _ _ _ _ _ _ ”
Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.
Maximum character count: PDIP20: 10
PSO20: 8
Oscillator Source Selection: [ ] Crystal Quartz/Ceramic resonator
[ ] RC Network
Watchdog Selection: [ ] Software Activation
[ ] Hardware Activation
Ports Pull-Up: [ ] Enabled [ ] Disabled
NMI Pull-Up: [ ] Enabled [ ] Disabled
Timer Pull-Up: [ ] Enabled [ ] Disabled
External STOP Mode Control: [ ] Enabled [ ] Disabled
OSG: [ ] Enabled [ ] Disabled
ADC SYNCHRO [ ] Enabled [ ] Disabled
UART Frame [ ] 10-bits [ ] 11-bits
ROM Readout Protection: [ ] Disabled (Fuse cannot be blown)
[ ] Enabled (Fuse can be blown by the customer)
Note: No part is delivered with protected ROM.
The fuse must be blown for protection to be effective.

Comments :
Supply Operating Range in the application:
Oscillator Fequency in the application:
Notes .. .. . .... . ... .. .. ... ... . .
Signature
Date

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ST62P18C

Notes:

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 ST6218C
8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD
TIMER, UART, OSG, SAFE RESET AND 20-PIN PACKAGE

■ 3.0 to 6.0V Supply Operating Range

■ 8 MHz Maximum Clock Frequency
■ -40 to +125°C Operating Temperature Range
■ Run, Wait and Stop Modes
■ 5 Interrupt Vectors
■ Look-up Table capability in Program Memory
■ Data Storage in Program Memory:
User selectable size
■ Data RAM: 192 bytes
■ User Programmable Options PDIP20
■ 12 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
■ 5 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
■ 8-bit Timer/Counter with 7-bit programmable PSO20
prescaler
■ 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer) (See end of Datasheet for Ordering Information)
■ Digital Watchdog
■ 8-bit A/D Converter with 7 analog inputs
■ 8-bit Asynchronous Peripheral Interface
(UART)
■ On-chip Clock oscillator can be driven by Quartz
Crystal or Ceramic resonator
■ Oscillator Safe Guard
■ Low Voltage Detector for safe Reset
■ One external Non-Maskable Interrupt
■ ST623x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
ROM
DEVICE I/O Pins
(Bytes)
ST6218C 7948 12

Rev. 2.5

November 1999 79/82

79
ST6218C

1 GENERAL DESCRIPTION

1.1 INTRODUCTION 7.3 ROM READOUT PROTECTION

The ST6218C is mask programmed ROM version If the ROM READOUT PROTECTION option is
of ST62T18C OTP devices. selected, a protection fuse can be blown to pre-
They offer the same functionality as OTP devices, vent any access to the program memory content.
selecting as ROM options the options defined in In case the user wants to blow this fuse, high volt-
the programmable option byte of the OTP version. age must be applied on the TEST pin.

Figure 1. Programming wave form Figure 1. Programming Circuit

0.5s min
TEST

5V 47mF
15
14V typ
10 100nF
5
VSS

VDD
TEST
150 µs typ
PROTECT

100mA TEST 14V

max
100nF
ZPD15
15V

4mA typ VR02003

t
VR02001

Note: ZPD15 is used for overvoltage protection

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 ST6218C

ST6218C MICROCONTROLLER OPTION LIST

Customer .. .. . .... . ... .. .. ... ... . ... .. .. .. .. . .. .. .. . . .... . ... .. .

Address .. .. . .... . ... .. .. ... ... . ... .. .. .. .. . .. .. .. . . .... . ... .. .

Contact .. .. . .... . ... .. .. ... ... . ... .. .. .. .. . .. .. .. . . .... . ... .. .

Phone No .. .. . .... . ... .. .. ... ... . ... .. .. .. .. . .. .. .. . . .... . ... .. .
Reference .. .. . .... . ... .. .. ... ... . ... .. .. .. .. . .. .. .. . . .... . ... .. .

STMicroelectronics references

Device: [ ] ST6218C
Package: [ ] Dual in Line Plastic [ ] Small Outline Plastic
[ ] Tape & Reel [ ] Stick (Default)
Temperature Range: [ ] 0°C to + 70°C [ ] - 40°C to + 85°C [ ] - 40°C to + 125°C
Special Marking: [ ] No [ ] Yes ”_ _ _ _ _ _ _ _ _ _ _ ”
Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.
Maximum character count: PDIP20: 10
PSO20: 8
Oscillator Source Selection: [ ] Crystal Quartz/Ceramic resonator
[ ] RC Network
Watchdog Selection: [ ] Software Activation
[ ] Hardware Activation
Ports Pull-Up: [ ] Enabled [ ] Disabled
NMI Pull-Up: [ ] Enabled [ ] Disabled
Timer Pull-Up: [ ] Enabled [ ] Disabled
External STOP Mode Control: [ ] Enabled [ ] Disabled
OSG: [ ] Enabled [ ] Disabled
ADC SYNCHRO [ ] Enabled [ ] Disabled
UART Frame [ ] 10-bits [ ] 11-bits
ROM Readout Protection: [ ] Disabled (Fuse cannot be blown)
[ ] Enabled (Fuse can be blown by the customer)
Note: No part is delivered with protected ROM.
The fuse must be blown for protection to be effective.

Comments :
Supply Operating Range in the application:
Oscillator Fequency in the application:
Notes .. .. . .... . ... .. .. ... ... . .
Signature
Date

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ST6218C

7.4 ORDERING INFORMATION

The following section deals with the procedure for part of the contractual agreement for the creation
transfer of customer codes to STMicroelectronics. of the specific customer mask.
7.4.1 Transfer of Customer Code The STMicroelectronics Sales Organization will be
Customer code is made up of the ROM contents pleased to provide detailed information on con-
and the list of the selected mask options. The tractual points.
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file gener-
ated by the development tool. All unused bytes Table 1. ROM Memory Map for ST6218C
must be set to FFh.
ROM Page Device Address Description
The selected mask options are communicated to
STMicroelectronics using the correctly filled OP- 0000h-007Fh Reserved
Page 0
0080h-07FFh User ROM
TION LIST appended.
7.4.2 Listing Generation and Verification 0800h-0F9Fh User ROM
0FA0h-0FEFh Reserved
When STMicroelectronics receives the user’s Page 1 0FF0h-0FF7h Interrupt Vectors
ROM contents, a computer listing is generated “STATIC” 0FF8h-0FFBh Reserved
0FFCh-0FFDh NMI Vector
from it. This listing refers exactly to the mask which
0FFEh-0FFFh Reset Vector
will be used to produce the specified MCU. The
listing is then returned to the customer who must Page 2
0000h-000Fh Reserved
thoroughly check, complete, sign and return it to 0010h-07FFh User ROM
STMicroelectronics. The signed listing forms a 0000h-000Fh Reserved
Page 3
0010h-07FFh User ROM
Table 2. ROM version Ordering Information
Sales Type ROM I/O Temperature Range Package
ST6218CB1/XXX 0 to +70°C
ST6218CB6/XXX -40 to 85°C PDIP20
ST6218CB3/XXX -40 to + 125°C
7948 12
ST6218CM1/XXX 0 to +70°C
ST6218CM6/XXX -40 to 85°C PSO20
ST6218CM3/XXX -40 to + 125°C

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics - All Rights Reserved.
Purchase of I2 C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
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http:// www.st.com

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