Charles W Davidson College of Engineering · Electrical Engineering

Digital System Design and Synthesis Section

01
EE 271
Fall 2023 3 Unit(s) 08/21/2023 to 12/06/2023 Modified 08/26/2023

 Contact Information
Instructor: Binh Le

Office Location: Engineering Building, Room 347A

Email: [email protected]

Office Hours: Friday, 17:00 – 18:00, California time (online). In-person appointment can be requested by
email.

Class Days/Time: Friday, 18:00 – 20:45, California time

Classroom: Engineering Building, Room 345

 Course Description and Requisites

In depth study of concepts and practices in modern digital system design, such as high-speed arithmetic,
cache memory design, advanced pipelining and processor design. Verilog or VHDL is used for simulation
and synthesis.

Prerequisite: EE 270.

Letter Graded

 Classroom Protocols
EE 271 students understand that professional attitude is necessary to maintain a comfortable academic
environment for the classroom. For examples:
 - Students will put their cell phones in quiet/vibration mode during the lecture.

- Students understand that drinking water, juices, etc. during the lecture is acceptable but NOT eating.

- Students will not skip the lecture and then ask the instructor to summarize the lecture later on. Office
hours are for students to have questions, not for the instructor to summarize the lecture for any specific
student.

- Students will attend the class on time and leave the class at the end of the lecture.

- Students will consult the course syllabus for class policies and requirements before requesting the
instructor for any special considerations and/or exceptions.

- To minimize possible tension during the exams, students are requested to follow the exam rules closely.

- Students will work on the project and report by their own and will not share the work with other students.

- Students understand that long-term learning is their responsibility and will always keep it up.

 Course Learning Outcomes (CLOs)

Upon successful completion of this course, students will be able to:

CLO 1. Design and manually optimize complex combinational and sequential digital circuits

CLO 2. Model combinational and sequential digital circuits by Verilog HDL

CLO 3. Design and model digital circuits with Verilog HDL at the algorithm (behavioral) and data flow (RTL)
levels as well as with behavioral and structural languages

CLO 4. Develop test benches to verify the design by simulation and analysis

CLO 5. Perform functional and timing verifications of digital circuits

CLO 6. Perform static and dynamic timing analysis with false paths and hazards

CLO 7. Synthesis combinational and sequential circuits with trade-offs in timing, area, and power

CLO 8. Understand the relationships between timing performance, parallelizing and pipelining

CLO 9. Understand fundamental principles of analyzing power distribution and optimizing power
consumption in digital circuits

 Course Materials

Verilog Styles for Synthesis

Author: D. R. Smith and P. D. Franzon
Publisher: Pearson Education
 ISBN: 0-201-61860-5
Optional

Digital Systems Design Using Verilog

Author: Charles Roth, Lizy K. John, Byeong Kil Lee
ISBN: 1285051076
Optional

Other Readings
Any “Verilog Language” books/notes. Below are a few online documents:

http://www.doulos.com/knowhow/verilog_ designers_ guide/

https://www. nandland.com (https://www.nandland.com/)

Other technology requirements / equipment / material

UNIX accounts on Cadence Laboratory

Rooms E289 and E291 are Cadence laboratories installed with Cadence and Synopsys software tools. Each
registered SJSU student should automatically have a UNIX account. Instructions on how to log into Unix
accounts can be found on Canvas, in the Lab documents folder.

EDA Tools

- Synopsys Verilog Compiler Simulator (VCS) (required): Available on SJSU Cadence Lab

- Synopsys Design Compiler (required): Available on SJSU Cadence Lab

- Cadence NC-Verilog Simulator (optional): Available on SJSU Cadence Lab

- Vivado Design Suite (free download from Xilinx)

- Any other Verilog simulators (such as ModelSim PE (optional))

- Documents on how to use the tools can be found on Canvas, in the Lab documents folder

 Course Requirements and Assignments

Lectures

Lectures are delivered in person. The course will follow the selected subjects as listed on the course
description. Additional theories and examples will be given and discussed in class as much as time permits.

- Please note that lecture materials are NOT solely based on the required texts and readings, so students
are responsible for following up the lectures in order to prepare themselves for the exams.

- Students are responsible for reading the texts, handouts, lecture presentations, etc.
- Students are responsible for following up and keeping track of the in-class lecture materials.

- Students are responsible for finding and reading additional books, papers, examples, etc. in order to gain
more understanding of the materials discussed in the lectures.

- Students are responsible for self-learning and using of EDA tools for assigned homework problems, lab
exercises, projects, and for lecture discussions.

Success in this course is based on the expectation that students will spend, for each unit of credit, a
minimum of 45 hours over the length of the course (normally three hours per unit per week) for instruction,
preparation/studying, or course related activities, including but not limited to internships, labs, and clinical
practice. Other course structures will have equivalent workload expectations as described in the syllabus.

Midterm and Final Exams

There will be one midterm exam & a comprehensive final exam. The exam dates are listed on the course
schedule section of this syllabus. Since make-up exams will NOT be given, please make sure that you are
able to attend all exams at the indicated scheduled dates and times (from the beginning of the semester) in
order to register for the course.

- All exams will be held in-class using Canvas and Respondus LockDown Browser + Webcam. Students are
required to bring a laptop and a webcam for taking the exams.

- All exams are closed-book exams.

One sheet (double-side 8.5x11) of hand-written notes is allowed for the midterm exam and two sheets
of hand-written notes are allowed for the final exam.
No calculators are allowed.

- There will be no make-up exams (in very special circumstances, written excuse and official proofs are
required for making-up exams).

- The midterm exam solution will be discussed in class after the exam date.

Design Project

There will be one design project. Project details can be found on Canvas. The due date of the project is
listed on the course schedule section of this syllabus.

Homework Assignments

- Homework assignments with due dates will be given through Canvas. Homework must be submitted
through Canvas and solutions will be available after the due dates.

- Do NOT submit HW via email.

- Late submission will NOT be accepted.

- There is no make-up homework.

 To get credit for your homework assignments, submissions must be neat, clean, and must be done
professionally and seriously. Your official name (not nickname), course #, and homework # must be visibly
shown on each assignment.

Final Examination or Evaluation

- The exam date and time is defined in the Course Schedule (last part of this syllabus) or can be found in
the university final exam schedule.

- It is a comprehensive exam; the exam covers all materials covered in the class.

 Grading Information
The overall course grade (letter-grade) will be assigned based on a defined grading standard as shown
below. The weights of the whole course work assignments are:

1. Homework assignments 10%

2. One midterm exam 30%
3. One final exam 40%
4. Design project 20%

And the overall course grade (letter-grade) will be assigned based on the distribution below:

Grading criteria (Example: 74% results in a grade of C plus):

Grade Percentage

A plus 95% and

above

A 90 to 94%

A minus 87 to 89%

B plus 84 to 86%

B 80 to 83%

B minus 77 to 79%

C plus 74 to 76%
 Grade Percentage

C 70 to 73%

C minus 67 to 69%

D plus 64 to 66%

D 60 to 63%

D minus 57 to 59%

F 0 to 56%

 University Policies
Per University Policy S16-9 (PDF) (http://www.sjsu.edu/senate/docs/S16-9.pdf), relevant university policy
concerning all courses, such as student responsibilities, academic integrity, accommodations, dropping and
adding, consent for recording of class, etc. and available student services (e.g. learning assistance,
counseling, and other resources) are listed on the Syllabus Information
(https://www.sjsu.edu/curriculum/courses/syllabus-info.php) web page. Make sure to visit this page to
review and be aware of these university policies and resources.

 Course Schedule

EE271- Advanced Digital System Design

and Synthesis (Fall 2023)
Course Schedule (Tentative)

Week Date Topics, Readings, Assignments, Deadlines

1 8/25/23 Course syllabus – Class information & policies / Lecture Note #1:
Introduction

Lecture Note #2: Review of Combinational Logic

2 9/01/23 Lecture Note #2 (continue)

Lecture Note #3: Review of Sequential Circuits

3 9/08/23 Lecture Note #3 (continue)

9/15/23 (Brief) Final Project Discussion

4 Lecture Note #4: Verilog HDL Models

5 9/22/23 Lecture Note #4 (continue)

Lecture Note #5: Additional Topics in Verilog

6 9/29/23 Lecture Note #5 (continue)

7 10/06/23 Lecture Note #6: Logic Synthesis

Midterm Review

8 10/13/23 Lecture Note #6 (continue)

Midterm Examination (6:00 – 7:15 PM)

9 10/20/23 Lecture Note #7: Timing Analysis and Optimization

Exam Return & Solution

10 10/27/23 Lecture Note #7 (continue)

Lecture Note #8: Synthesis and Optimizations

11 11/03/23 Lecture Note #8 (continue)

12 11/10/23 Veteran’s Day – No Class

13 11/17/23 Lecture Note #9: Power Analysis and Optimizations

14 11/24/23 Thanksgiving Holiday – No Class

Lecture Note #9 (continue) Review for Final Exam

15 12/01/23 Final Project Report Due (on Canvas)

16 12/08/23 Final Exam: Friday, December 08 (5:15 – 7:30 PM)

Additional Rules for Fall 2023 EE Laboratories

Check SJSU Health Advisories website for updated information about university requirements and rules
https://www.sjsu.edu/healthadvisories/