Marathwada Mitra Mandal’s College of Engineering

Karvenagar , Pune-41 1 052

Accredited with Grade ‘A’ by NAAC

Faculty Orientation Program

on
SE (E&TC/Elex) Revised Syllabus 2019 Course

Subject: Digital Circuits

under the aegis of
Board of Studies E&TC, SPPU, Pune.
[22/06/2020 To 26/06/2020]
Organized By
Department of Electronics & Telecommunication Engineering
 Faculty Orientation Program
on
SE (E&TC/Elex) Revised Syllabus 2019 Course

Subject: Digital Circuits

under the aegis of
Board of Studies E&TC, SPPU, Pune.

Presenter:

Dr. Sheetal Bhandari

Professor and Dean Students Development and welfare
2 Pimpri Chinchwad College of Engineering, Nigdi, Pune 44
 Digital Circuits
Faculty Orientation workshop schedule
Date Time Session Unit Resource person
22.6.20 09.45 am - 10:40 am 1 1 Ms. Sangita K. Bavkar, PVG Pune
11:30 am - 01:00 pm 2 2 Dr Tanuja Khatavkar, PVGCOET Pune
23.6.20 10.00 am - 11:25 am 1 3 Ms. Tanuja Khatavkar, PVGCOET Pune

11.30 am to 01.00 pm 2 4 Dr. S. A. Paithane, RSCOE Pune

24.6.20 10.00 am to 11.25 am 1 5 Dr. Sheetal U. Bhandari, PCCOE Pune
11.30 am to 01.00 pm 2 6 Dr. Sheetal U. Bhandari, PCCOE Pune
25.6.20 02.00 pm to 05.00 pm 1 DC Lab Dr. Dinesh. M. Chandwadkar
Dr. Sunita A. Patil (Ugale)
Ms. Shraddha. D. Shelke, KKWIEER, Nashik
26.6.20 02.00 pm to 05.00 pm 1 DC Lab

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGG 3

 Kind Request
❖ Keep your video off to meet bandwidth requirements
❖ Mute your mic to minimize noise
❖ Be patient in case of any network issue
❖ Note your valuable suggestions and queries for discussion at
the end

DEPARTMENT OF ELECTRONICS AND

4
TELECOMMUNICATION ENGG
 Digital Circuits-Course Details
Programme: UG Programme in E&TC/ Class: S.E (E&TC/ A.Y. 2020-21
Electronics Engineering Electronics) Sem. I
Course Code: 204182 (Theory) Course : Digital Circuits
Corresponding Lab Course Code : Lab Course Name: Digital Circuits Lab
204186
Teaching Scheme Examination Scheme
Theory Practical Tutorial Theory Lab
Online/ Term
(hrs/week) (hrs/week) (hrs/week) Endsem Sessional Practical Oral
Insem Work
3 hrs 2 hrs ---- 30 70 --- 25 -- --

Abstract:
Prerequisite:

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGG 5

 COURSE OBJECTIVES

The course aims to:

1. The fundamental principles of two-valued logic and various devices used to implement logical operations on
variables.

2. Boolean algebra, Karnaugh maps and its application to the design and characterization of digital circuits.
3. To analyze logic processes and implement logical operations using combinational logic circuits.
4. The principles of logic design and use of simple memory devices, flip-flops, and sequential circuits.
5. Concepts of sequential circuits and to analyze sequential systems in terms of state machines.
6. System design approach using programmable logic devices.

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 Unit V- State Machines (7L/40L)
Old New
Basic design steps- State diagram, State table, Basic design steps- State diagram, State table,
State reduction, State assignment, Mealy and State reduction, State assignment, Mealy and
Moore machines representation, Moore machines representation (2.5Hrs),
Implementation, finite state machine Implementation, finite state machine
implementation, Sequence detector. Introduction implementation, Sequence detector. (3Hrs.)
to Algorithmic state machines- construction of Introduction to Algorithmic state machines-
ASM chart and realization for sequential circuits construction of ASM chart and realization for
sequential circuits (1.5Hrs.)
Books:
Digital Principles and Applications, Leach, Malvino, Saha MGH 7th Edition (Chapter 11 Part A)

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGG 7

 Book Contents

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 COURSE OUTCOMES
Mapping
Blooms
Course After successful completion of the course with
Taxonomy PO MAPPING
Outcome students will be able to Syllabus
Level
Unit
Understand, design, implement and analyze Mealy
5 2,3,4 5 1,3
and Moore machines. Understand and design ASM

Program Outcomes (POs)

1. Engineering knowledge:
2. Problem analysis:
3. Design/development of solutions:
4. Conduct investigations of complex problems:
5. Modern tool usage:
6. The engineer and society:
7. Environment and sustainability:
8. Ethics:
9. Individual and team work:
10. Communication:
11. Project management and finance:
12. Life-long learning:

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGG 9

 Prerequisite
❖ K-Map
❖ Excitation Tables ( JK, D and T Flip-Flop)
❖ Some understanding of State Diagram

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 Some Observations
❖ Digital Design- Combinational and Sequential
Student interest, approach decline
❖ Observations- Lot of ambiguity/discomfort
Latch & F/F, Synchronous & Asynchronous, Set-up & Hold
time, Design & Analysis of sequential circuits
❖ Spend time to explain importance of this topic and its
relevance in further connected subjects and real time
applications

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGG 11

 Need and Relevance of the topic-
Motivation for Adult learning
❖ Subject – VLSI Design
❖ Core opportunities – IC Design (Imp. Vertical of Electronics)
❖ Digital Design – DSP, Microcontrollers, Processors etc.
❖ Digital Design – Combinational + Sequential
❖ Applications –
❖ All processors have Control unit which is Sequential design
(Hardwired)
❖ Hardware drivers
❖ Parity checkers
❖ Sequence checkers
DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGG 12
Make them appreciate the technique-FSM

Here is a sequential circuit with

two JK flip-flops. There is one
input, X, and one output, Z.
The values of the flip-flops
(Q1Q0) form the state, or the
memory, of the circuit.
The flip-flop outputs also go
back into the primitive gates on
the left. This fits the general X Z
sequential circuit diagram at the Inputs Combinational Outputs
bottom. circuit

Q0
Memory Q1

13
 FSM design
◦ State tables show the inputs, outputs, and flip-flop state changes for
sequential circuits.
◦ State diagrams are an alternative but equivalent way of showing the same
information.

Inputs Combinational Outputs

circuit

Memory

14
 State table and diagram
We can also represent the state table graphically with a state diagram.
A diagram corresponding to our example state table is shown below.

Present State Inputs Next State Outputs

Q1 Q0 X Q1 Q0 Z
input output
0 0 0 0 0 0 0/0 1/0
0 0 1 0 1 0
0 1 0 1 0 0 1/0
0 1 1 0 1 0 00 01
1 0 0 1 1 0
1/1
1 0 1 0 1 0 0/0 1/0 0/0
1 1 0 0 0 0
1 1 1 0 1 1
0/0
11 10

state
15
Mealy Machine
Moore Machine
 Two Approaches

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 COURSE OUTCOMES

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGG 19

 State transition diagram

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGG 20

Sequence recognizers (Mealy Machine)
A sequence recognizer is a special kind of sequential circuit that looks for a
special bit pattern in some input.
The recognizer circuit has only one input, X.
◦ One bit of input is supplied on every clock cycle. For example, it would take 20
cycles to scan a 20-bit input.
◦ This is an easy way to permit arbitrarily long input sequences.
There is one output, Z, which is 1 when the desired pattern is found.
Our example will detect the bit pattern “1001”:

Inputs: 11100110100 100110…

Outputs: 00000100000 100100…

Here, one input and one output bit appear every clock cycle.
This requires a sequential circuit because the circuit has to “remember” the
inputs from previous clock cycles, in order to determine whether or not a
match was found.
21
Sequential circuit design procedure
Step 1:
Make a state table based on the problem statement. The table should show the
present states, inputs, next states and outputs. (It may be easier to find a state
diagram first, and then convert that to a table.)
Step 2:
Assign binary codes to the states in the state table, if you haven’t already. If
you have n states, your binary codes will have at least
log2 n digits, and your circuit will have at least log2 n flip-flops.
Step 3:
For each flip-flop and each row of your state table, find the flip-flop input
values that are needed to generate the next state from the present state. You can
use flip-flop excitation tables here.
Step 4:
Find simplified equations for the flip-flop inputs and the outputs.
Step 5:
Build the circuit!

22
A basic state diagram
What state do we need for the sequence recognizer?
◦ We have to “remember” inputs from previous clock cycles.
◦ For example, if the previous three inputs were 100 and the current input
is 1, then the output should be 1.
◦ In general, we will have to remember occurrences of parts of the desired
pattern—in this case, 1, 10, and 100.
We’ll start with a basic state diagram:

1/0 0/0 0/0

A B C D

State Meaning
A None of the desired pattern (1001) has been input yet.
B We’ve already seen the first bit (1) of the desired pattern.
C We’ve already seen the first two bits (10) of the desired pattern.
D We’ve already seen the first three bits (100) of the desired pattern.

23
Overlapping occurrences of the pattern
What happens if we’re in state D (the last three inputs were 100), and the current
input is 1?
◦ The output should be a 1, because we’ve found the desired pattern.
◦ But this last 1 could also be the start of another occurrence of the pattern! For
example, 1001001 contains two occurrences of 1001.
◦ To detect overlapping occurrences of the pattern, the next state should be B.

1/0 0/0 0/0

A B C D
1/1
State Meaning
A None of the desired pattern (1001) has been input yet.
B We’ve already seen the first bit (1) of the desired pattern.
C We’ve already seen the first two bits (10) of the desired pattern.
D We’ve already seen the first three bits (100) of the desired pattern.

24
Filling in the other arrows
Remember that we need two outgoing arrows for each node, to
account for the possibilities of X=0 and X=1.
The remaining arrows we need are shown in blue. They also allow for
the correct detection of overlapping occurrences of 1001.
0/0
1/0
1/0 0/0 0/0
A B C D
1/0
0/0 1/1

State Meaning
A None of the desired pattern (1001) has been input yet.
B We’ve already seen the first bit (1) of the desired pattern.
C We’ve already seen the first two bits (10) of the desired pattern.
D We’ve already seen the first three bits (100) of the desired pattern.
25
Step 1: Making a state table
The first thing you have to figure out is precisely how the use of state will help you solve the
given problem.
◦ Make a state table based on the problem statement. The table should show the present states, inputs,
next states and outputs.
◦ Sometimes it is easier to first find a state diagram and then convert that to a table.
This is usually the most difficult step. Once you have the state table, the rest of the design
procedure is the same for all sequential circuits.
Sequence recognizers are especially hard! They’re the hardest example we’ll see in this class,
so if you understand this you’re in good shape.

26
Finally, making the state table
0/0
1/0

1/0 0/0 0/0

A B C D
1/0
0/0 1/1
Present Next
State Input State Output
Remember how the state A 0 A 0
diagram arrows A 1 B 0
B 0 C 0
correspond to rows of the
B 1 B 0
state table: C 0 D 0
C 1 B 0
present input/output next D 0 A 0
state state D 1 B 1

27
Step 2: Assigning binary codes to states
We have four states ABCD, so we need at least two flip-flops Q1Q0.
The easiest thing to do is represent state A with Q1Q0 = 00, B with 01, C with
10, and D with 11.
The state assignment can have a big impact on circuit complexity, but we
won’t worry about that too much in this class.
Present Next
Present Next
State Input State Output
State Input State Output
Q1 Q0 X Q1 Q0 Z
A 0 A 0
0 0 0 0 0 0
A 1 B 0
0 0 1 0 1 0
B 0 C 0
0 1 0 1 0 0
B 1 B 0
0 1 1 0 1 0
C 0 D 0
1 0 0 1 1 0
C 1 B 0
1 0 1 0 1 0
D 0 A 0
1 1 0 0 0 0
D 1 B 1
1 1 1 0 1 1

28
Step 3: Finding flip-flop input values
Next we have to figure out how to actually make the flip-flops change from
their present state into the desired next state.
This depends on what kind of flip-flops you use!
We’ll use two JKs. For each flip-flip Qi, look at its present and next states, and
determine what the inputs Ji and Ki should be in order to make that state change.
Present Next
State Input State Flip flop inputs Output
Q1 Q0 X Q1 Q0 J1 K1 J0 K0 Z
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 0 1 0
1 1 0 0 0 0
1 1 1 0 1 1

29
Finding JK flip-flop input values
For JK flip-flops, this is a little tricky. Recall the characteristic table:
If the present state of a JK flip-flop is 0 and we want the next state to be 1,
then we have two choices for the JK inputs:
◦ We can use JK=10, to explicitly set the flip-flop’s next state to 1.
◦ We can also use JK=11, to complement the current state 0.
So to change from 0 to 1, we must set J=1, but K could be either 0 or 1.
Similarly, the other possible state transitions can all be done in two different
ways as well.

J K Q(t+1) Operation
0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 Q’(t) Complement

30
 JK excitation table
An excitation table shows what flip-flop inputs are required in order to make a desired
state change.

Q(t) Q(t+1) J K Operation

0 0 0 x No change/reset
0 1 1 x Set/complement
1 0 x 1 Reset/complement
1 1 x 0 No change/set

This is the same information that’s given in the characteristic table, but presented
“backwards.”
J K Q(t+1) Operation
0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 Q’(t) Complement

31
Excitation tables for all flip-flops
Q(t) Q(t+1) D Operation
0 0 0 Reset
0 1 1 Set
1 0 0 Reset
1 1 1 Set

Q(t) Q(t+1) J K Operation

0 0 0 x No change/reset
0 1 1 x Set/complement
1 0 x 1 Reset/complement
1 1 x 0 No change/set

Q(t) Q(t+1) T Operation

0 0 0 No change
0 1 1 Complement
1 0 1 Complement
1 1 0 No change

32
Back to the example
We can now use the JK excitation table on the Q(t) Q(t+1) J K
right to find the correct values for each flip- 0 0 0 x
flop’s inputs, based on its present and next states. 0 1 1 x
1 0 x 1
1 1 x 0

Present Next
State Input State Flip flop inputs Output
Q1 Q0 X Q1 Q0 J1 K1 J0 K0 Z
0 0 0 0 0 0 x 0 x 0
0 0 1 0 1 0 x 1 x 0
0 1 0 1 0 1 x x 1 0
0 1 1 0 1 0 x x 0 0
1 0 0 1 1 x 0 1 x 0
1 0 1 0 1 x 1 1 x 0
1 1 0 0 0 x 1 x 1 0
1 1 1 0 1 x 1 x 0 1

33
Step 4: Find equations for the FF inputs and output
Now you can make K-maps and find equations for each of the four flip-flop inputs, as well as for the output Z.
These equations are in terms of the present state and the inputs.
The advantage of using JK flip-flops is that there are many don’t care conditions, which can result in simpler
MSP equations.
Present Next J1 = X’ Q0
State Input State Flip flop inputs Output
Q1 Q0 X Q1 Q0 J1 K1 J0 K0 Z K1 = X + Q 0
0 0 0 0 0 0 x 0 x 0
0 0 1 0 1 0 x 1 x 0
0 1 0 1 0 1 x x 1 0 J0 = X + Q 1
0 1 1 0 1 0 x x 0 0 K0 = X’
1 0 0 1 1 x 0 1 x 0
1 0 1 0 1 x 1 1 x 0
1 1 0 0 0 x 1 x 1 0 Z = Q1 Q0 X
1 1 1 0 1 x 1 x 0 1

34
Step 5: Build the circuit
Lastly, we use these simplified equations to build the completed circuit.

J1 = X’ Q0
K1 = X + Q0

J0 = X + Q1
K0 = X’

Z = Q 1Q0X

35
 Timing diagram
Here is one example timing diagram for our sequence detector.
◦ The flip-flops Q1Q0 start in the initial state, 00.
◦ On the first three positive clock edges, X is 1, 0, and 0. These inputs cause Q1Q0 to change, so after the third edge Q1Q0
= 11.
◦ Then when X=1, Z becomes 1 also, meaning that 1001 was found.
The output Z does not have to change at positive clock edges. Instead, it may change whenever X changes, since
Z = Q1Q0X.
CLK 1 2 3 4

Q1

Q0

36
Building the same circuit with D flip-flops
What if you want to build the circuit using D flip-flops instead?
We already have the state table and state assignments, so we can just start
from Step 3, finding the flip-flop input values.
D flip-flops have only one input, so our table only needs two columns for D1
and D0.
Present Next Flip-flop
State Input State inputs Output
Q1 Q0 X Q1 Q0 D1 D0 Z
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 0 1 0
1 1 0 0 0 0
1 1 1 0 1 1

37
D flip-flop input values (Step 3)
The D excitation table is pretty boring; set Q(t) Q(t+1) D Operation
the D input to whatever the next state 0 0 0 Reset
should be. 0 1 1 Set
1 0 0 Reset
You don’t even need to show separate 1 1 1 Set
columns for D1 and D0; you can just use
the Next State columns.
Present Next Flip flop
State Input State inputs Output
Q1 Q 0 X Q1 Q0 D1 D0 Z
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 0 1 0 0
0 1 1 0 1 0 1 0
1 0 0 1 1 1 1 0
1 0 1 0 1 0 1 0
1 1 0 0 0 0 0 0
1 1 1 0 1 0 1 1

38
Finding equations (Step 4)
You can do K-maps again, to find:

D1 = Q1 Q0’ X’ + Q1’ Q0 X’
D0 = X + Q 1 Q0’
Z = Q1 Q0 X
Present Next Flip flop
State Input State inputs Output
Q1 Q0 X Q1 Q0 D1 D0 Z
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 0 1 0 0
0 1 1 0 1 0 1 0
1 0 0 1 1 1 1 0
1 0 1 0 1 0 1 0
1 1 0 0 0 0 0 0
1 1 1 0 1 0 1 1

39
Building the circuit (Step 5)

40
Flip-flop comparison
JK flip-flops are good because there are many don’t care
values in the flip-flop inputs, which can lead to a simpler
circuit.

D flip-flops have the advantage that you don’t have to set up

flip-flop inputs at all, since Q(t+1) = D. However, the D input
equations are usually more complex than JK input equations

In practice, D flip-flops are used more often.

◦ There is only one input for each flip-flop, not two.
◦ There are no excitation tables to worry about.
◦ D flip-flops can be implemented with slightly less hardware than
JK flip-flops.

41
111 Sequence Detector –Moore Machine

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGG 42

 Summary of FSM Design
:
◦ Draw a state diagram and Make a state table. This step is usually the
hardest.
◦ Assign binary codes to the states if you didn’t already.
◦ Use the present states, next states, and flip-flop excitation tables to find
the flip-flop input values.
◦ Find simplified equations using K-Map for the flip-flop inputs and
outputs and build the circuit.

43
 ASM

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGG 44

 Principle components

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGG 45

 Principle components

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111 Sequence Detector-Mealy machine

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGG 47

 State Reduction Techniques
Removing redundant states
❖ Row elimination

❖ Implication Table

Advantages:
❖ Low power

❖ Fast

❖ Less hardware

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGG 48

 Digital Circuits-Module-V
Delivery Methods (DM)
Chalk & Group Industrial/
ICT Tools Expert Talk Survey Mini project Lab
Talk Discussion Field Visit
√ √ √ --- -- --- -- √

Online mode: Offline mode:

Content Delivery PPTs
❖ Google teams Chalk and Talk
❖ Microsoft Teams Group Activity
Flipped Classroom
❖ Bodhi Tree by IIT-Bombay

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGG 49

 Assessment

Understand, design, implement and analyze Mealy and Moore

machines. Understand and design ASM
❖ Define/Explain: State table, State Diagram, ASM chart notations etc.
(MCQ-GATE )
❖ Design and Implement: FSM Moore/Mealy Sequence Generator,
ASM Chart
❖ Analyze: Differentiation

❖ Lifelong Learning: Real life applications

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGG 50

Suggestions are Welcome!

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGG 51