UNIT-VI COMPUTER ARCHITECTURE AND ORGANIZATION

Computer Arithmetic
Data is manipulated by using the arithmetic instructions in digital computers. Data is
manipulated to produce results necessary to give solution for the computation problems. The
Addition, subtraction, multiplication and division are the four basic arithmetic operations. If we
want then we can derive other operations by using these four operations.
To execute arithmetic operations there is a separate section called arithmetic processing unit
in central processing unit. The arithmetic instructions are performed generally on binary or decimal
data. Fixed-point numbers are used to represent integers or fractions. We can have signed or
unsigned negative numbers. Fixed-point addition is the simplest arithmetic operation.
If we want to solve a problem then we use a sequence of well-defined steps. These steps are
collectively called algorithm. To solve various problems we give algorithms.
In order to solve the computational problems, arithmetic instructions are used in digital
computers that manipulate data. These instructions perform arithmetic calculations.
And these instructions perform a great activity in processing data in a digital computer. As we
already stated that with the four basic arithmetic operations addition, subtraction, multiplication and
division, it is possible to derive other arithmetic operations and solve scientific problems by means
of numerical analysis methods.
A processor has an arithmetic processor (as a sub part of it) that executes arithmetic
operations. The data type, assumed to reside in processor, registers during the execution of an
arithmetic instruction. Negative numbers may be in a signed magnitude or signed complement
representation. There are three ways of representing negative fixed point - binary numbers signed
magnitude, signed 1’s complement or signed 2’s complement. Most computers use the signed
magnitude representation for the mantissa.
6.1 Addition and Subtraction
With Signed –Magnitude Data
We designate the magnitude of the two numbers by A and B. Where the signed numbers are
added or subtracted, we find that there are eight different conditions to consider, depending on the
sign of the numbers and the operation performed. These conditions are listed in the first column of
Table. The other columns in the table show the actual operation to be performed with the
magnitude of the numbers. The last column is needed to present a negative zero. In other words,
when two equal numbers are subtracted, the result should be +0 not -0.
The algorithms for addition and subtraction are derived from the table and can be stated as
follows (the words parentheses should be used for the subtraction algorithm).
Table: Addition and Subtraction of Signed-Magnitude Numbers

Operation Add Magnitudes Subtract Magnitudes

When A > B When A < B When A = B

(+A) + (+B) +(A + B)

(+A) + (– B) + (A – B) – (B – A) + (A – B)

(– A) + (+ B) – (A – B) + (B – A) + (A – B)

(– A) + (– B) – (A + B)

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UNIT-VI COMPUTER ARCHITECTURE AND ORGANIZATION

(+ A) – (+ B) + (A + B) – (B – B) + (A – B)

(+ A) – (– B) + (A + B)

(–A) – (+B) – (A + B)

(–A) – (–B) – (A – B) + (B – A) + (A – B)

When the signs of A and B are same, add the two magnitudes and attach the sign of result is
that of A. When the signs of A and B are not same, compare the magnitudes and subtract the
smaller number from the larger. Choose the sign of the result to be the same as A, if A > B or the
complement of the sign of A if A < B. If the two magnitudes are equal, subtract B from A and make
the sign of the result will be positive.

Figure: Hardware Architecture for Addition and Subtraction of Signed-Magnitude Numbers

Figure: Flowchart

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With Signed –2’s Complement Data

6.2 Multiplication Algorithms

Signed-Magnitude complement
Multiplication of two fixed-point binary numbers in signed magnitude representation is done with
paper and pencil by a process of successive shift and adds operations. This process is best
illustrated with a numerical example:
23 10111 Multiplicand
19 x 10011 Multiplier

10111
10111
00000
00000
10111

437 110110101 Product

This process looks at successive bits of the multiplier, least significant bit first. If the
multiplier bit is 1, the multiplicand is copied as it is; otherwise, we copy zeros. Now we shift
numbers copied down one position to the left from the previous numbers. Finally, the numbers are
added and their sum produces the product.

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UNIT-VI COMPUTER ARCHITECTURE AND ORGANIZATION

When multiplication is implemented in a digital computer, we change the process slightly.

Here, instead of providing registers to store and add simultaneously as many binary numbers as
there are bits in the multiplier, it is convenient to provide an adder for the summation of only two
binary numbers, and successively accumulate the partial products in a register. Second, instead of
shifting the multiplicand to left, the partial product is shifted to the right, which results in leaving
the partial product and the multiplicand in the required relative positions. Now, when the
corresponding bit of the multiplier is 0, there is no need to add all zeros to the partial product since
it will not alter its value.
The hardware for multiplication consists of the equipment given in below Figure. The
multiplier is stored in the register and its sign in Qs. The sequence counter SC is initially set bits in
the multiplier. When the content of the counter reaches zero, the product is complete and we stop
the process.

Table: Numerical Example for Binary Multiplier

Multiplicand B = 10111 E A Q SC
Multiplier in Q 0 00000 10011 101
Qn = 1; add B 10111
First partial product 0 10111
Shift right EAQ 0 01011 11001 100
Qn = 1; add B 10111

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Second partial product 1 00010

Shift right EAQ 1 00001 01100 011
Qn = 0; shift right EAQ 0 01000 10110 010
Qn = 0; shift right EAQ 0 00100 01011 001
Qn = 1; add B 10111
Fifth partial product 0 11011
Shift right EAQ 0 11011

Final product in AQ = 0110110101

Booth’s Multiplication Algorithm (signed-2’s complement)

If the numbers are represented in signed 2’s complement then we can multiply them by
using Booth algorithm. In fact the strings of 0's in the multiplier need no addition but just shifting,
and a string of l's in the multiplier from bit weight 2k to weight 2m can be treated as 2k+1 - 2m. For
example, the binary number 001111 (+15) has a string of 1's from 23 to 20(k = 3, m = 0).
The hardware architecture for Signed – 2’s Complement as shown below

The Flowchart for Signed – 2’s Complement as shown below

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UNIT-VI COMPUTER ARCHITECTURE AND ORGANIZATION

The number can be represented as 2k+1 – 2m = 24- 20= 16 - 1 = 15. Therefore, the
multiplication M x 14, where M is the multiplicand and 14 the multiplier may be computed as M x
24 - M x 21. That is, the product can be obtained by shifting the binary multiplicand M four times to
the left and subtracting M shifted left once.
Booth algorithm needs examination of the multiplier bits and shifting of the partial product.
Prior to the shifting, the multiplicand added to the partial product, subtracted from the partial
product, or left unchanged by the following rules:
1. The multiplicand is subtracted from the partial product when we get the first least significant 1
in a string of 1's in the multiplier.
2. The multiplicand is added to the partial product when we get the first Q (provided that there
was a previous 1) in a string of 0's in the multiplier.
3. The partial product does not change when the multiplier bit is the same as the previous
multiplier bit.
The algorithm applies to both positive and negative multipliers in 2's complement
representation. This is because a negative multiplier ends with a string of l's and the last operation
will be a subtraction of the appropriate weight. For example, a multiplier equal to -14 is represented
in 2's complement as 110010 and is treated as -24 + 22 - 21 = -14.
A numerical example of Booth algorithm is given in Table for n = 5. It gives the multiplication of (-
9) x (-13) = +117.
Table: Example of Multiplication with Booth Algorithm
BR = 10111

Qn Qn+1 BR + 1 = 01001 AC QR Qn+1

SC

10 Initial 00000 10011 0 101

Subtract BR 01001
01001
ashr 00100 11001 1 100
11 ashr 00010 01100 1 011
01 Add BR 10111
11001
ashr 11100 10110 0 010
00 ashr 11110 01011 0 001
10 Subtract BR 01001
00111

ashr 0011 10101 1 000

Array Multiplier
To check the bits of the multiplier one at a time and forming partial products is a sequential
operation requiring a sequence of add and shift micro-operations. The multiplication of two binary
numbers can be done with one micro-operation by using combinational circuit that forms the
product bits all at once.
This is a fast way since all it takes is the time for the signals to propagate through the gates
that form the multiplication array. However, an array multiplier requires a large number of gates,

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and so it is not an economical unit for the development of ICs.

Now we see how an array multiplier is implemented with a combinational circuit. Consider
the multiplication of two 2-bit numbers as shown in Fig. The multiplicand bits are b1 and b0, the
multiplier bits are a1 and a0, and the product is c3 c2 c1 c0. The first partial product is obtained by
multiplying a0 by b1b0. The multiplication of two bits gives a 1 if both bits are 1; otherwise, it
produces a 0. This is identical to an AND operation and can we implement it with an AND gate. As
shown in the diagram, the first partial product is formed by means of two AND gates. The second
partial product is formed by multiplying a1 by b1b0 and is shifted one position to the left. The two
partial products are added with two half-adder (HA) circuits. Usually, there are more bits in the
partial products and it will be necessary to use full-adders to produce the sum. Note that the least
significant bit of the product does not have to go through an adder since it is formed by the output
of the first AND gate.

Figure: 2-bit by 2-bit array multiplier

As a second example, consider a multiplier circuit that multiplies a binary number of four
bits with a number of three bits. Let the multiplicand be represented by b3b2b1b0 and the multiplier
by a2a1a0. Since k=4 and j=3, we need 12 AND gates and two 4-bit adders to produce a product of
seven bits. The logic diagram of the multiplier is shown in Figure.

c6 c5 c4 c3 c2 c1 c0
Figure: 4-bit by 3-bit array multiplier

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6.3 Division Algorithms

Division of two fixed-point binary numbers in signed magnitude representation is
performed with paper and pencil by a process of successive compare, shift and subtract operations.
Binary division is much simpler than decimal division because here the quotient digits are either 0
or 1 and there is no need to estimate how many times the dividend or partial remainder fits into the
divisor. The division process is described in Figure. The divisor B has five bits and the dividend A
had ten bits.
Division: 11010 Quotient = Q
B = 10001 0111000000 Dividend = A
01110 5 bits of A < B, quotient has 5
011100 bits
- 10001 6 bits of A VVB
- 010110 Shift right B and subtract; enter
- -10001 1 in Q
- - 001010 7 bits of remainder V B
- - - 010100 Shift right B and subtract; enter
- - - -10001 1 in Q
- - - -000110 Remainder < B; enter 0 in Q;
- - - - -00110 shift right B
Remainder V B
Shift right B and subtract; enter
1 in Q
Remainder < B; enter 0 in Q
Final remainder

Figure : Example of Binary Division

The devisor is compared with the five most significant bits of the dividend. Since the 5-bit
number is smaller than B, we again repeat the same process. Now the 6-bit number is greater than
B, so we place a 1 for the quotient bit in the sixth position above the dividend. Now we shift the
divisor once to the right and subtract it from the dividend. The difference is known as a partial
remainder because the division could have stopped here to obtain a quotient of 1 and a remainder
equal to the partial remainder. Comparing a partial remainder with the divisor continues the
process. If the partial remainder is greater than or equal to the divisor, the quotient bit is equal to 1.
The divisor is then shifted right and subtracted from the partial remainder. If the partial remainder
is smaller than the divisor, the quotient bit is 0 and no subtraction is needed. The divisor is shifted
once to the right in any case. Obviously the result gives both a quotient and a remainder.
Hardware Implementation for Signed-Magnitude Data
In hardware implementation for signed-magnitude data in a digital computer, it is
convenient to change the process slightly. Instead of shifting the divisor to the right, two dividends,
or partial remainders, are shifted to the left, thus leaving the two numbers in the required relative
position. Subtraction is achieved by adding A to the 2's complement of B. End carry gives the
information about the relative magnitudes.
The hardware required is identical to that of multiplication. Register EAQ is now shifted to
the left with 0 inserted into Qn and the previous value of E is lost. The example is given in Figure
to clear the proposed division process. The divisor is stored in the B register and the double-length
dividend is stored in registers A and Q. The dividend is shifted to the left and the divisor is
subtracted by adding its 2's complement value. E keeps the information about the relative
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magnitude. A quotient bit 1 is inserted into Qn and the partial remainder is shifted to the left to
repeat the process when E = 1. If E = 0, it signifies that A < B so the quotient in Qn remains a 0
(inserted during the shift). To restore the partial remainder in A the value of B is then added to its
previous value. The partial remainder is shifted to the left and the process is repeated again until we
get all five quotient-bits. Note that while the partial remainder is shifted left, the quotient bits are
shifted also and after five shifts, the quotient is in Q and A has the final remainder. Before showing
the algorithm in flowchart form, we have to consider the sign of the result and a possible overflow
condition. The sign of the quotient is obtained from the signs of the dividend and the divisor. If the
two signs are same, the sign of the quotient is plus. If they are not identical, the sign is minus. The
sign of the remainder is the same as that of the dividend.

Figure: Example of Binary Division with Digital Hardware

Below is a flowchart of the hardware multiplication algorithm. In the beginning, the
multiplicand is in B and the multiplier in Q. Their corresponding signs are in Bs and Qs
respectively. We compare the signs of both A and Q and set to corresponding sign of the product
since a double-length product will be stored in registers A and Q. Registers A and E are cleared and
the sequence counter SC is set to the number of bits of the multiplier. Since an operand must be
stored with its sign, one bit of the word will be occupied by the sign and the magnitude will consist
of n-1 bits.
Now, the low order bit of the multiplier in Qn is tested. If it is 1, the multiplicand (B) is
added to present partial product (A), 0 otherwise. Register EAQ is then shifted once to the right to

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form the new partial product. The sequence counter is decremented by 1 and its new value checked.
If it is not equal to zero, the process is repeated and a new partial product is formed. When SC = 0
we stops the process.
The hardware divide algorithm is given in Figure. A and Q contain the dividend and B has
the divisor. The sign of the result is transferred into Q. A constant is set into the sequence counter
SC to specify the number of bits in the quotient. As in multiplication, we assume that operands are
transferred to registers from a memory unit that has words of n bits. Since an operand must be
stored with its sign, one bit of the word will be occupied by the sign and the magnitude will have n-
1 bit.

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An overflow may occur in the division operation, which may be easy to handle if we are
using paper and pencil but is not easy when using hardware. This is because the length of registers
is finite and will not hold a number that exceeds the standard length. To see this, let us consider a
system that has 5-bit registers. We use one register to hold the divisor and two registers to hold the
dividend. From the example of Figure, the quotient will consist of six bits if the five most
significant bits of the dividend constitute a number greater than the divisor. The quotient is to be
stored in a standard 5-bit register, so the overflow bit will require one more flip-flop for storing the
sixth bit. This divide-overflow condition must be avoided in normal computer operations because
the entire quotient will be too long for transfer into a memory unit that has words of standard
length, that is, the same as the length of registers. Provisions to ensure that this condition is detected
must be included in either the hardware or the software of the computer, or in a combination of the
two.
When the dividend is twice as long as the divisor, we can understand the condition for
overflow as follows:
A divide-overflow occurs if the high-order half bits of the dividend makes a number greater
than or equal to the divisor. Another problem associated with division is the fact that a division by
zero must be avoided. The divide-overflow condition takes care of this condition as well. This
occurs because any dividend will be greater than or equal to a divisor, which is equal to zero.
Overflow condition is usually detected when a special flip-flop is set. We will call it a divide-
overflow flip-flop and label it DVF.

6.4 Floating-point Arithmetic operations

In many high-level programming languages we have a facility for specifying floating-point
numbers. The most common way is by a real declaration statement. High level programming
languages must have a provision for handling floating-point arithmetic operations. The operations
are generally built in the internal hardware. If no hardware is available, the compiler must be
designed with a package of floating-point software subroutine. Although the hardware method is
more expensive, it is much more efficient than the software method. Therefore, floating- point
hardware is included in most computers and is omitted only in very small ones.
Basic Considerations
There are two part of a floating-point number in a computer - a mantissa m and an exponent
e. The two parts represent a number generated from multiplying m times a radix r raised to the
value of e. Thus
m x re
The mantissa may be a fraction or an integer. The position of the radix point and the value
of the radix r are not included in the registers. For example, assume a fraction representation and a
radix 10. The decimal number 537.25 is represented in a register with m = 53725 and e = 3 and is
interpreted to represent the floating-point number
.53725 x 103
A floating-point number is said to be normalized if the most significant digit of the mantissa
in nonzero. So the mantissa contains the maximum possible number of significant digits. We cannot
normalize a zero because it does not have a nonzero digit. It is represented in floating-point by all
0’s in the mantissa and exponent.
Floating-point representation increases the range of numbers for a given register. Consider a
computer with 48-bit words. Since one bit must be reserved for the sign, the range of fixed-point
integer numbers will be + (247 – 1), which is approximately + 1014. The 48 bits can be used to
represent a floating-point number with 36 bits for the mantissa and 12 bits for the exponent.

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Assuming fraction representation for the mantissa and taking the two sign bits into consideration,
the range of numbers that can be represented is + (1 – 2-35) x 22047

This number is derived from a fraction that contains 35 1’s, an exponent of 11 bits
(excluding its sign), and because 211–1 = 2047. The largest number that can be accommodated is
approximately 10615. The mantissa that can accommodated is 35 bits (excluding the sign) and if
considered as an integer it can store a number as large as (235 –1). This is approximately equal to
1010, which is equivalent to a decimal number of 10 digits.
Computers with shorter word lengths use two or more words to represent a floating-point
number. An 8-bit microcomputer uses four words to represent one floating-point number. One word
of 8 bits are reserved for the exponent and the 24 bits of the other three words are used in the
mantissa.
Arithmetic operations with floating-point numbers are more complicated than with fixed-
point numbers. Their execution also takes longer time and requires more complex hardware.
Adding or subtracting two numbers requires first an alignment of the radix point since the exponent
parts must be made equal before adding or subtracting the mantissas. We do this alignment by
shifting one mantissa while its exponent is adjusted until it becomes equal to the other exponent.
Consider the sum of the following floating-point numbers:
.5372400 x 102 + .1580000 x 10-1
It is necessary to make two exponents be equal before the mantissas can be added. We can
either shift the first number three positions to the left, or shift the second number three positions to
the right. When we store the mantissas in registers, shifting to the left causes a loss of most
significant digits. Shifting to the right causes a loss of least significant digits. The second method is
preferable because it only reduces the accuracy, while the first method may cause an error. The
usual alignment procedure is to shift the mantissa that has the smaller exponent to the right by a
number of places equal to the difference between the exponents. Now, the mantissas can be added.
. 5372400 x 102 +. 0001580 x 102 = . 5373980 x 102
When two normalized mantissas are added, the sum may contain an overflow digit. An
overflow can be corrected easily by shifting the sum once to the right and incrementing the
exponent. When two numbers are subtracted, the result may contain most significant zeros as
shown in the following example:
.56780 x 105 - .56430 x 105 = .00350 x 105
An underflow occurs if a floating-point number that has a 0 in the most significant position
of the mantissa. To normalize a number that contains an underflow, we shift the mantissa to the left
and decrement the exponent until a nonzero digit appears in the first position. Here, it is necessary
to shift left twice to obtain .35000 x 103. In most computers a normalization procedure is performed
after each operation to ensure that all results are in a normalized form.
Floating-point multiplication and division need not do an alignment of the mantissas.
Multiplying the two mantissas and adding the exponents can form the product. Dividing the
mantissas and subtracting the exponents perform division.
The operations done with the mantissas are the same as in fixed-point numbers, so the two
can share the same registers and circuits. The operations performed with the exponents are
compared and incremented (for aligning the mantissas), added and subtracted (for multiplication)
and division), and decremented (to normalize the result). We can represent the exponent in any one
of the three representations - signed-magnitude, signed 2’s complement or signed 1’s complement.
Biased exponents have the advantage that they contain only positive numbers. Now it
becomes simpler to compare their relative magnitude without bothering about their signs. Another

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advantage is that the smallest possible biased exponent contains all zeros. The floating-point
representation of zero is then a zero mantissa and the smallest possible exponent.

Register Configuration
The register configuration for floating-point operations is shown in figure. As a rule, the
same registers and adder used for fixed-point arithmetic are used for processing the mantissas. The
difference lies in the way the exponents are handled.
The register organization for floating-point operations is shown in Fig. Three registers are
there, BR, AC, and QR. Each register is subdivided into two parts. The mantissa part has the same
uppercase letter symbols as in fixed-point representation. The exponent part may use corresponding
lower-case letter symbol.

Figure: Registers for Floating Point arithmetic operations

The AC has a mantissa whose sign is in As, and a magnitude that is in A. The diagram
shows the most significant bit of A, labeled by A1. The bit in his position must be a 1 to normalize
the number. Note that the symbol AC represents the entire register, that is, the concatenation of As,
A and a.
In the similar way, register BR is subdivided into Bs, B, and b and QR into Qs, Q and q. A
parallel-adder adds the two mantissas and loads the sum into A and the carry into E. A separate
parallel adder can be used for the exponents. The exponents do not have a district sign bit because
they are biased but are represented as a biased positive quantity. It is assumed that the floating-
point numbers are so large that the chance of an exponent overflow is very remote and so the
exponent overflow will be neglected. The exponents are also connected to a magnitude comparator
that provides three binary outputs to indicate their relative magnitude.
The number in the mantissa will be taken as a fraction, so they binary point is assumed to reside to
the left of the magnitude part. Integer representation for floating point causes certain scaling
problems during multiplication and division. To avoid these problems, we adopt a fraction
representation.
The numbers in the registers should initially be normalized. After each arithmetic operation,
the result will be normalized. Thus all floating-point operands are always normalized.

Addition and Subtraction of Floating Point Numbers

During addition or subtraction, the two floating-point operands are kept in AC and BR. The
sum or difference is formed in the AC. The algorithm can be divided into four consecutive parts:
1. Check for zeros.
2. Align the mantissas.
3. Add or subtract the mantissas
4. Normalize the result

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A floating-point number cannot be normalized, if it is 0. If this number is used for computation,

the result may also be zero. Instead of checking for zeros during the normalization process we
check for zeros at the beginning and terminate the process if necessary. The alignment of the
mantissas must be carried out prior to their operation. After the mantissas are added or subtracted,
the result may be un-normalized. The normalization procedure ensures that the result is normalized
before it is transferred to memory.
For adding or subtracting two floating-point binary numbers, if BR is equal to zero, the
operation is stopped, with the value in the AC being the result. If AC = 0, we transfer the content of
BR into AC and also complement its sign we have to subtract the numbers. If neither number is
equal it to zero, we proceed to align the mantissas.
The magnitude comparator attached to exponents a and b gives three outputs, which show their
relative magnitudes. If the two exponents are equal, we go to perform the arithmetic operation. If
the exponents are not equal, the mantissa having the smaller exponent is shifted to the right and its
exponent incremented. This process is repeated until two exponents are equal.
The addition and subtraction of the two mantissas is similar to the fixed-point addition and
subtraction algorithm presented in Fig. The magnitude part is added or subtracted depends on the
operation and the signs of the two mantissas. If an overflow occurs when the magnitudes are added,
it is transferred into flip-flop E. If E = 1, the bit is transferred into A1 and all other bits of A are
shifted right. The exponent must be incremented so that it can maintain the correct number. No
underflow may occur in this case this is because the original mantissa that was not shifted during
the alignment was already in a normalized position.
If the magnitudes were subtracted, there may be zero or may have an underflow in the result. If
the mantissa is equal to zero the entire floating-point number in the AC is cleared to zero.
Otherwise, the mantissa must have at least one bit that is equal to 1. The mantissa has an underflow
if the most significant bit in position A1, is 0. In that case, the mantissa is shifted left and the
exponent decremented. The bit in A1 is checked again and the process is repeated until A1 = 1.
When A1 = 1, the mantissa is normalized and the operation is completed.

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Figure: Addition and Subtraction of floating –point numbers

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