Microprocessor Architecture
Microprocessor Architecture
Register Types
General Purpose Registers (AX, BX, CX, DX): Used to store operands and results of
arithmetic/logical operations. Can be used as 8-bit or 16-bit registers.
Index and Pointer Registers (SP, BP, SI, DI): Used to store offsets for addressing memory.
Segment Registers (CS, DS, SS, ES): Used to identify code, data, stack, and extra segments
respectively.
Status Flags
CF, AF, PF, ZF, SF, TF, IF, DF
Addressing Modes
Immediate: Operand is part of instruction
Direct: Explicit memory address is part of instruction
Register: Operand is in register
Register Indirect: Effective address is in register
Based Register Indirect: Effective address is (Base Register) + Offset
Based Indexed Indirect: Effective address is (Base Register) + (Index Register) + Offset
Memory Organization
,F0000-FFFFF, 64KB System ROM ,E0000-EFFFF, 64KB System ROM ,D0000-DFFFF, 64KB
Expansion ROM ,C0000-CFFFF, 64KB Expansion ROM ,A0000-AFFFF, 64KB Video Memory
,90000-9FFFF, 64KB User Memory up to 640KB ,80000-8FFFF, 64KB User Memory up to 576KB
,70000-7FFFF, 64KB User Memory up to 512KB ,60000-6FFFF, 64KB User Memory up to 448KB
,50000-5FFFF, 64KB User Memory up to 384KB ,40000-4FFFF, 64KB User Memory up to 320KB
,30000-3FFFF, 64KB User Memory up to 256KB ,20000-2FFFF, 64KB User Memory up to 192KB
,10000-1FFFF, 64KB User Memory up to 128KB ,00000-0FFFF, 64KB User Memory up to 64KB
Microprocessor 80286
Addressing Modes
Real Address Mode: Compatible with 8086, 1MB address space
Protected Virtual Address Mode: 16MB physical, 1GB virtual address space using segmentation and
paging
Protection Rings
0: Most privileged, 1, 2, 3: Least privileged
Segment Registers
Code Segment: CS
Data Segment: DS
Stack Segment: SS
Extra Segment: ES
Descriptor Tables
Global Descriptor Table: GDT
Local Descriptor Table: LDT
Data Formats
Single Precision: Sign bit, 8-bit exponent, 23-bit mantissa
Double Precision: Sign bit, 11-bit exponent, 52-bit mantissa
Extended Precision: Sign bit, 15-bit exponent, 64-bit mantissa
Operations
Arithmetic, exponential, logarithmic, trigonometric instructions
Protection Mechanisms
Segment Descriptor Access Bytes
Code: R, W
Data: R, W
LDT: N/A
Privilege Levels
Levels 0-2, Level 3 least privileged
Multitasking Support
Task Register
Points to TSS of currently running task
Task Switching
Hardware saves/restores context on task switches
Memory Management
Segmentation
Logical grouping of physical memory using segments
Paging
Maps virtual to physical addresses using page tables
Stack Switching
Switches to TSS stack on privilege level changes
Data Formats
Single precision: 1-bit sign, 8-bit exponent, 23-bit mantissa
Double precision: 1-bit sign, 11-bit exponent, 52-bit mantissa
Extended precision: 1-bit sign, 15-bit exponent, 64-bit mantissa
Operations
Arithmetic, trigonometric, exponential instructions
Exception Reporting
Reports underflow, overflow, invalid operation exceptions
Segment Descriptor
Base, Limit, Access bytes, Privilege level
Linear to Physical Address Translation
Segment Base + Offset -> Physical Address
Access Checks
Checks DPL vs CPL on descriptor access
Task Management
Task Register
Points to TSS of currently running task
Task Switching
Hardware saves/restores context on switches
Local Descriptor Table
Per-task descriptor table pointed to by LDT register
Memory Management
Segmentation
Logical grouping of physical memory using segments
Paging
Maps virtual addresses to physical using page tables
Virtual Memory
Combines segmentation and paging across storage
Privilege Checks
Checks DPL vs CPL on descriptor access
Boundary Checking
Checks offset vs limit on memory access
Stack Switching
Switches stacks on privilege level changes
Data Formats
Single: 1-bit sign, 8-bit exponent, 23-bit mantissa
Double: 1-bit sign, 11-bit exponent, 52-bit mantissa
Extended: 1-bit sign, 15-bit exponent, 64-bit mantissa
Operations
Arithmetic, trigonometric, exponential instructions
Exception Reporting
Reports underflow, overflow, invalid operation exceptions
Segment Descriptor
Base, Limit, Access bytes, Privilege level