CENG 103

Introduction to Computer Engineering

Part II – Boolean Algebra and Digital Logic

Prof. Dr. Semih Bilgen

Istanbul Okan University
 Boolean Algebra
Logical variable (Boolean Variable, or simply «Boolean»):
A variable which can take one of two values: True/False, or 1/0.
Logical operation (Boolean operation):

A B «AND» «OR» (AvB) «NOT» (~ A) «XOR»

(AΛB) or or (A+B) or (A’) (A⊕B)
(A.B)
0 0 0 0 1 0
0 1 0 1 1 1
1 0 0 1 0 1
1 1 1 1 0 0
 Bitwise Boolean operations
e.g.
a 00101101
b 11101000
~a (NOT) 11010010
a.b (AND) 00101000
a+b (OR) 11101101
~(a.b) (NOT AND : NAND) 11010111
ab (= ~a + b) (A IMPLIES B : (NOT A) OR B) 11111010
a⊕b 11000101
(XOR : (A AND NOT B) OR (B AND NOT A))
 Equality of Boolean expressions –
Boolean Algebra
Theorems of Boolean Algebra:
Commutative: X+Y = Y+X, X.Y = Y.X Complement: X+X’ = 1
Associative: X + Y + Z = (X + Y) + Z = X + (Y + Z) X.X’ = 0
X.Y.Z = (X.Y).Z = X.(Y.Z) Double Negation: (X’)’ = X
Distributive: X.(Y+Z) = X.Y + X.Z De Morgan: (X.Y)’ = X’ + Y’
X + Y.Z = (X+Y).(X+Z) (X+Y)’ = X’.Y’
Idempotent: X+X = X, X.X = X Absorption: X + X.Y = X
AND Rule: X.1 = X, X.0 = 0 X (X+Y) = X
OR Rule: X+1 = 1, X+0 = X
 De Morgan’s Laws
~(A+B) = (~A).(~B)
~(A.B) = (~A) + (~B)

A B ~A ~B A.B A+B ~(A.B) ~(A+B) (~A)+(~B) (~A).(~B)

0 0 1 1 0 0 1 1 1 1
0 1 1 0 0 1 1 0 1 0
1 0 0 1 0 1 1 0 1 0
1 1 0 0 1 1 0 0 0 0
 Boolean Algebra - Examples

Simplify F = A.(A+B’) Simplify F = AB+AB’

F = A.A + A.B’ (distributive) F = A.(B+B’) (distributive)

F = A + A.B’ (idempotence) F = A.1 (complement)
F = A.(1+B’) (AND rule; distributive) F = A (AND rule)
F = A.1 (OR rule)
F = A (AND rule)
 Digital Logic
Logic Gates:
Inverter (NOT Gate) AND Gate OR Gate
 Basic logic gates
The use of transistors for the
construction of logic gates
depends upon their utility as
fast switches.

When the base-emitter diode is

turned on enough to be driven
into saturation, the collector
voltage (VCC) with respect to
NOR : NOT OR ~(A+B) the emitter may be near zero
NAND: NOT AND ~(A.B) and can be used to construct OR Gate
gates for the TTL logic family.

For the OR logic, the transistors are For the AND logic, the
in parallel and when one or both of transistors are in series and
the transistors are in the conducting both transistors must be in the
state, the output will be high. conducting state to drive the
output high.
 Combinational circuits
Logic circuits whose outputs at any time depend on inputs supplied at
that time.
e.g. 2-to-4 decoder: e.g. 3-to-8 decoder:

D0 = A0’.A1’
…
D3 = A0.A1
 Using smaller circuits to build larger ones:
e.g. Constructing a 3-to-8 decoder with two 2-to4 decoders:
 Another common combinational circuit family:
Multiplexer (MUX): Only the input signal selected by the «select» signal is transferred to the output.
e.g. 4-to-1 MUX: e.g. 8-to-1 MUX:
 Basic arithmetic circuits:
One bit (half) adder: One bit full adder:
Sum = A⊕ B, Carry = A.B

A B S C
0 0 0 0
0 1 1 0
1 0 1 0
One bit full adder,
1 1 0 1 an alternative realisation

 Sequential circuits
The output of a sequential circuit depends on earlier inputs as well as
the current inputs. That is, the circuit «remembers» earlier inputs. That
is, sequential circuits store information  Memory.
Outputt = F (Inputt , Statet)
Statet+1 = G (Inputt , Statet) (State Transition Function)
Simplest sequential circuit: One bit memory (R-S flip-flop):
When S=R=1, the state (Q) does not change,
regardless of whether it is 0 or 1.

If briefly S=0 and R=1, Q will become 1 (The FF will be SET),

and similarly, if briefly R=0 and S=1, Q will become 0
(that is, the FF will be RESET).
 Gated D-Latch (or D Flip Flop or D-FF)
S

Rather than controlling the FF with a «brief application» of the control signal, that is R or S,
state change in the gated D-Latch will ocur only when «Enable» = 1.
When «Enable» is momentarily set to 1, exactly one of the outputs S or R will be set to 0,
depending on the value of D. If D equals 1, then S is set to 0.
If D equals 0, then both inputs to the lower NAND gate are 1, resulting in R being set to 0.
As we saw earlier, if S is set to 0, the R-S latch is set to 1. If R is set to 0, the R-S latch is set to 0.
Thus, the R-S latch is set to 1 or 0 according to whether D is 1 or 0.
When «Enable» returns to 0, both S and R return to 1, and the value stored in the R-S latch persists.
 Computer Memory
e.g.
Eight «words», each 4 bits long,
addressable with 3-bit addresses.

In this example, since addresses

are 3 bits long, the «address space»
has a size of 23 = 8 words.
Remember, one of 2n options can be
selected with an n-bit code, here
used as an «address» to access a
word of memory.
So if the memory consists of, say, 1024
(= 210) words, addresses must be 10 bits
long, to be able to select (or «access», or
«address») one among all 1024 words.
 Physical kinds of memory devices:
RAM: Random Access Memory
A memory device consisting of address inputs as well as data words,
together with the address decoding and data multiplexing circuitry.
RAM may be of static (SRAM, power refresh needed less frequently) or
dynamic (DRAM, power must be continually supplied) type.
SRAM consists of 6 transistors per bit, whereas DRAM is built with a
single transistor and a capacitor per bit.
Synchronous Dynamic RAM (SDRAM) is a newer and more widely used
kind of DRAM, in which an extra «clock» signal controls data read/write
operations.
 ROM: Read Only Memory
• Fundamental property: Non-volatile – stores information without power
supplied
• Types:
• MROM: Masked ROM: Info stored only at manufacturing time – not practical.
• PROM: Programmable ROM: Info loaded once by users (programmers) but not
modifiable.
• EPROM: Erasable Programmable ROM: Info can be erased on a UV device and re-
programmed.
• EEPROM: Electrically Erasable Programmable ROM: Re-programmed without having
to remove from the device.
• Flash ROM: Or simply «flash memory», fast readable/writable memory – (not exactly
«ROM» any more, and the most common memory type used currently)
RAM vs ROM comparison
RAM ROM
RAMs are volatile and they can ROMs are non-volatile so they
only store data and programs can store data permanently for
temporarily. decades.
Only the ROMs installed for
processors are fast but most of
RAMs are way faster than ROMs.
the ROMs are slower than
RAMs.
RAMs operate on high Most of the ROMs cannot
frequencies. operate on high frequencies.
Only a small number of ROMs
All RAMs can directly
can communicate with
communicate with the CPU.
processors directly.
Most of the devices do not have Nearly all of the digital devices
RAMs. have ROM.
The expense of RAM depends on Expense on ROM depends on its
its capacity and quantity. type and its function.
RAMs need refreshing pulses ROMs do not need refreshing
continuously. signals.
 Sequential logic circuits – an example
e.g. A sequential circuit with two D Flip-Flops, A and B; two inputs, x
and y, and one output, z, is specified by the following next-state and
output equations:
A(t+1) = x′y + xA
B(t+1) = x′B + xA
z=B
a) Draw the logic diagram of the circuit.
b) List the state table for the sequential circuit.
c) Draw the corresponding state diagram.
 z=B

a) Draw the logic diagram of the circuit.

e.g. continued
b) List the–state
(a)table
logic diagram
for the sequentialof the
circuit. given circuit
c) Draw the corresponding state diagram.

A(t+1) = x′y + xAa)

B(t+1) = x′B + xA
z=B

Page: 2
 e.g. continued – (b) state table
b)

Present State Inputs Next State Output

A(t+1) = x′y + xA A B x y A B z
B(t+1) = x′B + xA 0 0 0 0 0 0 0
z=B 0 0 0 1 1 0 0
0 0 1 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 1 1
0 1 0 1 1 1 1
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 0 0 0
1 0 0 1 1 0 0
1 0 1 0 1 1 0
1 0 1 1 1 1 0
1 1 0 0 0 1 1
1 1 0 1 1 1 1
1 1 1 0 1 1 1
1 1 1 1 1 1 1
 1 0 1 0 1 1 0
1 0 1 1 1 1 0
1 1 0 0 0 1 1
1 1 0 1 1 1 1
e.g. continued – (c) state diagram
1
1
1
1
1
1
0
1
1
1
1
1
1
1

c)

A(t+1) = x′y + xA
B(t+1) = x′B + xA
z=B
 Another example: A single RSFF
State: Q, Inputs: RS
Q R S Qt+1 Qt+1 = QR + Q’S’
0 0 0 1
0 0 1 0 R1 1S
0 1 0 0
0 1 1 1 0 R0 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
0S

NOTE: Each FF can be in one of 2 states, so with N flip flops, a machine with 2N states can be constructed.