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VLIW ARCHITECTURE and Pipeline

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Suman Chatterjee
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24 views5 pages

VLIW ARCHITECTURE and Pipeline

vliw

Uploaded by

Suman Chatterjee
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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What is VECTOR PROCESSOR:

Vector processor is basically a central processing unit that has


the ability to execute the complete vector input in a single
instruction. More specifically we can say, it is a complete unit of
hardware resources that executes a sequential set of similar
data items in the memory using a single instruction.
Unlike scalar processors that operate on only a single pair of
data, a vector processor operates on multiple pair of data.
However, one can convert a scalar code into vector code. This
conversion process is known as vectorization. So, we can say
vector processing allows operation on multiple data elements
by the help of single instruction.

These instructions are said to be single instruction multiple


data or vector instructions. The CPU used in recent time
makes use of vector processing as it is advantageous than
scalar processing.
Let us now move further to understand how the vector
processor functions.

Explain the Architecture and Working of vector


processor
The figure below represents the typical diagram showing vector
processing by a vector computer:
The functional units of a vector computer are as follows:

 IPU or instruction processing unit


 Vector register
 Scalar register
 Scalar processor
 Vector instruction controller
 Vector access controller
 Vector processor
As it has several functional pipes thus it can execute the
instructions over the operands. We know that both data and
instructions are present in the memory at the desired memory
location. So, the instruction processing unit i.e., IPU fetches the
instruction from the memory.
Once the instruction is fetched then IPU determines either the
fetched instruction is scalar or vector in nature. If it is scalar in
nature, then the instruction is transferred to the scalar register
and then further scalar processing is performed.

While, when the instruction is a vector in nature then it is


fed to the vector instruction controller. This vector instruction
controller first decodes the vector instruction then accordingly
determines the address of the vector operand present in the
memory.
Then it gives a signal to the vector access controller about
the demand of the respective operand. This vector access
controller then fetches the desired operand from the memory.
Once the operand is fetched then it is provided to the
instruction register so that it can be processed at the vector
processor.
At times when multiple vector instructions are present, then the
vector instruction controller provides the multiple vector
instructions to the task system. And in case the task system
shows that the vector task is very long then the processor
divides the task into subvectors.

These subvectors are fed to the vector processor that makes


use of several pipelines in order to execute the instruction over
the operand fetched from the memory at the same time.

Advantages of Vector Processor

 Vector processor uses vector instructions by which code


density of the instructions can be improved.
 The sequential arrangement of data helps to handle the
data by the hardware in a better way.
 It offers a reduction in instruction bandwidth.

Explain different Types of Vector Instructions


There are various types of vector instructions which are as follows −
 Vector-vector instructions − One or two vector operands
are fetched from the specific vector registers, introduce
through a functional pipeline unit and make results in another
vector register. These instructions are defined by the following
two mappings −
f 1 : v i → vj
f2: vj x vk − vi
 Vector-scalar instructions − As shown in the figure, it
shows a vector-scalar instruction corresponding to the
following mapping −
f3: s x vi −> vj
 Vector-memory instructions − This corresponds to vector
load or vector store element by element, between the vector
register (V) and the memory (M) as defined below −
f4: M → V Vector Load
f5: V → M Vector Store

 Vector reduction instructions − These correspond to the


following mappings −
f6: vi − sj
f7: v x vj − sk
 Gather and scatter instructions − These instructions use
two vector registers to gather or to scatter vector elements
randomly throughout the memory, corresponding to the
following mappings −
a: M → v1 x v0 Gather
fa: v1 x v0 − M Scatter
Gather is an operation that fetches from memory the nonzero
elements of a sparse vector using indices that themselves are
indexed.
Scatter does the opposite, storing into memory a vector in a
sparse vector whose nonzero entries are indexed. The vector
register contains the data and the vector register is used as an
index to gather or scatter data from or to random memory
locations respectively.
 Masking instructions − In masking instructions, it uses a
mask vector to wrap or to broaden a vector to a shorter or
longer index vector, respectively, equivalent to the following
mappings −
f10: v0x vm → v1

VLIW ARCHITECTURE:

https://www.geeksforgeeks.org/very-long-instruction-word-vliw-architecture/

PIPELINE- definition, different stages of pipeline, performance factors of pipeline.

https://www.geeksforgeeks.org/very-long-instruction-word-vliw-architecture/

different types of pipeline hazards and its solution:

https://www.geeksforgeeks.org/computer-organization-and-architecture-pipelining-set-2-
dependencies-and-data-hazard/

Example : Consider a 4 segment pipeline with stage delays (2 ns, 8 ns, 3 ns,
10 ns). Find the time taken to execute 100 tasks in the above pipeline.
Solution : As the above pipeline is a non-linear pipeline,
Tp = max(2, 8, 3, 10) = 10 ns
We know that ETpipeline = (k + n – 1) Tp = (4 + 100 – 1) 10 ns = 1030 ns

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