PSUD2 Technical Notes Duncan Amplification

PSU DESIGNER 2 SOFTWARE, AND ASSOCIATED DOCUMENTATION (INCLUDING THIS TECHNICAL NOTE) ARE
COPYRIGHT ©1998-2021, DUNCAN AMPLIFICATION. ANY TRADEMARKS USED HEREIN ARE ACKNOWLEDGED AS BEING
THE PROPERTY OF THEIR RESPECTIVE OWNERS.

THE SOFTWARE AND ASSOCIATED DOCUMENTATION ARE NOT GUARANTEED TO BE FREE FROM DEFECTS OR ERRORS,
NOR IS THE SOFTWARE GUARANTEED TO PERFORM IN ACCORDANCE WITH ANY SUPPLIED DOCUMENTATION. NO
LIABILITY CAN BE ACCEPTED FOR ANY LOSSES ARISING FROM THE USE OF THE SOFTWARE OR DOCUMENTATION OR
ANY SUPPLEMENTS OR CLARIFICATION TO THE DOCUMENTATION PROVIDED BY DUNCAN AMPLIFICATION,
HOWSOEVER RECEIVED.

USE OF THE SOFTWARE TO ASSIST IN THE DESIGN OF LIFE-CRITICAL SYSTEMS IS SPECIFICALLY PROHIBITED. LIFE
CRITICAL SYSTEMS INCLUDES, BUT IS NOT LIMITED TO, MEDICAL EQUIPMENT, SAFETY SYSTEMS, AEROSPACE AND
DEFENCE EQUIPMENT, AND WEAPONS SYSTEMS.

Title: PSU Designer 2 – Technical Notes

Document created: 2000-01-26
Revision level: 2 (2021-03-27)
Author: Duncan Munro ([email protected])
Support: Please direct any comments to the forum at https://groups.io/g/duncanampspsud

Contents
1 Introduction ............................................................................................................................................3
2 Models ....................................................................................................................................................3
2.1 Transformer ..........................................................................................................................................3
2.2 Rectifier ................................................................................................................................................4
2.2.1 Rectifier mode i ....................................................................................................................................4
2.2.2 Rectifier mode ii ...................................................................................................................................4
2.2.3 Rectifier mode iii...................................................................................................................................4
2.2.4 Rectifier mode iv ..................................................................................................................................4
2.2.5 Known deficiencies with the rectifier model .........................................................................................5
2.3 Resistor ................................................................................................................................................5
2.4 Capacitor ..............................................................................................................................................5
2.5 Inductor ................................................................................................................................................5
2.6 Current source .....................................................................................................................................5
3 Simulation ..............................................................................................................................................6
3.1 Block structure .....................................................................................................................................6
3.2 Block rules ............................................................................................................................................6
3.3 Simulation outline .................................................................................................................................7
3.3.1 Basis for simulation – timesteps ..........................................................................................................7
3.3.2 Delta limiting .........................................................................................................................................7
3.3.3 Timestep decimation ............................................................................................................................7
3.3.4 Decimation degeneration .....................................................................................................................7
3.4 Simulation process ...............................................................................................................................7
3.4.1 Step by step .........................................................................................................................................7
3.4.2 Calculating loop currents .....................................................................................................................8
3.4.3 Calculating V and I ..........................................................................................................................8
3.4.4 Calculating new terminal voltages .......................................................................................................8
3.5 Known issues with the simulation ........................................................................................................8
4 File formats ............................................................................................................................................9
4.1 Rectifier file TXT ...................................................................................................................................9
4.2 Rectifier files XML ................................................................................................................................9
4.3 PSU files ............................................................................................................................................10
4.3.1 PSU file general format ......................................................................................................................10
4.3.2 PSU file header format .......................................................................................................................10
4.3.3 PSU file block format..........................................................................................................................11
4.3.4 Data representations ..........................................................................................................................11
4.3.5 Example PSU file ...............................................................................................................................12
4.3.6 Shortcomings with binary format ........................................................................................................13
5 Revision history ...................................................................................................................................14

Reference: PSUD2-DOC-TECHNICAL-R2 Page 1 of 14

PSUD2 Technical Notes Duncan Amplification

Reference: PSUD2-DOC-TECHNICAL-R2 Page 2 of 14

PSUD2 Technical Notes Duncan Amplification

1 Introduction
PSUD2 is a software application allowing linear mains operated power supplies to be modelled prior to their
construction in order to assess:

(a) Component stress levels

(b) Performance data
(c) Stability under varying load

This purpose of this document is to detail the methods used to simulate power supply activity. There are two
major sections, Models and Simulation, which deal with component level activities and system level activities
respectively.

2 Models

2.1 Transformer

The transformer model consists of an AC voltage generator in series with a fixed resistance. The resistance
represents the source impedance presented by the following factors:

(a) Mains supply impedance

(b) Primary copper losses
(c) Secondary copper losses
(d) Coupling losses

In the interests of model simplicity and speed of simulation, no attempt is made to model core losses,
leakage inductance, or capacitive effects between windings.

The transformer model has an output terminal voltage at time t, of:

Vout t = Vsrc  sin( 2ft )  2

Where Vsrc is the RMS source voltage, and f is the mains frequency.

Reference: PSUD2-DOC-TECHNICAL-R2 Page 3 of 14

PSUD2 Technical Notes Duncan Amplification

2.2 Rectifier

The rectifier model is a simplistic static model which converts a voltage across its terminals into a current.
No attempt is made to model reactive elements such as capacitance or inductance, nor is there any attempt
to model charge storage effects.

There are four modes of operation for the rectifier model:

(i) Forward (conducting) voltage which users the rectifier mode i described in section
2.2.1 below, in series with a perfect resistor
(ii) Zero voltage
(iii) Normal reverse voltage
(iv) Reverse voltage causing arcing in a vacuum tube rectifier, or zener effect in a
solid state rectifier.

2.2.1 Rectifier mode i

In mode (i), the transfer function is:

I = a V b
Where a and b are factors, VFac and VLaw respectively.

This transfer element is modelled in series with a perfect resistor with the value DRes.

2.2.2 Rectifier mode ii

In mode (ii), the transfer function returns a current of zero to reflect the terminal voltage of zero.

2.2.3 Rectifier mode iii

In mode (iii), a nominal resistance value of 100M is used to model reverse leakage, resulting in:

V
I=
10 8
Later revisions of the software allow a range of reverse resistances to be simulated, these being selected
from the menu.

2.2.4 Rectifier mode iv

Mode (iv) represents the zener region of a solid state device, although can also simulate arcing in a vacuum
tube device. Neither of these circumstances should arise in an adequate power supply design, and their
addition to the model is used to prevent megavolt level results under these conditions.

If Vz is expressed as a negative zener voltage, then as an extension to mode (iii):

Vz V − Vz
I= +
108 Rz
In the above, Rz is the zener slope resistance. In the current implementation of the rectifier model, this is
specified as 10.

Reference: PSUD2-DOC-TECHNICAL-R2 Page 4 of 14

PSUD2 Technical Notes Duncan Amplification

2.2.5 Known deficiencies with the rectifier model

Aside from the inability to model capacitance, the rectifier model has the capability to produce numeric
underflows at very low positive values of V in mode (i). This risk of this is increased when high values of
Vlaw are used, although at the time of writing, no exceptions have been reported in practical use.

2.3 Resistor

Perfect resistors are used in the model where:

V
I=
R

2.4 Capacitor

Capacitors are modelled as a perfect capacitor in series with a perfect resistor. The resistor provides some
approximation of ESR, although inductive effects are clearly not modelled by this scheme. Given that the
intended use of the model is mains frequencies, this is not felt to be a serious shortcoming.

2.5 Inductor

Inductors are modelled as a perfect inductor in series with a perfect resistor. Variations of inductance with
current are not modelled. It is intended that this will be addressed in subsequent releases of the software if
there is sufficient demand for it.

2.6 Current source

Constant current sources are used to load the power supply, although there is one deviation from a perfect
current source. If the terminal voltage goes negative, the current is reduced to zero.

Reference: PSUD2-DOC-TECHNICAL-R2 Page 5 of 14

PSUD2 Technical Notes Duncan Amplification

3 Simulation

3.1 Block structure

The concept of the simulation system is a contiguous chain of linked blocks forming a network. Each block
assumes one of the following styles:

(a) A voltage source (transformer/rectifier etc.)

(b) A filter
(c) A final load

Each block is a “black box”, with voltage sources and final loads being two terminal devices, and each filter
being a four terminal device. It is not necessary for any block to be aware of the contents of an adjacent
block.

I0 I1 I2

I0 I1 I2

Source Filter Filter Load

Note that each block has a current loop between itself and each adjacent block. Blocks may request voltage
information from adjacent blocks, and in certain circumstances, may set the terminal voltage of adjacent
blocks on completion of each simulation step.

3.2 Block rules

There are a number of rules which apply to the blocks, in order for the simulation to operate correctly:

(a) At least two blocks must be present in the system

(b) The first block must always be a voltage source
(c) The final block must always be a final load

Between the voltage source and the final load, there may be zero or more filter blocks 1. The filter blocks can
be arranged in any desired order.

1Note that a current tap is defined as a “filter”. For practical purposes, it will be a two terminal device,
although the simulation will consider it as a four terminal filter block.

Reference: PSUD2-DOC-TECHNICAL-R2 Page 6 of 14

PSUD2 Technical Notes Duncan Amplification

3.3 Simulation outline

3.3.1 Basis for simulation – timesteps

The simulation consists of a sequence of discrete time step intervals, which are continuous in time. Blocks
containing elements of a reactive nature will change their properties in relation to time, such as a capacitor
charging up.

At any point in time, the simulation only needs to know the results of the previous step which we will refer to
as T-1. Clearly, T is the time now, and T – T-1 is the time step interval.

3.3.2 Delta limiting

The results provided by the simulation at T-1 are used to predict the results at T, although there may be
instances where this method is unsatisfactory. As an example, if T -1 suggests a large current flowing through
a loop, with a small value capacitor in this loop, the result will be to increase the voltage on the capacitor by
an amount which would greatly exceed that found in a real world situation.

The solution for this is to provide V limiting for capacitors, and I limiting for inductors. Both V and I are
arbitary amounts which are currently defined as 1% of the generator voltage and 1% of the anticipated total
output current respectively.

3.3.3 Timestep decimation

In circumstances where V/I limits have been exceeded, the simulation step is decimated in time into four
equal sub-simulations in order to bring the V/I calculations within sensible limits. Note that the sub-
simulations may also be decimated in time recursively, until a stable solution is found.

3.3.4 Decimation degeneration

Under some situations, the decimation process may continue to degenerate to repeatedly smaller timestep
values. As the simulation time is proportional to the timestep, this situation (if left unchecked) could result in
excessive simulation times, stack faults, or the system giving the appearance of being locked. A minimum
timestep value is applied to the decimation process, and an exception will be generated should the timestep
fall below this minimum threshold.

3.4 Simulation process

The process starts by resetting the time to 0.0, and resetting the values of all elements within the blocks,
inductors have no current, and capacitors have no voltage.

3.4.1 Step by step

When cleared, the zeroed results become the T-1 state. The following steps are then executed:

(a) Working through each block, the loop currents are calculated. This information
generates I0, I1, I2… This information is easily obtained, as each block provides an
input generator voltage/resistance, and an output generator voltage/resistance. In the
case of constant current loads, and the input to a block containing an inductor2, the loop
current will be the value of the load itself, or the current in the inductor at T -1
respectively.

2 Constant current loads and inductive inputs will be referred to as “CC Input” blocks.

Reference: PSUD2-DOC-TECHNICAL-R2 Page 7 of 14

PSUD2 Technical Notes Duncan Amplification

(b) The values for V and I are calculated (if required) for each block. Should these
exceed the V/I limits, then the process starting at (a) is executed for 4 smaller equal
time steps are described in section 3.3.2.
(c) Assuming that V/I fall within prescribed limits, the values are applied to the elements
within each block, along with the new loop currents for state T.
(d) The new terminal voltages are calculated for each block.
(e) This creates state T, reporting (if required) is carried out.
(f) State T-1  T.
(g) If the complete simulation time has not been reached, the simulation goes back to (a)

This completes the simulation cycle, with some of the finer details being discussed in the following sections.

3.4.2 Calculating loop currents

Loop currents are calculated between blocks [a] and [b] by one of two methods:

(a) If block [b] is a CC input device (constant current load or inductor), then block [b] is queried to find the
terminal current at T-1. This sets the output current of [a].
(b) Otherwise… The generator voltage equivalent of [a] and [b] are queried to give E[a] and E[b]. Similarly,
the blocks can be queried for their equivalent generator resistance to give R[a] and R[b]. The loop
current is calculated as (E[a]+E[b]) / (R[a]+R[b]).

3.4.3 Calculating V and I

Not all blocks contain reactive components – this step will only apply to those that do. For a capacitor:

I t
V =
C
Where I is the current flowing into the capacitor, t is the timestep, and C is the value of the capacitor. For
inductors:

V t
I =
L
Where V is the voltage across the inductor, t is the timestep, and L is the value of the inductor. Note that
these calculations may arrive at erroneous results as discussed in section 3.3.2.

3.4.4 Calculating new terminal voltages

A new set of terminal voltages to represent the T state is calculated by each block. Clearly, the output
terminal of one block should be at the same potential as the input terminal of the next block.

This is calculated from left to right with each block calculating its own output voltage, and setting the input
voltage of the next block.

3.5 Known issues with the simulation

Some of the shortcuts used for the calculations result in errors, in some cases of 2-3%. This may be
significant in terms of the design used and cannot be resolved with the calculation schemes used in PSUD2.
A slower, but more accurate, method of calculation is used in PSUD3 which resolves this issue.

Reference: PSUD2-DOC-TECHNICAL-R2 Page 8 of 14

PSUD2 Technical Notes Duncan Amplification

4 File formats
There are two types of stored data, rectifiers and power supply designs. The initial design of PSUD2 used a
single text file to store all the rectifier parameters and this format is described in section 4.1. From build
2.20.0 (released 23rd February 2020) the rectifiers were stored as individual XML format files, this format
being described in section 4.2. This made it easier to share individual rectifier models.

4.1 Rectifier file TXT

From the earliest release of the software, the rectifier parameters were stored in a rectifiers.txt file
which resided in the program files area. From build 2.10.0 (released 22nd November 2019) the rectifiers.txt
file resided in the users application data area to comply with the Windows 10 security model.

The general format of the file is an ASCII encoded text file with zero or more lines, each of which can contain
one of the following:

• Blank
• A comment
• A rectifier definition

Blank is self-explanatory.

A comment line is a line where the first character is an asterisk character followed by optional text.

Rectifier definitions are a series of 8 comma separated values which contain the following information:

• Name of the rectifier as a text string. Commas are not allowed in the text
• Type of the rectifier. Allowed values are SS for Solid State and VT for Vacuum Tube
• DRes parameter as described in section 2.2.1
• VLaw parameter as described in section 2.2.1
• VFac parameter as described in section 2.2.1
• VPIV the peak inverse voltage which will cause the Zener action described in section 2.2.4
• IPks the peak surge current in Amps (single cycle) specified by the device data sheet
• IPkr the peak repetitive current in Amps specified by the device data sheet

A typical comment and rectifier definition line could look like:

*Name Type DRes VLaw VFac VPIV IPks IPkr

1N4001, SS, 0.042, 20, 9.353, 50, 30, 6

Note that the format of floating-point numbers uses a period as a decimal separator. Many countries use the
comma as a decimal separator, however PSUD stores all floating-point numbers with the period separator so
that the files can be shared between different countries.

4.2 Rectifier files XML

From build 74 (version 2.20.0) released 23rd February 2020, the rectifiers are no longer presented in a single
text file. Each of the rectifiers is in an XML format with each file having the extension .rect to distinguish it
as a rectifier file. Files are encoded in a text format using UTF-8 representations.

The contents of a typical rectifier file is:

<?xml version="1.0" encoding="UTF-8"?>

<rectifier>
<name>1N4001</name>
<description>1N4001 imported from PSUD2</description>
<version>211</version>

Reference: PSUD2-DOC-TECHNICAL-R2 Page 9 of 14

PSUD2 Technical Notes Duncan Amplification

<creationdate>2019-11-23 17:30:32</creationdate>
<type>SS</type>
<vlaw>20</vlaw>
<vfac>9.353</vfac>
<dres>0.042</dres>
<vpiv>50</vpiv>
<ipks>30</ipks>
<ipkr>6</ipkr>
</rectifier>

The name may not include comma or angle bracket characters. It is possible to have files with the same
rectifier name, for example 1n914.rect and 1n4148.rect both having the content:

<rectifier>
<name>1N4148</name>
:

In this instance the latest file loaded will take priority, there is no guarantee which file will be the latest loaded
and as such, this practice is best avoided.

As with the rectifiers.txt file, the representation of floating point numbers uses the period as the decimal
separator.

4.3 PSU files

The PSU files used for PSUD up to version 2.x use the file extension .psu and are in a binary format. It is
anticipated that the files for PSUD version 3 and onwards will use the extension .psud and will have an
XML format in the same way as the newer rectifiers described in section 4.2.

4.3.1 PSU file general format

The binary format of the PSU files is a sequence of data objects in the format:

Header Block+

4.3.2 PSU file header format

The header contains two items:

Version_String Number_Of_Blocks

Version_String contains a string showing the version of the software which was used to generate the file.
Currently, there is only one valid entry for the version which is PSUD2-00 any other entry is deemed invalid
and will not be loaded by PSUD version 2.x. The method for storing the string is described in section 4.3.4

Following the header is Block+ to denote “one or more instances of Block”.

Reference: PSUD2-DOC-TECHNICAL-R2 Page 10 of 14

PSUD2 Technical Notes Duncan Amplification

4.3.3 PSU file block format

The entry Number_Of_Blocks in the header will signify the total number of blocks which have been stored.
Each block content will vary depending on the block type, however all will start off with an identifier string
which will be one of the Identifiers in the following table:

Identifier Type Following Contents

TBlockFilterC Filter, C Two floating point values for capacitor value,

ESR value

TBlockFilterLC Filter, LC Four floating point values for inductor value,

inductor resistance, capacitor value, capacitor
ESR

TBlockFilterRC Filter, RC Three floating point values for resistor value,

capacitor value, capacitor ESR

TBlockFilterT Current tap Three floating point values for initial current,
later current (for stepped values), step time in
seconds

TBlockLoadI Load, constant current Floating point value for load current

TBlockLoadR Load, resistive Floating point value for load resistance

TBlockSourceBRS3 Source, bridge rectifier, solid state Floating point value for RMS voltage, floating
point value for source resistance, text string
for rectifier name

TBlockSourceBRT Source, bridge rectifier, vacuum Ditto

tube

TBlockSourceFWS Source, full wave, solid state Ditto

TBlockSourceFWT Source, full wave, vacuum tube Ditto

TBlockSourceHWS Source, half wave, solid state Ditto

TBlockSourceHWT Source, half wave, vacuum tube Ditto

TBlockSourceVDS Source, voltage doubler, solid Ditto

state

TBlockSourceVDT Source, voltage double, vacuum Ditto

tube

4.3.4 Data representations

Each datatype is represented differently and is set by the development library for FPC which is used to read
and write streams of data. There is a prefix byte which shows the type of data, followed by the data itself.

The table of bytes used within the software are as follows:

Prefix Byte Contents Example

02 Short unsigned integer contained 02 0A

in 8 bits The decimal integer 10

3 Note that TBlockSource..T and TBlockSource..S are equivalent, the only difference being the on-screen
representation as a vacuum tube or solid-state rectifier respectively.

Reference: PSUD2-DOC-TECHNICAL-R2 Page 11 of 14

PSUD2 Technical Notes Duncan Amplification

05 Extended floating point value 10 05 00 00 00 00 00 00 80 A6 07 40

bytes in little-endian format (most The extended float value 333.0
significant byte last)

06 A short string (255 characters or 06 06 31 4E 34 30 30 37

less), represented by a length byte The text “1N4007”
followed by the bytes in the string.
There is no zero terminator

4.3.5 Example PSU file

The following is a hex dump of the default PSU file that comes with the software, this is the PSU design that
it loads on startup.

Offset(h) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
00000000 06 08 50 53 55 44 32 2D 30 30 02 03 06 0F 54 42 ..PSUD2-00....TB
00000010 6C 6F 63 6B 53 6F 75 72 63 65 42 52 53 05 00 00 lockSourceBRS...
00000020 00 00 00 00 80 A6 07 40 05 00 00 00 00 00 00 00 ....€¦.@........
00000030 F8 03 40 06 06 31 4E 34 30 30 37 06 0D 54 42 6C ø[email protected]
00000040 6F 63 6B 46 69 6C 74 65 72 43 05 00 58 82 C5 E1 ockFilterC..X‚Åá
00000050 CC AF E6 F2 3F 05 00 00 00 00 00 00 00 80 00 40 ̯æò?........€.@
00000060 06 0B 54 42 6C 6F 63 6B 4C 6F 61 64 52 05 00 00 ..TBlockLoadR...
00000070 00 00 00 00 40 9C 0B 40 ....@œ.@

Taking the file apart, here is the description of each element section by section:

Offset Length Bytes Content Description

0000 000A 06 08 50 53 55 44 String: “PSUD2-00” Header string
32 2D 30 30

000A 0002 02 03 Short integer: 3 Number of blocks

000C 0011 06 0F 54 42 6C 6F String: Block 1 type is a bridge
63 6B 53 6F 75 72 “TBlockSourceBRS” rectifier
63 65 42 52 53

001D 000B 05 00 00 00 00 00 Float: 333.0 Block 1: RMS voltage of

00 80 A6 07 40 the transformer
0028 000B 05 00 00 00 00 00 Float: 31.0 Block 1: Source
00 00 F8 03 40 impedance of the
transformer
0033 0008 06 06 31 4E 34 30 String: “1N4007” Block1: Rectifier model
30 37 used for the bridge
003B 000F 06 0D 54 42 6C 6F String: “TBlockFilterC” Block 2 type is a
63 6B 46 69 6C 74 capacitor filter
65 72 43

004A 000B 05 00 58 82 C5 E1 Float: 2.2 E-04 Block 2: Capacitor value

AF E6 F2 3F

0055 000B 05 00 00 00 00 00 Float: 2.0 Block 2: Capacitor ESR

00 00 80 00 40

0060 000D 06 0B 54 42 6C 6F String: “TBlockLoadR” Block 3 type is a resistive

63 6B 4C 6F 61 64 load
52

006D 000B 05 00 00 00 00 00 Float: 5000.0 Block 3: Load resistance

Reference: PSUD2-DOC-TECHNICAL-R2 Page 12 of 14

PSUD2 Technical Notes Duncan Amplification

00 40 9C 0B 40

4.3.6 Shortcomings with binary format

Developed in 1998, the format does not lend itself well to readability or extensibility. The known
shortcomings are:

1. The binary file format is very much specific to the development environment
2. There is only one type of rectifier allowed in a bridge. This will prevent, for example, hybrid bridges
that combine vacuum tube and solid state rectifiers

As stated previously, future versions of the software will use a human-readable XML format to address the
issues listed above.

Reference: PSUD2-DOC-TECHNICAL-R2 Page 13 of 14

PSUD2 Technical Notes Duncan Amplification

5 Revision history
Rev # Date By Reason
0 2000-01-26 DM Initial document release
1 2017-02-09 DM Tidy up
2 2021-03-27 DM Added file formats for PSUD2

Reference: PSUD2-DOC-TECHNICAL-R2 Page 14 of 14