Computer Memory System Overview & Characteristics of Memory Systems

1. Which of the following is the fastest type of memory in a typical computer system?
A) RAM
B) ROM
C) Cache
D) Hard disk
2. What is the primary characteristic that distinguishes volatile from non-volatile
memory?
A) Speed
B) Data retention without power
C) Cost
D) Storage capacity
3. In the memory hierarchy, which type of memory typically has the highest access
time?
A) Registers
B) Cache
C) RAM
D) Secondary storage
4. Which of the following is NOT a characteristic of a good memory system?
A) Low access time
B) High cost per bit
C) Large storage capacity
D) Reliability

Memory Hierarchy

5. What is the main purpose of the memory hierarchy in computer systems?

A) To reduce storage size
B) To balance speed, cost, and capacity
C) To increase complexity
D) To improve power efficiency
6. In a typical memory hierarchy, which level is directly accessed by the CPU?
A) RAM
B) Cache
C) Hard drive
D) Registers
7. Which of the following memories is at the lowest level of the memory hierarchy?
A) Secondary storage
B) L3 cache
C) RAM
D) Registers

Cache Memory Principles

8. What is the main purpose of cache memory in a computer system?

A) To store large amounts of data
B) To act as a buffer between CPU and RAM
C) To permanently store data
D) To execute programs faster
9. Which of the following is a key characteristic of cache memory?
A) High latency
B) Small size
 C) Low cost
D) Slow access speed
10. What principle is cache memory based on?
A) Sequential access
B) Locality of reference
C) Random access
D) Binary search

Pentium 4 Cache Organization & Cache Design

11. How many levels of cache are typically present in a Pentium 4 processor?
A) 1
B) 2
C) 3
D) 4
12. What type of cache organization is used in the Pentium 4 processor?
A) Fully associative
B) Direct-mapped
C) Set-associative
D) Multi-level associative
13. Which of the following is NOT a key element of cache design?
A) Cache size
B) Mapping function
C) Instruction set architecture
D) Write policy

Cache Addresses, Size, and Mapping Functions

14. Which factor directly affects the hit rate in cache memory?
A) Cache address length
B) Cache size
C) Line size
D) Write policy
15. What is the function of a mapping technique in cache design?
A) To determine how data is stored in the cache
B) To optimize cache power consumption
C) To increase cache capacity
D) To improve CPU speed
16. What is a typical mapping function used in cache memory?
A) Random mapping
B) Associative mapping
C) Static mapping
D) Matrix mapping

Replacement Algorithms, Write Policy, and Line Size

17. Which of the following is a common cache replacement algorithm?

A) Least Recently Used (LRU)
B) FIFO (First In, First Out)
C) Random replacement
D) All of the above
18. What does a cache write-through policy ensure?
A) Data is written to both cache and main memory
 B) Data is written only to the cache
C) Data is discarded after writing
D) Data is written at a later time
19. How does increasing the line size of a cache affect performance?
A) It decreases miss penalty
B) It increases hit rate
C) It decreases hit rate
D) It increases the number of replacement algorithms

Number of Caches

20. What is the main purpose of having multiple levels of cache (L1, L2, L3) in modern
processors?
A) To reduce cost
B) To balance speed and size
C) To eliminate the need for RAM
D) To increase power consumption

ExternalMemory

1. What is the primary function of a magnetic disk?

A) Store data
B) Execute programs
C) Process graphics
D) Control hardware
2. Which mechanism is used to read data from a magnetic disk?
A) Optical laser
B) Magnetic head
C) Electric current
D) Mechanical arm
3. What is the typical data organization format on a magnetic disk?
A) Files and folders
B) Tracks and sectors
C) Bytes and bits
D) Pages and blocks
4. How are data sectors on a magnetic disk typically formatted?
A) Using a laser
B) With magnetic fields
C) Through thermal transfer
D) By mechanical engraving
5. Which of the following is NOT a physical characteristic of magnetic disks?
A) Platters
B) Spindle speed
C) Transistors
D) Read/write heads
6. What is the purpose of the disk performance parameter "seek time"?
A) Time taken to read data
B) Time taken to move the read/write head
C) Time to format the disk
D) Time to store data
7. What does SSD stand for?
A) Solid State Drive
B) Storage System Device
 C) Sequential Data Disk
D) Secondary Storage Drive
8. Which is a major advantage of SSDs over HDDs?
A) Larger physical size
B) Slower access times
C) Higher speed
D) More mechanical parts
9. What type of memory is primarily used in SSDs?
A) Magnetic
B) Optical
C) Flash
D) RAM
10. In an SSD, how is data organized?
A) Tracks and sectors
B) Cells and pages
C) Layers and disks
D) Blocks and clusters
11. Which of the following is a practical issue associated with SSDs?
A) Susceptibility to magnetic fields
B) Limited write endurance
C) Large physical size
D) High power consumption
12. What is a common use for magnetic tape?
A) Real-time processing
B) Long-term archival storage
C) High-speed data retrieval
D) Running operating systems
13. How does magnetic tape store data?
A) Using laser etching
B) By magnetizing particles on a surface
C) Through electrical charges
D) Via optical discs
14. Which of the following is a disadvantage of using magnetic disks?
A) Faster than SSDs
B) Susceptible to physical damage
C) No moving parts
D) Lower cost per GB
15. What is the typical lifespan of an SSD compared to an HDD?
A) Shorter
B) About the same
C) Longer
D) Not measurable
16. Which performance parameter describes the amount of data that can be
read/written per second?
A) Latency
B) Throughput
C) Seek time
D) RPM
17. What is one of the main components of a magnetic disk drive?
A) Solid state chip
B) Optical lens
C) Platter
D) Transistor
18. How does SSD performance change with increased data usage?
A) It improves over time
B) It stays the same
C) It can degrade
D) It doubles
19. Which of the following storage types is typically slower?
A) SSD
B) HDD
C) Flash memory
D) RAM
20. What is a common feature of both magnetic disks and SSDs?
A) They both use mechanical parts
B) They both store data digitally
C) They both require frequent defragmentation
D) They both are susceptible to magnetic interference
21. Physical memory is divided into sets of finite size called:
A) Pages
B) Vectors
C) Blocks
D) Frames
22. During the transfer of data between the processor and memory, we use:
A) TLB
B) Cache
C) Buffers
D) Registers

23. If a system is a 64-bit machine, the length of each word will be:
A) 12 bytes
B) 16 bytes
C) 8 bytes
D) 4 bytes
24. The type of memory assignment used in Intel processors is:
A) Medium Endian
B) Big Endian
C) None of the mentioned
D) Little Endian

25. A 24-bit address generates an address space of:

A) 16,777,216 locations
B) 1024 locations
C) 2^48 locations
D) 4096 locations
26. The collection of the above-mentioned entities where data is stored is called:
A) Byte
B) Set
C) Block
D) Word
27. The method used to map logical addresses of variable length onto physical memory
is:
A) Paging with segmentation
B) Overlays
C) Segmentation
D) Paging
28. When using the Big Endian assignment to store a number, the sign bit of the
number is stored in:
A) None of the mentioned
B) The lower order byte of the word
C) The higher order byte of the word
D) Can't say

29. To get the physical address from the logical address generated by the CPU, we use:
A) MAR
B) Overlays
C) MMU
D) TLB
30. The smallest entity of memory is called:
A) Instance
B) Unit
C) Cell
D) Block
31. Which of the following techniques is used to effectively utilize main memory?
A) Dynamic loading
B) Both Dynamic linking and loading
C) Dynamic linking
D) Address binding
32. When the instruction Add #%01011101,R1 is executed, what happens?
A) The numerical value represented by the binary value is added to the value of R1
B) None of the mentioned
C) The binary addition between the operands takes place
D) The addition doesn't take place, whereas this is similar to a MOV instruction
33. The technique used to store programs larger than the memory is:
A) Buffers
B) Extension registers
C) Overlays
D) Both Extension registers and Buffers
34. When generating physical addresses from a logical address, the offset is stored in:
A) Translation look-aside buffer
B) Page table
C) Shift register
D) Relocation register
35. The unit which acts as an intermediate agent between memory and backing store to
reduce process time is:
A) TLB's
B) Page tables
C) Registers
D) Cache
36. Complete the following analogy: Registers are to RAM as Cache is to:
A) TLB
B) Overlays
C) Page Table
D) System stacks
37. The BOOT sector files of the system are stored in:
A) Hard disk
B) ROM
C) RAM
D) Fast solid-state chips in the motherboard
38. If we want to perform memory or arithmetic operations on data in Hexadecimal
mode, we use which symbol before the operand?
A) *
B) ~
C) !
D) $
39. The transfer of large chunks of data without the direct involvement of the processor
is done by:
A) Arbitrator
B) DMA controller
C) None of the mentioned
D) User system programs
40. Does the Load instruction perform the following operation(s)?
A) Loads the contents of a disc onto a memory location
B) Loads the contents of a location onto the accumulators
C) Load the contents of the PCB onto the register
D) None of the mentioned
41. In a system with 32 registers, the register ID is __________ long.
A) 8 bits
B) 16 bits
C) 5 bits
D) 6 bits
42. The instruction Add R1, R2, R3 in RTN (Register Transfer Notation) is:
A) R3 ← [R1] + [R2] + [R3]
B) R3 = R1 + R2 + R3
C) R3 = [R1] + [R2]
D) R3 ← [R1] + [R2]
Answer: D) R3 ← [R1] + [R2]
43. The two phases of executing an instruction are __________.
A) Instruction fetch and instruction execution
B) Instruction fetch and instruction processing
C) Instruction decoding and storage
D) Instruction execution and storage
44. The Instruction fetch phase ends with __________.
A) Placing the data from the address in MAR into MDR
B) Decoding the data in MDR and placing it in IR
C) Completing the execution of the data and placing its storage address into MAR
D) Placing the address of the data into MAR
45. RTN stands for __________.
A) Register Transfer Notation
B) Regular Transmission Notation
C) Regular Transfer Notation
D) Register Transmission Notation
46. Can you perform an addition on three operands simultaneously in ALU using the
Add instruction?
A) Not possible using Add, we have to use AddSetCC
B) None of the mentioned
C) Yes
D) Not permitted
47. While using the iterative construct (Branching) in execution, __________ instruction
is used to check the condition.
A) TestCondn
B) TestAndSet
 C) None of the mentioned
D) Branch
48. The instruction Add Loc, R1 in RTN is __________.
A) Not possible to write in RTN
B) R1 = Loc + R1
C) AddSetCC Loc + R1
D) R1 ← [Loc] + [R1]
49. The condition flag Z is set to 1 to indicate __________.
A) The operation has resulted in an error
B) There is no empty register available
C) The result is zero
D) The operation requires an interrupt call
50. When using Branching, the usual sequencing of the PC is altered. A new instruction
is loaded which is called __________.
A) Branch target
B) Forward target
C) Loop target
D) Jump instruction
51. The advantage of I/O mapped devices over memory-mapped devices is
___________.
A) The devices connected using I/O mapping have a bigger buffer space
B) No advantage as such
C) The former offers faster transfer of data
D) The devices have to deal with fewer address lines
52. The method which offers higher speeds of I/O transfers is ___________.
A) Interrupts
B) Memory mapping
C) Program-controlled I/O
D) DMA
53. The system is notified of a read or write operation by ___________.
A) Appending an extra bit of the address
B) Enabling the read or write bits of the devices
C) Sending a special signal along the BUS
D) Raising an appropriate interrupt signal
54. The method of synchronizing the processor with the I/O device in which the device
sends a signal when it is ready is:
A) Exceptions
B) Interrupts
C) Signal handling
D) DMA
55. In memory-mapped I/O ____________.
A) The I/O devices have a separate address space
B) The I/O devices and the memory share the same address space
C) A part of the memory is specifically set aside for the I/O operation
D) The memory and I/O devices have an associated address space
56. The process wherein the processor constantly checks the status flags is called
___________.
A) Echoing
B) Reviewing
C) Inspection
D) Polling
57. In Intel's IA-32 architecture, there is a separate 16-bit address space for the I/O
devices.
 A) True
B) False
58. The method of accessing the I/O devices by repeatedly checking the status flags is
___________.
A) None of the mentioned
B) Program-controlled I/O
C) I/O mapped
D) Memory-mapped I/O
59. To overcome the lag in the operating speeds of the I/O device and the processor, we
use ___________.
A) Buffer spaces
B) Exceptions
C) Interrupt signals
D) Status flags
60. The usual BUS structure used to connect the I/O devices is ___________.
A) Node to Node BUS structure
B) Single BUS structure
C) Star BUS structure
D) Multiple BUS structure
61. The 8085 microprocessor responds to the presence of an interrupt ___________.
A) As soon as the trap pin becomes 'LOW'
B) By checking the trap pin for 'high' status at the end of each instruction fetch
C) By checking the trap pin for 'high' status at the end of the execution of each instruction
D) By checking the trap pin for 'high' status at regular intervals
62. A single interrupt line can be used to service n different devices.
A) True
B) False
63. The resistor which is attached to the service line is called _____
A) Line resistor
B) Push-down resistor
C) Pull-up resistor
D) Break down resistor
64. Interrupts form an important part of _____ systems.
A) Batch processing
B) Real-time processing
C) Multitasking
D) Multi-user
65. The interrupt-request line is a part of the ___________.
A) Control line
B) Data line
C) Address line
D) None of the mentioned
66. ______ type circuits are generally used for interrupt service lines.
i) open-collector
ii) open-drain
iii) XOR
iv) XNOR
A) i, ii
B) ii
C) ii, iii
D) ii, iv
67. The signal sent to the device from the processor to the device after receiving an
interrupt is ___________.
A) Return signal
 B) Permission signal
C) Service signal
D) Interrupt-acknowledge
68. An interrupt that can be temporarily ignored is ___________.
A) High priority interrupt
B) Vectored interrupt
C) Non-maskable interrupt
D) Maskable interrupt
69. The return address from the interrupt-service routine is stored on the ___________.
A) Memory
B) System heap
C) Processor stack
D) Processor register
70. CPU has two modes: privileged and non-privileged. In order to change the mode
from privileged to non-privileged:
A) A non-privileged instruction (which does not generate an interrupt) is needed
B) A hardware interrupt is needed
C) A software interrupt is needed
D) Either hardware or software interrupt is needed
71. The time between the reception of an interrupt and its service is ______.
A) Switching time
B) Interrupt delay
C) Interrupt latency
D) Cycle time
72. When the process is returned after an interrupt service, ______ should be loaded
again.
i) Register contents
ii) Condition codes
iii) Stack contents
iv) Return addresses
A) i, ii
B) i, iv
C) ii, iii, and iv
D) iii, iv
73. How can the processor ignore other interrupts when it is servicing one
___________?
A) By disabling the devices from sending the interrupts
B) All of the mentioned
C) By turning off the interrupt request line
D) By using edge-triggered request lines
74. Which interrupt is unmaskable?
A) RST 5.5
B) TRAP
C) RST 7.5
D) Both RST 5.5 and 7.5
75. From amongst the following given scenarios, determine the right one to justify
interrupt mode of data transfer.
i) Bulk transfer of several kilobytes
ii) Moderately large data transfer of more than 1kb
iii) Short events like mouse action
iv) Keyboard inputs
A) ii
B) iv
 C) i and ii
D) i, ii, and iv
76. IDE stands for _________.
A) Integrated Device Electronics
B) International Device Encoding
C) International Decoder Encoder
D) Industrial Decoder Electronics
77. What is the full form of ISA?
A) Industry Standard Architecture
B) None of the mentioned
C) International American Standard
D) International Standard Architecture
78. The system developed by IBM with ISA architecture is ______.
A) None of the mentioned
B) SPARC
C) SUN-SPARC
D) PC-AT
79. SCSI stands for ___________.
A) Signal Coding System Interface
B) Signal Computer System Interface
C) Small Computer System Interface
D) Small Coding System Interface
80. What is the full form of ANSI?
A) American National Standards Institute
B) Asian National Standards Institute
C) Architectural National Standards Institute
D) None of the mentioned
81. IDE disk is connected to the PCI BUS using ______ interface.
A) ISA
B) IEEE
C) ANSI
D) ISO
82. ________ is an extension of the processor BUS.
A) None of the mentioned
B) PCI BUS
C) USB
D) SCSI BUS
83. ______ is used as an intermediate to extend the processor BUS.
A) Connector
B) Gateway
C) Bridge
D) Router
84. ISO stands for __________.
A) Industrial Standards Organisation
B) International Software Organisation
C) Industrial Software Organisation
D) International Standards Organisation
85. The video devices are connected to ______ BUS.
A) SCSI
B) PCI
C) HDMI
D) USB
86. Which is fed into the BUS first by the initiator?
A) Address, Commands or controls
 B) Data
C) Commands or controls
D) Address
87. The time for which the data is to be on the BUS is affected by __________.
A) Memory access time
B) Propagation delay of the circuit
C) Setup time of the device
D) Propagation delay of the circuit & Setup time of the device
88. The classification of BUSes into synchronous and asynchronous is based on
__________.
A) The devices connected to them
B) The Timing of data transfers
C) The type of data transfer
D) None of the mentioned
89. The device which starts data transfer is called __________.
A) Initiator
B) Distributor
C) Transactor
D) Master
90. In synchronous BUS, the devices get the timing signals from __________.
A) None of the mentioned
B) A common clock line
C) Timing generator in the device
D) Timing signals are not used at all
91. The delays caused in the switching of the timing signals is due to __________.
A) Processor delay
B) Memory access time
C) WMFC
D) Propagation delay
92. The device which interacts with the initiator is __________.
A) Slave
B) Master
C) Friend
D) Responder
93. _____________ signal is used as an acknowledgment signal by the slave in Multiple
cycle transfers.
A) Slave ready signal
B) Master ready signal
C) Ack signal
D) Slave received signal
94. The primary function of the BUS is __________.
A) To connect the various devices to the CPU
B) All of the mentioned
C) To facilitate data transfer between various devices
D) To provide a path for communication between the processor and other devices
95. The Master strobes the slave at the end of each clock cycle in Synchronous BUS.
A) True
B) False
96. The meter in and out lines are used for __________.
A) Measure the CPU usage
B) None of the mentioned
C) Monitoring the usage of devices
D) Monitoring the amount of data transferred
97. The master indicates that the address is loaded onto the BUS, by activating _____
signal.
A) WMFC
B) INTR
C) SSYN
D) MSYN
98. The transmission on the asynchronous BUS is also called _____.
A) Bulk transfer
B) Hand-Shake transmission
C) Switch mode transmission
D) Variable transfer
99. Asynchronous mode of transmission is suitable for systems with multiple peripheral
devices.
A) False
B) True
100. The BUS that allows I/O, memory, and Processor to coexist is _______.
A) Attributed BUS
B) External BUS
C) Processor BUS
D) Backplane BUS
101. MRDC stands for _______.
A) Memory Ready Command
B) None of the mentioned
C) Memory Re-direct Command
D) Memory Read Enable
102. The devices with variable speeds are usually connected using asynchronous
BUS.
A) False
B) True
103. The MSYN signal is initiated __________.
A) Soon after the address and commands are loaded
B) Soon after the decoding of the address
C) None of the mentioned
D) After the slave gets the commands
104. The asynchronous BUS mode of transmission allows for a faster mode of
data transfer.
A) False
B) True
105. In IBM's S360/370 systems, _____ lines are used to select the I/O devices.
A) Connect
B) Peripheral
C) Search
D) SCAN in and out
106. The PCI follows a set of standards primarily used in _____ PC's.
A) SUN
B) Intel
C) IBM
D) Motorola
107. The key feature of the PCI BUS is _________.
A) None of the mentioned
B) Low-cost connectivity
C) Plug and Play capability
D) Expansion of Bandwidth
108. Signals whose names end in ____ are asserted in the low voltage state.
A) !
B) #
C) $
D) *
109. The ______ is the BUS used in Macintosh PC's.
A) EISA
B) NuBUS
C) None of the mentioned
D) PCI
110. The master is also called as _____ in PCI terminology.
A) Chief
B) Commander
C) Initiator
D) Starter
111. When transferring data over the PCI BUS, the master has to hold the
address until the completion of the transfer to the slave.
A) True
B) False
112. PCI stands for _______.
A) Processor Computer Interconnect
B) Peripheral Component Interconnect
C) Peripheral Computer Internet
D) Processor Cable Interconnect
113. The PCI BUS supports _____ address space/s.
A) I/O
B) Memory
C) All of the mentioned
D) Configuration
114. _____ provides a separate physical connection to the memory.
A) PCI BUS
B) PCI bridge
C) PCI interface
D) Switch circuit
115. ______ address space gives the PCI its plug-and-play capability.
A) Configuration
B) Memory
C) I/O
D) All of the mentioned
116. The SEL signal signifies _________.
A) That the target is being selected
B) The initiator is selected
C) None of the mentioned
D) The device for BUS control is selected
117. _____ is used to reset all the device controls to their startup state.
A) RST
B) None of the mentioned
C) SRT
D) ATN
118. In a data transfer operation involving SCSI BUS, the control is with ______.
A) Initiator
B) SCSI controller
C) Target Controller
D) Target
119. The SCSI BUS uses ______ arbitration.
A) Centralised
B) Hybrid
C) Distributed
D) Daisy chain
120. The key features of the SCSI BUS are _________.
A) The cost-effective connective media
B) The ability to overlap data transfer requests
C) None of the mentioned
D) The highly efficient data transmission
121. The MSG signal is used _________.
A) To send a message to the target
B) To tell that the information being sent is a message
C) To receive a message from the mailbox
D) None of the mentioned
122. The BSY signal signifies _________.
A) The controller is busy
B) The BUS is busy
C) The Initiator is busy
D) The Target is Busy
123. In SCSI transfers, the processor is not aware of the data being transferred.
A) False
B) True
124. ________ signal is asserted when the initiator wishes to send a message to the
target.
A) MSG
B) ATN
C) SMS
D) APP
125. What is the DB(P) line?
A) That the data line is partly closed
B) That the data line is carrying the parity information
C) That the data line is temporarily occupied
D) That the data line is carrying the device information
126. When the USB is connected to a system, its root hub is connected to the
________.
A) IDE
B) Processor BUS
C) PCI BUS
D) SCSI BUS
127. The I/O devices form the _____ of the tree structure.
A) Right subtrees
B) Leaves
C) Left subtrees
D) Subordinate root
128. The USB address space can be shared by the user's memory space.
A) True
B) False
129. The sampling process in speaker output is a ________ process.
A) None of the mentioned
B) Asynchronous
C) Isochronous
D) Synchronous
130. The initial address of a device just connected to the HUB is ________.
A) 0101010
B) FFFFFFF
C) AHFG890
D) 0000000
131. A USB pipe is a ______ channel.
A) Both Simplex and Full-Duplex
B) Full-Duplex
C) Half-Duplex
D) Simplex
132. USB is a parallel mode of transmission of data and this enables for the fast
speeds of data transfers.
A) True
B) False
133. The type/s of packets sent by the USB is/are _______.
A) Data
B) Address
C) Both Data and Control
D) Control
134. The transfer rate, when the USB is operating in low-speed operation is _____.
A) 12 Mb/s
B) 5 Mb/s
C) 2.5 Mb/s
D) 1.5 Mb/s
135. The device can send a message to the host by taking part in _____ for the
communication path.
A) Arbitration
B) None of the mentioned
C) Polling
D) Prioritizing
136. In USB, the devices can communicate with each other.
A) True
B) False
137. The USB device follows _______ structure.
A) Huffman
B) Hash
C) Tree
D) List
138. The devices connected to USB are assigned a ____ address.
A) 16 bit
B) 7 bit
C) 9 bit
D) 4 bit
139. Locations in the device to or from which data transfers can take place is
called ________.
A) Hosts
B) None of the mentioned
C) Source
D) End points
140. The high-speed mode of operation of the USB was introduced by _____.
A) ISA
B) ANSI
C) USB 2.0
D) USB 3.0