MEMORY TERMINOLOGIES

1. Memory Cell

This is a device or electrical circuit used to store a single bit (o or 1). Examples of memory cells
include a flip-flop, a single magnetic core, and a single spot on a magnetic tape or disk.

Fig2.1 a memory cell

If the READ/WRITE line is set to 1, then the two AND gates a and b each will have a 1 input. If at
the same time the DATA INPUT is 1 then the output of a would be 1 and b would be a 0. The flip-
flop is therefore set and stores logic 1. During this period the AND gate c is disabled because of the
NOT gate e. Similarly if the DATA INPUT is zero (0) b is enabled and the flip-flop stores a 0.

In order to read from the cell, the READ/WRITE line has to be made zero, 0. This disables gates a
and b preventing data from being written in. However c is enabled and its output will be the logic
value stored by the flip-flop.

2. Memory Word

This is a group of bits (cells) in a memory that represents information or data of some type. For
example, a register consisting of eight flip-flops can be considered to be a memory that is storing 8-
bit word. Word sizes in modern computers typically
ranges from 4 to 64 bits depending on the size of the computer.

3. Byte

This is a special term used for an 8-bit word. A byte always consists of 8 bits, which is one of the
most common word sizes in microcomputers.

4. Capacity

This is a way of specifying how many bits can be stored in a particular memory device or complete
memory system. Suppose there is a memory, which can store 4096 20-bit words. This represents a
total capacity of 81920 bits. This memory can also be represented as 4096 x 20. When represented
this way, the first number, (4096) is the number of words, and the second number, (20) is the number
of bits per word, (word size).
The number of words in a memory is often a multiple of 1024. It is common to use the designation
“1K” to represent 1024 when referring to memory capacity. Thus a memory that has a storage
capacity of 4K x 20 is actually a 4096 x 20 memory.

If a microprocessor has n address lines, then the number of address locations that it can uniquely
address is given by the formula
L = 2n
If the word size is W then the capacity, C, is given by
C = 2n x W
Sometimes the capacity is specified in terms of bytes. The capacity in bytes is given by
C = (2n x W)/8 bytes.

5. Address.

This is a number that identifies the location of a word in memory. Each word stored in a memory
device or system has a unique address. Addresses are always specified as a binary number, although,
octal, hexadecimal, and decimal numbers are often used for convenience.

Fig 2.2

The figure 2.2 shows a small memory consisting of eight words. Each of these eight words has a
specific address represented as a 3-bit number ranging from 000 to 111. When one refers to a
specific word location in memory, he uses its address code to identify it.

6. Read Operation

This is the operation whereby the binary words stored in a specific memory location (address) is
sensed and then transferred to another location. The read operation is also called a FETCH operation

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because the word is fetched from the memory. In the figure above, if we want to read WORD4 we
perform a read operation on address 100.

Fig 2.3 Read Operation

1. Address 5H put on address bus

2. Read signal applied
3. Contents of address 5H in memory put on data bus and stored in data register.

Once the address code is on the bus, the microprocessor control unit sends a read signal to the
memory. At the memory, the address bits are decoded, and the desired memory locations selected.
The read signal causes the contents of the selected address to be put on the data bus. The data byte is
then loaded into the data register to be used by the microprocessor. This completes the read
operation.

Note that each memory location contains one byte of data. When a byte is read from memory, it is
not destroyed but remains in the memory. This process of copying the contents of the memory
location without destroying those contents is called
NON-DESTRUCTIVE READOUT.

7. Write Operation

This is the operation whereby a new word is placed into a particular memory location. It is also
referred to as a store operation. Whenever a new word is written into a memory location, it replaces
the word that was previously stored there. The old word is lost in the process of writing into this
memory location.
 Fig. 2.4 Write Operation
The memory is addressed in the same way as during a read operation. A data byte being held in the
data register is put on to the data bus and the microprocessor sends the memory a WRITE signal.
This causes the byte on the data bus to be stored at the selected location in the memory as specified
by the 16-bit address code. The existing contents of that particular memory location are replaced by
the new data byte. This completes the write operation.

8. Memory Timing

The time between the arrival of the address signal and either the appearance of the data at the output
terminals or the completion of a write operation is called the memory access time. This is a measure
of a memory device’s operating speed. It is the amount of time required to perform a read operation.
It is the time between the memory receiving a read command signal and the data becoming available
at the memory output. This depends upon the technology used and the structure of the memory. For
a memory of the kind shown forming different register memories, the access time for two different
memory locations selected at random is essentially the same, and for this reason it is called a random
access memory (RAM).

Fig 2.5 A memory made of registers

Access time can be divided into two separate sections as shown in Figure 2.7 below.
 Fig.2.6 Divisions of access time.
The time between the arrival of the address signal and the location of that address signal is called the
latency, while the time for reading out of or writing into that address is called the data transfer time.
After the transfer of data a finite time is required for the device to return to its original internal state,
and this is called the settling time.
The sum of the latency, data transfer time and settling time is called the cycle time. It is the amount
of time required for the memory to perform a read or write operation and then return to its original
state ready for the next command. Cycle time is normally longer than access time. In effect, cycle
time is a measure of memory speed.

GENERAL MEMORY OPERATION

Although each type of memory is different in its internal operation, there are certain basic operating
principles that are the same for all memory systems.
Every memory system requires several different types of input and output lines to perform the
following functions:
 Select the address in memory that is being accessed for a READ or WRITE operation.
 Select either a READ or WRITE operation to be performed.
 Supply the input data to be stored in memory during a WRITE operation.
 Hold the output data coming from memory during a READ operation.
ENABLE (or DISABLE) the memory so that it will (or will not) respond to the address inputs and
read/write command.
MEMORY MAPPING

a) Hexadecimal Addresses

Hexadecimal numbers are easy to write and interpret and they do allow direct transformation to
and from binary form. This is because each hexadecimal digit directly represents a 4 bit binary
pattern. To write a binary number in hexadecimal, the number is divided into groups of 4 bits,
starting from the least significant end and the hexadecimal representation of each group is written
down. Taking 16 - bit binary number as an example we can have:

Binary Decimal Hexadecimal

0000000000000000 0 0000
0000000011110000 240 00F0
1110000000000001 57345 E001
0000101101101010 2922 0B6A
1111111111111111 65535 FFFF

If hexadecimal numbers are used to store addresses, and assume that the microcomputer has sixteen
address lines with a word size of 8 bits the memory map can be drawn as shown in figure.

When the MPU performs a READ or a WRITE operation it has to place an address on the address
bus to select one and only one memory location or 110 device. Most 8 - bit MPUs have a 16 bit
address bus that can specify any of 65536 different addresses.
In hex, these addresses range from 0000 to FFFF; this address range is called the MCs address space.
It is common to refer to the lowest address 0000 as the bottom of address space and the highest
address, FFFF, as the top of address space.
The microcomputer designer has to allocate this address space between the RAM ROM and I/O
devices
That is to be part of the system. The manner in which the total address space is apportioned among
These devices depend to a certain extent on characteristics of the MPU. In most cases however,
Some of the choices that the designer makes can be somewhat arbitrary.

b) Filling the memory

In practice the microcomputer system may not contain enough chips to provide storage of all these
addresses.
Only part of the available memory space may be filled with real memory chips. In such a
system only a section of the total number of addresses can be actually used in a program. The
remainder being invalid for future expansion.

A further complication is that the microcomputer memory is composed of a

mixture of memory
types, part may be ROM and part may be RAM.

c) The idea of memory Map

A memory map shows pictorially the total range of addresses available in a microcomputer system
together with the use to which any particular address is used. For example, a microcomputer
system may contain only two chips such as 4k bytes of ROM and 1k byte of RAM.

fig.

ROM occupies the address section from 0000H to 0FFFH. RAM occupies addresses from
3000H to 33FFH. Addresses 1000H to 2FFFH and addresses 3400H to FFFFH are unused.

The memory map therefore allows the system user to see at a glance what memory capacity is
available in the system and what addresses are not used. Of course, these unused addresses are
available for future memory or I/O expansion.
d) Memory pages
The 65,536 addresses can be divided into 256 blocks of 256 addresses, where each block is called
a page. Figure shows how the address space is organized into pages. Each page consists of all
hex addresses beginning with the same two digits. For example, page 00 includes all 256 hex
addresses in the range 0000 to 00FF. Similarly, page 7A includes hex addresses 7A00 to 7AFF

Fig. Address space organized into pages

Using page organization, one can think of each address as consisting of a page number and a word
number. To illustrate consider the address 2877.

2 8 7 7
page word
number number

The two most significant digits are the page number, and the least significant digits specify the
word number on that page.

Example

Determine how many pages are allocated for ROM in the memory map of Fig. and use this to
calculate the total number of ROM addresses. Repeat for RAM.

Solution

ROM occupies address 0000H to 0FFFH, this includes pages

00,01,02,03,04,05,06,07,08,09,0A,0B,0C, OD, OE and OF for a total of sixteen pages.
Since each page is 256 addresses, the total number of ROM address is 16 x 256 = 4096.

RAM occupies pages 30, 31, 32, and 33 for a total of four pages and 4 x 256 = 1024 addresses

Example
A certain microcomputer has 4096 RAM locations starting at address 0000. How many pages of
memory are allocated to RAM? Determine the complete RAM address range.

Solution
 4096/256 = 16 pages
The pages are 00,01,02,03,04,05,06,07,08,09, 0A, 0B, 0C, 0D, 0E & 0F. The complete
address range is 0000 to 0FFF.

Example

A certain program stored in ROM occupies all of page FD. What addresses does the program
occupy?

Solution

FDOO to FDFF

MEMORY ORGANIZATION

a) Bit organized

Most microcomputers have eight data buses and therefore have to store 8 bit words in
each memory location or address. If memory chips that are bit organized are used, then eight of them
are required with their address lines paralleled. The outputs are separated and taken from each chip
as shown below:

DATA LINES
Fig.
For 8 address lines each chip will contain 2 = 256 cells. Address lines will be A0 to A7. With
8 chips, the memory will store 256 words x 8 bits (256 x 8) memory

Question

a) Design a 1k x 8 bit memory using 1024 x 1 memory chips.

b) How many pages of memory are stored in each module?
c) Would you use 256 x 4 RAMs or 1k x 1RAMs if you needed a memory capacity two pages?
YC `
b)Word organized

Word organized chips can also be used and have them connected in a similar way. For
instance, if available are 256 x 4 memory chips, this can be connected to form (256 x 8) as shown
below.

Larger memories are made by use of an input chip select signal (CE) when this input is set, the
chip can be written into or read out of. If the chip is disabled, i.e. not set then chip can neither be
written into nor read from. A 1024 - word x 4-bit memory can be implemented from 4. 256 words x
4 bit chips are shown below even if there are Only 8 address lines.

The chip enable lines from each chip are not connected together so that only the chip whose CE line
has a positive signal will actually give an output or be written into. For example, if one wants to
address a word at address 14 decimal (binary 00001110) for chip 3 then the following address
signals are required.

Ao = 0 A4 = 1 CE1 = 0
A1 = 0 A5 = 1 CE2 = 0
A2 = 0 A6 = 1 CE3 = 1
A3 = 0 A7 = 0 CE4 = 0

Example:
 Would you use 256 x 4 RAMs or 1k x 1 RAMs if you needed a memory capacity of two
pages?
Solution
Two pages would be 512 x 8. Four 256 x 4 chips can be arranged as two 256 x 8 modules. 1k x 1
RAMs cannot be arranged to store only 512 words because each RAM has 1024 addresses. You
would have to use eight of these RAMs as in Fig. for a 1k x 8 capacity. This, of course, would be
wasteful because only half of this capacity is required. Thus the 256 x 4 RAM is the best choice.
Example
Describe the organization of a 16k x 8 RAM memory that uses 4k x 1 chips.
Solution
First eight, 4k x 1 chips are combined to form a 4k x 8 module. Then, four of these 4k x 8 modules
are used to produce the desired 16k x 8 capacity.
Example
What is the largest number of 1k x 8 memory modules (chips) that can be used with the Intel
8085 MPU?

Solution
The Intel 8085 can output 2 16 = 65,536 addresses. Because 1k = 1024, then

65,536 = 64
1024
Thus the 65536 addresses consist of 64 different 1 k blocks.

To select chip a A8 = A9 = 0

To select chip b A8 = 1 A9 = 0

To select chip c A8 = 0 A9 = 1

To select chip d A8 = A9
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