112暑 - IC TECH
112暑 - IC TECH
2. A 5-m wide trench is etched in a (100) Si wafer, so that the sidewalls of the trench are (110) plane as
shown in Fig.(a). This structure is then oxidized in H2O ambient at 1000℃for 50 min as shown in
Fig.(b). Assume the appropriate oxidation coefficient scale as (110): (100) = 1.2: 1.0.
(a) Please estimate tox(100), (2 pts)
(b) Please estimate tox(110), (3 pts)
3. Please explain what is the transient enhanced diffusion (TED) effect? What are the possible impacts
of TED for forming source/drain junction? (5 pts)
4. A process engineer fabricating an NMOSFET wants to dope the polysilicon gate at the same time as
doping the arsenic source/drain diffusion. The source/drain implant dose is 2×1015 cm-2 at an energy
of 50 keV.
(a) For the above implant conditions, what is the minimum polysilicon thickness that can be used if
the implant is not to affect the channel doping which is 1×1016 cm-3 near the surface? (Assume the
gate oxide is negligibly thick compared to the polysilicon). (5 pts)
(b) Assuming that this polysilicon thickness is actually used, how much of the implant dose will
penetrate the polysilicon mask is the process engineer decides to change the implant energy to 80
keV? (5 pts)
Note: the ion concentration, n(x), is assumed to be described by a symmetrical Gaussian
5. Please describe the baking steps employed in regular photoresist coating/development processes in
photolithography and their specific purposes. (8 pts)
6. (a) Please state the mechanisms and operation principles of RIE. (6 pts) (b) Why processing at low
pressure (<50 mTorr) is important for the etching of nanometer-scaled structures in IC manufacturing?
(2 pts)
7. Point out the species listed below which are radicals: Ar, N2, Cl, O, CH3, SiH4, SiH, Si2H6. (4 pts)
8. Free-response questions. Please explain in detail (including major features, processes, mechanisms,
definitions, or causes) the following items. (12 pts)
(a) Proximity effect (e-beam lithography)
(b) Immersion lithography
(c) Electron temperature
9. Step coverage of sputtering deposition can be improved by adding collimator, long-throw sputtering,
or ionized sputtering. Please briefly describe these three techniques and the mechanisms by which
they can improve step coverage (9 pts)
10. Compare the purity and etching rate in BOE of the SiO2 films formed by (a) APCVD TEOS/O3, (b)
LPCVD TEOS, (c) HTO (SiCl2H2 + N2O), and (d) PECVD TEOS/O2. (8 pts)
11. Explain the mechanism of the bottom-up filling of the Cu ECD process (3 pts) and explain the
advantages of Cu ECD over Cu CVD. (3 pts)
12. Explain the mechanism of SiO2 CMP. (4 pts) With the same abrasives, if the weight percentage is the
same, but the abrasive is smaller, will the polishing rate increase or slow down? Why? (2 pts)
13. Starting from the 0.18 m technology node, the Cu-interconnect fabricated by damascene process is
used to replace the Al-interconnect fabricated by subtractive process. Why? (4 pts) In recent years,
Ru-interconnect using subtractive process has attracted a lot of attention. Why? (5 pts)