8051 interrupts

Interrupts vs. polling

a) A single microcontroller can serve several devices. There are two ways to do that:
interrupts or polling.
b) In the interrupt method, whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal. Upon receiving an interrupt signal, the
microcontroller interrupts whatever it is doing and serves the device. The program associated
with the interrupt is called the interrupt service routine (ISR) or interrupt handler.
c) In polling, the microcontroller continuously monitors the status of a given device; when
the status condition is met, it performs the service. After that, it moves on to monitor the next
device until each one is serviced. Although polling can monitor the status of several devices
and serve each of them as certain conditions are met, it is not an efficient use of the
microcontroller.
d) The advantage of interrupts is that the microcontroller can serve many devices (not all at
the same time, of course); each device can get the attention of the microcontroller based on
the priority assigned to it. The polling method cannot assign priority since it checks all
devices in a round-robin fashion. More importantly, in the interrupt method the
microcontroller can also ignore (mask) a device request for service. This is again not possible
with the polling method.
e) The most important reason that the interrupt method is preferable is that the polling method
wastes much of the microcontroller’s time by polling devices that do not need service. So in
order to avoid tying down the microcontroller, interrupts are used. For example, in discussing
timers in Chapter 9 we used the instruction “JNB TF, target”, and waited until the timer
rolled over, and while we were waiting we could not do anything else.
f) That is a waste of the microcontroller’s time that could have been used to perform some
useful tasks. In the case of the timer, if we use the interrupt method, the microcontroller can
go about doing other tasks, and when the TF flag is raised the timer will interrupt the
microcontroller in whatever it is doing.
Interrupt service routine
When an interrupt is invoked, the microcontroller runs the interrupt service routine. For every
interrupt, there is a fixed location in memory that holds the address of its ISR. The group of
memory locations set aside to hold the addresses of ISRs is called the interrupt vector table.

Steps in executing an interrupt

Upon activation of an interrupt, the microcontroller goes through the following steps.
1. It finishes the instruction it is executing and saves the address of the next
instruction (PC) on the stack.
2. It also saves the current status of all the interrupts internally (i.e., not on the
stack).
3. It jumps to a fixed location in memory called the interrupt vector table that
holds the address of the interrupt service routine.
4. The microcontroller gets the address of the ISR from the interrupt vector table
and jumps to it. It starts to execute the interrupt service subroutine until it
reaches the last instruction of the subroutine, which is RETI (return from interrupt).
5. Upon executing the RETI instruction, the microcontroller returns to the place
where it was interrupted. First, it gets the program counter (PC) address from
the stack by popping the top two bytes of the stack into the PC. Then it starts
to execute from that address.
4.5.1 Six interrupts in the 8051
In reality, only five interrupts are available to the user in the 8051, but many manufacturers’
data sheets state that there are six interrupts since they include reset. The six interrupts in the
8051 are allocated as follows.
1. Reset. When the reset pin is activated, the 8051 jumps to address location 0000. This
is the power-up reset.
2. Two interrupts are set aside for the timers: one for Timer 0 and one for Timer
3. Memory locations OOOBH and 001BH in the interrupt vector table belong
to Timer 0 and Tinier 1, respectively.
4. Two interrupts are set aside for hardware external hardware interrupts. Pin
numbers 12 (P3.2) and 13 (P3.3) in port 3 are for the external hardware interrupts
INTO and INT1, respectively. These external interrupts are also referred
to as EX1 and EX2. Memory locations 0003H and 0013H in the interrupt vector table
are assigned to INTO and INT1, respectively.
5. Serial communication has a single interrupt that belongs to both receive and
transmit. The interrupt vector table location 0023H belongs to this interrupt.
From Table 4.5 , also notice that only three bytes of ROM space are assigned to the reset pin.
They are ROM address locations 0, 1, and 2. Address location 3 belongs to external hardware
interrupt 0. For this reason, in our program we put the LJMP as the first instruction and
redirect the processor away from the interrupt vector table
Table 4.5; Interrupt Vector Table for the 8051

Figure 4.9. Redirecting the 8051 from the Interrupt Vector Table at Power-up
4.5.2 Enabling and disabling an interrupt
Upon reset, all interrupts are disabled (masked), meaning that none will be responded to by
the microcontroller if they are activated. The interrupts must be enabled by software in order
for the microcontroller to respond to them. There is a register called IE (interrupt enable) that
is responsible for enabling (unmasking) and disabling (masking) the interrupts. Note that IE
is a bit-addressable register.
Steps in enabling an interrupt
1. To enable an interrupt, we take the following steps: .1. Bit D7 of the IE register (EA)
must be set to high to allow the rest of register to take effect.
2. If EA = 1, interrupts are enabled and will be responded to if their corresponding bits
in IE are high. If EA = 0, no interrupt will be responded to, even if the associated bit
in the IE register is high.

Figure 4.10. IE (Interrupt Enable) Register

Example 4-16

4.6 Programming timer

Figure 4.11. TF Interrupt

Roll-over timer flag and interrupt
1. Timer flag (TF) is raised when the timer rolls over. In that chapter, we also showed
how to monitor TF with the instruction “JNB TF, target”. In polling TF, we have to
wait until the TF is raised.
2. The problem with this method is that the microcontroller is tied down while waiting
for TF to be raised, and cannot do any thing else. Using interrupts solves this problem
and avoids tying down the controller.
3. If the timer interrupt in the IE register is enabled, whenever the timer rolls over, TF is
raised, and the microcontroller is interrupted in whatever it is doing, and jumps to the
interrupt vector table to service the ISR.
 4. In this way, the microcontroller can do other things until it is notified that the timer
has rolled over

Example 4-17
Write a program that continuously gets 8-bit data from PO and sends it to PI while
simultaneously creating a square wave of 200 (as period on pin P2.1. Use Timer 0 to create
the square wave. Assume that XTAL =11.0592 MHz.
Solution:

Example 4-18
Write a program o create a square wave that has a high portion of 1085 us and a low portion
of 15 us. Assume XTAL = 11.0592 MHz. Use Timer 1.
Notice that the low portion of the pulse is created by the 14 MC (machine cycles) where
each MC = 1.085 us and 14 x 1.085 us = 15.19 us.

Example 4-19
Write a program to generate a square wave of 50 Hz frequency on pin PI .2. UseTimer 0.
Assume that XTAL = 11.0592MHz.
4.7 External hardware interrupts

The 8051 has two external hardware interrupts. Piri 12 (P3.2) and pin 13 (P3.3) of the 8051,
designated as INTO and INT1, are used as external hardware interrupts. Upon activation of
these pins, the 8051 gets interrupted in whatever it is doing and jumps to the vector table to
perform the interrupt service routine.
 Figure 4.12: Activation of INTO and INT1
a) External interrupts INTO and INT1
There are only two external hardware interrupts in the 8051: INTO and INT1. They are
located on pins P3.2 and P3.3 of port 3, respectively. The interrupt vector table locations
0003H and 0013H are set aside for INTO and INT1, respectively. As mentioned in Section
11.1, they are enabled and disabled using the IE register. How are they activated? There are
two types of activation for the external hardware interrupts: (1) level triggered, and (2) edge
triggered. Let’s look at each one. First, we see how the level-triggered interrupt works.

4.7.1 Level-triggered interrupt

In the level-triggered mode, INTO and INT1 pins are normally high (just like all I/O port pins)
and if a low-level signal is applied to them, it triggers the interrupt. Then the microcontroller
stops whatever it is doing and jumps to the interrupt vector table to service that interrupt. This
is called a level-triggered or level-activated interrupt and is the default mode upon reset of
the 8051. The low-level signal at the INT pin must be removed before the execution of the
last instruction of the interrupt service routine, RETI; otherwise, another interrupt will be
generated. In other words, if the low-level interrupt signal is not removed before the ISR is
finished it is interpreted as another interrupt and the 8051 jumps to the vector table to execute
the ISR again.

Example 4.20
Assume that the INT1 pin is connected to a switch that is normally high. Whenever it goes
low, it should turn on an LED. The LED is connected to PI .3 and is normally off. When it is
turned on it should stay on for a fraction of a second. As long as the switch is pressed low, the
LED should stay on.
Solution:

4.7.2 Sampling the low level-triggered interrupt

1. Pins P3.2 and P3.3 are used for normal I/O unless the INTO and INT1 bits in the IE
registers are enabled. After the hardware interrupts in the IE register are enabled, the
controller keeps sampling the INT« pin for a low-level signal once each machine
cycle. According to one manufacturer’s data sheet “the pin must be held in a low state
until the start of the execution of ISR.
2. If the INTn pin is brought back to a logic high before the start of the execution of ISR
there will be no interrupt.” However, upon activation of the interrupt due to the low
level, it must be brought back to high before the execution of RETI. Again, according
to one manufacturer’s data sheet, “If the INTw pin is left at a logic low after the RETI
instruction of the ISR, another interrupt will be activated after one instruction is
executed.” Therefore, to ensure the activation of the hardware interrupt at the INTw
pin, make sure that the duration of the low-level signal is around 4 machine cycles,
 but no more. This is due to the fact that the level-triggered interrupt is not latched.
Thus the pin must be held in a low state until the start of the ISR execution.

Figure 4.13:. Minimum Duration of the Low Level-Triggered Interrupt (XTAL =

11.0592 MHz)

4.7.3 Edge-triggered interrupts

As stated before, upon reset the 8051 makes INTO and INT1 low-level triggered interrupts.
To make them edge-triggered interrupts, we must program the bits of the TCON register. The
TCON register holds, among other bits, the ITO and IT1 flag bits that determine level- or
edge-triggered mode of the hardware interrupts. ITO and IT1 are bits DO and D2 of the
TCON register, respectively. They are also referred to as TCON.O and TCON.2 since the
TCON register is bit-addressable. Upon reset, TCON.O (ITO) and TCON.2 (III) are both Os,
meaning that the external hardware interrupts of INTO and INT1 pins are low-level triggered.
By making the TCON.O and TCON.2 bits high with instructions such as “SETB TCON. 0″
and “SETB TCON. 2″, the external hardware interrupts of INTO and INT1 become edge-
triggered. For example, the instruction “SETB CON. 2″ makes INT1 what is called an edge-
triggered interrupt, in which, when a high-to-low signal is applied to pin P3.3, in this case,
the controller will be interrupted and forced to jump to location 0013H in the vector table to
service the ISR (assuming that the interrupt bit is enabled in the IE register).

Figure 4.14:. TCON (Timer/Counter) Register (Bit-addressable)

TF1 TCON.7 Timer 1 overflow flag. Set by hardware when timer/counter 1

overflows. Cleared by hardware as the processor vectors to the interrupt service routine.
TR1 TCON.6 Timer 1 run control bit. Set/cleared by software to turn timer/counter 1 on/off.
TF0 TCON.5 Timer 0 overflow flag. Set by hardware when timer/counter 0 overflows.
Cleared by hardware as the processor vectors to the service routine.
TR0 TCON.4 Timer 0 run control bit. Set/cleared by software to turn
timer/counter 0 on/off.
IE1 TCON.3 External interrupt 1 edge flag. Set by CPU when the external interrupt edge (H-
to-L transition) is detected. Cleared by CPU when the interrupt is processed. Note: This flag
does not latch low-level triggered interrupts.
IT1 TCON.2 Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low-
level triggered external interrupt.
IE0 TCON.1 External interrupt 0 edge flag. Set by CPU when external interrupt (H-to-L
transition) edge is detected. Cleared by CPU when interrupt is processed. Note: This flag
does not latch low-level triggered interrupts.
IT0 TCON.0 Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low-
level triggered external interrupt.

Example 4-21
Assuming that pin 3.3 (INT1) is connected to a pulse generator, write a program in which the
falling edge of the pulse will send a high to PI.3, which is connected to an LED (or buzzer).
In other words, the LED is turned on and off at the same rate as the pulses are applied to the
INT1 pin. This is an edge-triggered version of Example 11-5.
4.7.4 Sampling the edge-triggered interrupt

In edge-triggered interrupts, the external source must be held high for at least one machine
cycle, and then held low for at least one machine cycle to ensure that the transition is seen by
the microcontroller.

1. The falling edge is latched by the 8051 and is held by the TCON register. The TCON.
1 and TCON.3 bits hold the latched falling edge of pins INTO and INT1, respectively.
TCON.l and TCON.3 are also called IEO and IE1, respectively, as shown in Figure
11-6. They function as interrupt-in-service flags.
2. When an interrupt-in-service flag is raised, it indicates to the external world that the
interrupt is being serviced and no new interrupt on this INTw pin will be responded to
until this service is finished. This is just like the busy signal you get if calling a
telephone number that is in use. Regarding the ITO and IT1 bits in the TCON register,
the following two points must be emphasized.

Example 4-22
What is the difference between the RET and RETI instructions? Explain why we cannot use
RET instead of RETI as the last instruction of an ISR.
Solution:
Both perform the same actions of popping off the top two bytes of the stack into the program
counter, and making the 8051 return to where it left off. However, RETI also performs an
additional task of clearing the interrupt-in-service flag, indicating that the servicing of the
interrupt is over and the 8051 now can accept a new interrupt on that pin. If you use RET
instead of RETI as the last instruction of the interrupt service routine, you simply block any
new interrupt on that pin after the first interrupt, since the pin status would indicate that the
interrupt is still being serviced. In the cases of TFO, TF1, TCON.l, and TCON.3, they are
cleared by the execution of RETI.
4.8 Serial communication interrupt

Rl and Tl flags and interrupts

1. TI (transfer interrupt) is raised when the last bit of the framed data, the stop bit, is
transferred, indicating that the SBUF register is ready to transfer the next byte. RI
(received interrupt), is raised when the entire frame of data, including the stop bit, is
received. In other words, when the SBUF register has a byte, RI is raised to indicate
that the received byte needs to be picked up before it is lost (overrun) by new
incoming serial data.
2. As far as serial communication is concerned, all the above concepts apply equally
when using either polling or an interrupt. The only difference is in how the serial
communication needs are served. In the polling method, we wait for the flag (TI or RI)
to be raised; while we wait we cannot do anything else. In the interrupt method, we
are notified when the 8051 has received a byte, or is ready to send the next byte; we
can do other things while the serial communication needs are served.
3. In the 8051 only one interrupt is set aside for serial communication. This interrupt is
used to both send and receive data. If the interrupt bit in the IE register (IE.4) is
enabled, when RI or TI is raised the 8051 gets interrupted and jumps to memory
address location 0023H to execute the ISR. In that ISR we must examine the TI and
RI flags to see which one caused the interrupt and respond accordingly.

Figure 4.15:. Single Interrupt for Both TI and RI

Example 4-23
Write a program in which the 8051 reads data from PI and writes it to P2 continuously while
giving a copy of it to the serial COM port to be transferred serially. Assume that XTAL =
11.0592 MHz. Set the baud rate at 9600.
Solution:
Example 4-24
Write a program in which the 8051 gets data from PI and sends it to P2 continuously while
incoming data from the serial port is sent to PO. Assume that XTAL = 11.0592 MHz. Set the
baud rate at 9600.
Solution:
4.9 Interrupt priority in 8051/52

Interrupt priority upon reset

When the 8051 is powered up, the priorities are assigned according to Table 4.6.
Table 4.6: Interrupt priority

Example 4-26
Discuss what happens if interrupts INTO, TFO, and INT1 are activated at the same time.
Assume priority levels were set by the power-up reset and that the external hardware
interrupts are edge-triggered.
Solution:
If these three interrupts are activated at the same time, they are latched and kept internally.
Then the 8051 checks all five interrupts according to the sequence listed in Table 4.6.If any is
activated, it services it in sequence. Therefore, when the above three interrupts are activated,
IEO (external interrupt 0) is serviced first, then Timer 0 (TFO), and finally IE1 (external
interrupt 1).

Figure 4.16:. Interrupt Priority Register (Bit-addressable)

Example 4-27
(a) Program the IP register to assign the highest priority to INT1 (external interrupt 1), then
(b) discuss what happens if INTO, INT1, and TFO are activated at the same time. Assume
that the interrupts are both edge-triggered.
Solution:
1. MOV IP,#000001006 ;IP.2 = 1 to assign INT1 higher priority
The instruction “SETB IP.2″ also will do the same thing as the above line since
IP is bit-addressable.
2. The instruction in Step (a) assigned a higher priority to INT1 than the others;
therefore, when INTO, INT1, and TFO interrupts are activated at the same time, the
8051services INT1 first, then it services INTO, then TFO. This is due to the fact that
INT1 has a higher priority than the other two because of the instruction in Step (a).
The instruction in Step (a) makes both the INTO and TFO bits in the IP register 0.
Example 4-28
Assume that after reset, the interrupt priority is set by the instruction “MOV IP,
400001100B”. Discuss the sequence in which the interrupts are serviced.
Solution:
The instruction “MOV IP, #0 0 0 0110 OB” (B is for binary) sets the external interrupt 1
(INT1) and Timer 1 (TF1) to a higher priority level compared with the rest of the interrupts.
However, since they are polled according to Table 11-3, they will have the following priority.

4.10 Interrupt programming in C

The 8051 C compilers have extensive support for the 8051 interrupts with two major features
as follows:
1. They assign a unique number to each of the 8051 interrupts, as shown in Table
11-4.
2. It can also assign a register bank to an ISR. This avoids code overhead due to
the pushes and pops of the RO – R7 registers.
Table 4.7: 8051/52 Interrupt Numbers in C

Example 4-29
Write a C program that continuously gets a single bit of data from PI. 7 and sends it to Pl.0,
while simultaneously creating a square wave of 200 (as period on pin P2.5. Use timer 0 to
create the square wave. Assume that XTAL = 11.0592 MHz.
Solution:
Example 4-30
Write a C program that continuously gets a single bit of data from PI. 7 and sends it to Pl.0 in
the main, while simultaneously (a) creating a square wave of 200 us period on pin P2.5, and
(b) sending letter ‘A’ to the serial port. Use Timer 0 to create the square wave. Assume that
XTAL = 11.0592 MHz. Use the 9600 baud rate.
Solution:
Example 4-31
Write a C program using interrupts to do the following:
1. Receive data serially and send it to P0,
2. Read port PI, transmit data serially, and give a copy to P2,
3. Make timer 0 generate a square wave of 5 kHz frequency on P0.l.
Assume that XTAL = 11.0592 MHz. Set the baud rate at 4800.
Solution:
Example 4-32
Write a C program using interrupts to do the following:
1. Generate a 10000 Hz frequency on P2.1 using TO 8-bit auto-reload,
2. Use timer 1 as an event counter to count up a 1-Hz pulse and display it on PO. The
pulse is connected to EX1.
Assume that XTAL = 11.0592 MHz. Set the baud rate at 9600.