Langage de programmation

VHDL
Exercices: Logique séquentielle
Bascule D

Code VHDL
library ieee ;
use ieee.std_logic_1164.all;
entity dff is
port( data_in,clock: in std_logic;
data_out: out std_logic);
end dff;
architecture behv of dff is
begin
process(data_in, clock)
begin
if (clock'event and clock='1') then data_out <= data_in;
end if;
end process;
end behv;
Testbench D library ieee;
use ieee.std_logic_1164.all;
entity dff_TB is -- entity declaration
end dff_TB;
architecture TB of dff_TB is
signal T_data_in,T_clock,T_data_out: std_logic;
component dff
port( clock, data_in: in std_logic;data_out: out std_logic);
end component;
begin
U_DFF: dff port map (T_data_in, T_clock, T_data_out);
process
begin
T_clock <= '0';
wait for 10 ns;
T_clock <= '1';
wait for 10 ns;
end process;
process
begin
-- case 1
T_data_in <= '1';wait for 20 ns;
-- case 2
T_data_in <= '0';wait for 10 ns;
-- case 3
T_data_in <= '1';wait for 20 ns;
-- case 4
T_data_in <= '0';wait for 20 ns;
-- case 5
T_data_in <= '1';wait for 10 ns;
-- case 5
T_data_in <= '0';wait for 10 ns;
-- case 5
T_data_in <= '1';wait for 20 ns;
wait;
end process;
end TB;
 Affectation des pins
NET "clock" LOC = "B8";
NET "data_out" LOC = "J14";
NET "data_in" LOC = "B18";

RTL
chronogramme
Bascule JK Code JK
--JK
library ieee;
use ieee.std_logic_1164.all;
entity JK_FF is
port ( clock,J,K,reset: in std_logic;
Q, Qbar: out std_logic);
end JK_FF;
architecture behv of JK_FF is
signal state: std_logic;
signal input: std_logic_vector(1 downto 0);
begin
input <= J & K;
p: process(clock, reset) is
begin

if (reset='1') then
state <= '0';
elsif (rising_edge(clock)) then

-- compare to the truth table

case (input) is
when "11" =>
state <= not state;
when "10" =>
state <= '1';
when "01" =>
state <= '0';
when others =>
null;
end case;
end if;

end process;
RTL
--JK Testbench
library ieee; Affectation des pins
use ieee.std_logic_1164.all;
entity jkff_TB is
end jkff_TB;
architecture TB of jkff_TB is NET "clock" LOC = "B8";
signal T_J, T_K,T_clock,T_reset,T_Q,T_Qbar: std_logic; NET "rest" LOC = "B18";
component JK_FF is
port ( clock,J,K,reset: in std_logic; # Leds
Q,Qbar: out std_logic ); NET "Qbar" LOC = "J14";
end component; NET "Q" LOC = "J15";
begin
# Switches
U_JKFF: JK_FF port map (T_clock, T_J, T_K, T_reset, T_Q, T_Qbar);
process NET "J" LOC = "G18";
begin NET "K" LOC = "H18";
T_clock <= '0';wait for 5 ns;
T_clock <= '1';wait for 5 ns;
end process;
process
begin
T_reset <= '1'; wait for 25 ns;
T_reset <= '0';wait for 10 ns;
-- case 1 chronogramme
T_J <= '0'; T_K <= '1';wait for 15 ns;
-- case 2
T_J <= '1';T_K <= '0';wait for 5 ns;
-- case 3
T_J <= '1';T_K <= '1';wait for 5 ns;
wait;
end process;
end TB;
Registre Code

---------------------------------------------------
-- n-bit Register
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity reg is
generic(n: natural :=2);
port( I: in std_logic_vector(n-1 downto 0);
clock,load,clear: in std_logic;
Q: out std_logic_vector(n-1 downto 0));
end reg;
architecture behv of reg is
signal Q_tmp: std_logic_vector(n-1 downto 0);
begin
process(I, clock, load, clear)
begin
if clear = '0' then
-- use 'range in signal assigment
Q_tmp <= (Q_tmp'range => '0');
elsif (clock='1' and clock'event) then
if load = '1' then
Q_tmp <= I;
end if;
end if;
end process;
-- concurrent statement
Q <= Q_tmp;
end behv;
Register RTL
TestBench Register -- Test Bench for 2-bit
library ieee;
use ieee.std_logic_1164.all;
entity reg_TB is
end reg_TB;
architecture TB of reg_TB is
component reg
port( I:in std_logic_vector(1 downto 0); clock,load,clear: in std_logic; Q:out std_logic_vector(1 downto 0) );
end component;
signal T_Q,T_I: std_logic_vector(1 downto 0);
signal T_clear,T_load,T_clock: std_logic;
begin
U_reg: reg port map (T_I, T_clock, T_load, T_clear, T_Q);
-- concurrent process to offer the clock signal
process
begin
T_clock <= '0';
wait for 5 ns;
T_clock <= '1';
wait for 5 ns;
end process;
process
begin
T_I <= "10"; T_load <= '0'; T_clear <= '1';
-- case 1
wait for 20 ns; T_load <= '1';
-- case 2
wait for 10 ns; T_load <= '0';
--wait for 10 ns;
-- case 3
wait for 10 ns; T_clear <= '0';
--wait for 10 ns;
-- case 4
wait for 10 ns; T_clear <= '1';
--wait for 10 ns;
wait;
end process;
end TB;
Chronogramme

Pins
NET "clock" LOC = "B8";
# Leds
NET "Q<0>" LOC = "J14";
NET "Q<1>" LOC = "J15";
# Switches
NET "I<0>" LOC = "G18";
NET "I<1>" LOC = "H18";
NET "clear" LOC = "D18";
#NET "load" LOC = "B18";
#NET "i3" LOC = "K17";
Registre à décalage 3 bits

-- 3-bit Shift-Register/Shifter

library ieee ;
use ieee.std_logic_1164.all;
entity shift_reg is
port( I,clock,shift: in std_logic;
Q: out std_logic);
end shift_reg;
architecture behv of shift_reg is
-- initialize the declared signal
signal S: std_logic_vector(2 downto 0):="111";
begin
process(I, clock, shift, S)
begin
-- everything happens upon the clock changing
if clock'event and clock='1' then
if shift = '1' then
S <= I & S(2 downto 1);
end if;
end if;
end process;
-- concurrent assignment
Q <= S(0);
end behv;
Shift register RTL -- Test Bench for 3-bit shift register
library ieee;
use ieee.std_logic_1164.all;
entity shifter_TB is -- entity declaration
end shifter_TB;
architecture TB of shifter_TB is
component shift_reg
port( I,clock,shift: in std_logic;Q: out std_logic);
end component;
signal T_I,T_clock,T_shift,T_Q: std_logic;
begin
U_shifter: shift_reg port map (T_I, T_clock, T_shift, T_Q);
-- concurrent process of clock
process
begin
T_clock <= '0';
wait for 5 ns;
T_clock <= '1';
wait for 5 ns;
end process;
-- concurrent process of test
process
begin

T_shift <= '1'; -- start shifting

T_I <= '0';
wait for 20 ns;
T_I <= '1'; -- 1st/2nd bit input
wait for 20 ns;
T_I <= '0'; -- 3rd bit input
wait for 10 ns;
T_I <= '1'; -- 4th bit input
wait;
end process;
end TB;
Chronogramme

Routing
Compteur
-- Test Bench for counter
library ieee;
use ieee.std_logic_1164.all;
entity counter_TB is
end counter_TB;
architecture TB of counter_TB is
component counter
port( clock,clear,count: in std_logic; Q: out std_logic_vector(1 downto 0) );
end component;
signal T_clock,T_clear,T_count: std_logic;
signal T_Q: std_logic_vector(1 downto 0);
begin
U_counter: counter port map (T_clock, T_clear, T_count, T_Q);
process
begin
T_clock <= '0'; -- clock cycle is 10 ns
wait for 5 ns;
T_clock <= '1';
wait for 5 ns;
end process;

--
process
variable err_cnt: integer :=0;
Chronogramme ????
begin
T_clear <= '1'; -- start counting
T_count <= '1';
wait for 20 ns;
T_clear <= '0'; -- start counting
T_count <= '0';
wait for 20 ns;
T_clear <= '1'; -- start counting
T_count <= '1';
wait for 20 ns;
wait;
end process;
end TB;
 comb_logic: process(current_state, a)
Que fait le code suivant? begin
-- use case statement to show the -- state transistion
library ieee ; case current_state is
use ieee.std_logic_1164.all; when S0 => x <= '0';
----------------------------------------------------- if a='0' then
entity seq_design is next_state <= S0;
port( a,clock,reset:in std_logic;x: elsif a ='1' then
out std_logic); next_state <= S1;
end seq_design; end if;
----------------------------------------------------- when S1 => x <= '0';
architecture FSM of seq_design is if a='0' then
-- define the states of FSM model next_state <= S1;
type state_type is (S0, S1, S2, S3); elsif a='1' then
signal next_state, current_state: state_type; next_state <= S2;
begin end if;
-- cocurrent process#1: state registers when S2 => x <= '0';
state_reg: process(clock, reset) if a='0' then
begin next_state <= S2;
if (reset='1') then elsif a='1' then
current_state <= S0; next_state <= S3;
elsif (clock'event and clock='1') then end if;
current_state <= next_state; when S3 => x <= '1';
end if; if a='0' then
end process; next_state <= S3;
elsif a='1' then
next_state <= S0;
end if;
when others =>
x <= '0';
next_state <= S0;
end case;
end process; end FSM;
Que fait le code suivant? library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- two 4-bit inputs and one 8-bit outputs
entity multiplier is
port( num1, num2: in std_logic_vector(1 downto 0);
product: out std_logic_vector(3 downto 0));
end multiplier;
architecture behv of multiplier is
begin
process(num1, num2)
variable num1_reg: std_logic_vector(2 downto 0);
variable product_reg: std_logic_vector(5 downto 0);
begin
num1_reg := '0' & num1;
product_reg := "0000" & num2;
-- use variables doing computation
-- algorithm is to repeat shifting/adding
for i in 1 to 3 loop
if product_reg(0)='1' then
product_reg(5 downto 3) := product_reg(5 downto 3)
+ num1_reg(2 downto 0);
end if;
product_reg(5 downto 0) := '0' & product_reg(5 downto 1);
end loop;
-- assign the result of computation back to output signal
product <= product_reg(3 downto 0);
end process;
end behv;