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3 views3 pages

Haha

Uploaded by

nguyenminhphuoc154
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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//CLK1

module CLK1(CLOCK_50,CLK);
input CLOCK_50;
output reg CLK;
reg [25:0] counter;

always @(posedge CLOCK_50)


if (counter == 24999999)
begin
counter <= 1'b0;
CLK <= ~CLK;
end
else
counter <= counter + 1'b1;

endmodule

//counter
module counter(CLK, reset, cp, dem);
input CLK;
input reset;
input cp;
output reg[5:0] dem;

always @(posedge CLK)


begin
dem <= dem +1'b1;
if (dem == 6'd59)
dem <= 1'b0;
else if (cp == 1'b0)
dem <= dem;
else if (reset == 1'b0)
dem <= 1'b0;
end

endmodule

//control
module control(CLK, giay, phut, cp, reset, gt_dem, KEY);
input [5:0]gt_dem;
input [1:0] KEY;
input CLK;
output wire cp;
output wire reset;
output reg[5:0] giay;
output reg[5:0] phut;

always @(posedge CLK)


begin
giay <= gt_dem;
if (giay == 6'd59)
begin
phut <= phut + 1'b1;
giay <= 1'b0;
end
else if (reset == 1'b0)
begin
phut <= 1'b0;
end
end

assign reset = (KEY[0] == 1'b0)? 1'b0: 1'b1;


assign cp = (KEY[1] == 1'b0)? 1'b0: 1'b1;
endmodule

//display
module display(giay, phut ,HEX0, HEX1, HEX2, HEX3, HEX4);
input [5:0] giay;
input [5:0] phut;
output [0:6] HEX0, HEX1, HEX2, HEX3, HEX4;
wire [3:0]donvig, chucg, donvip, chucp;

assign HEX2 = 7'b1111110;


assign donvig = giay % 4'd10;
assign donvip = phut % 4'd10;
assign chucg = giay / 4'd10;
assign chucp = phut / 4'd10;

assign HEX0 = (donvig == 4'b0000) ? 7'b0000001 : //so 0


(donvig == 4'b0001) ? 7'b1001111 : //so 1
(donvig == 4'b0010) ? 7'b0010010 : //so 2
(donvig == 4'b0011) ? 7'b0000110 : //so 3
(donvig == 4'b0100) ? 7'b1001100 : //so 4
(donvig == 4'b0101) ? 7'b0100100 : //so 5
(donvig == 4'b0110) ? 7'b1100000 : //so 6
(donvig == 4'b0111) ? 7'b0001111 : //so 7
(donvig == 4'b1000) ? 7'b0000000 : 7'b0000100; //so 8,9

assign HEX1 = (chucg == 4'b0000) ? 7'b0000001 : //so 0


(chucg == 4'b0001) ? 7'b1001111 : //so 1
(chucg == 4'b0010) ? 7'b0010010 : //so 2
(chucg == 4'b0011) ? 7'b0000110 : //so 3
(chucg == 4'b0100) ? 7'b1001100 : //so 4
(chucg == 4'b0101) ? 7'b0100100 : //so 5
(chucg == 4'b0110) ? 7'b1100000 : //so 6
(chucg == 4'b0111) ? 7'b0001111 : //so 7
(chucg == 4'b1000) ? 7'b0000000 : 7'b0000100; //so 8,9

assign HEX3 = (donvip == 4'b0000) ? 7'b0000001 : //so 0


(donvip == 4'b0001) ? 7'b1001111 : //so 1
(donvip == 4'b0010) ? 7'b0010010 : //so 2
(donvip == 4'b0011) ? 7'b0000110 : //so 3
(donvip == 4'b0100) ? 7'b1001100 : //so 4
(donvip == 4'b0101) ? 7'b0100100 : //so 5
(donvip == 4'b0110) ? 7'b1100000 : //so 6
(donvip == 4'b0111) ? 7'b0001111 : //so 7
(donvip == 4'b1000) ? 7'b0000000 : 7'b0000100; //so 8,9

assign HEX4 = (chucp == 4'b0000) ? 7'b0000001 : //so 0


(chucp == 4'b0001) ? 7'b1001111 : //so 1
(chucp == 4'b0010) ? 7'b0010010 : //so 2
(chucp == 4'b0011) ? 7'b0000110 : //so 3
(chucp == 4'b0100) ? 7'b1001100 : //so 4
(chucp == 4'b0101) ? 7'b0100100 : //so 5
(chucp == 4'b0110) ? 7'b1100000 : //so 6
(chucp == 4'b0111) ? 7'b0001111 : //so 7
(chucp == 4'b1000) ? 7'b0000000 : 7'b0000100; //so 8,9
endmodule

//dongho
module dongHo(CLOCK_50, hex0, hex1, hex2, hex3, hex4, key);
input CLOCK_50;
input [1:0] key;
output [0:6] hex0, hex1, hex2, hex3, hex4;
wire clk1, cp, reset;
wire [5:0] gt, s, m;

CLK1 U0 (.CLOCK_50(CLOCK_50), .CLK(clk1));


counter U1 (.CLK(clk1), .cp(cp), .reset(reset), .dem(gt));
control U2
(.gt_dem(gt), .CLK(clk1), .cp(cp), .reset(reset), .giay(s), .phut(m), .KEY(key));
display U3 (.giay(s), .phut(m), .HEX0(hex0), .HEX1(hex1), .HEX2(hex2), .HEX3(hex3),
.HEX4(hex4));

endmodule

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