Architecture - Features, Operating Modes

FEATURES OF 80386:
Two versions of 80386 are commonly available:

1) 80386DX
2) 80386SX
80386DX 80386SX
1) 32 bit address bus 1) 24 bit address bus
32bit data bus 16 bit data bus
2) Packaged in 132 pin ceramic 1) 100 pin flat
pin grid array(PGA) package
3) Address 4GB of memory 2) 16 MB of memory
Department of Computer
Engineering,PCCOE,Pune
The 80386 is a 32-bit microprocessor that can support
8-bit, 16-bit and 32-bit operands. It has 32-bits
registers, 32-bits internal and external data bus, and 32-
bit address bus.
Due to its 32-bit address bus, the 80386 can address up
to 4GB of physical memory. The physical memory of this
processor is organized in terms of segments of 4 GB size
at maximum.
80386 Microprocessor has a 16-byte prefetch queue
It operates at clock speeds of 16 MHz to 33 MHz.
32 bit processor, it has 32 bit ALU which allows to
process 32 bit data at a time.
32 bit address bus, therefore it can access 4GB physical
memory and 64Terabytes of Virtual memory.
It has pipeline architecture which allows simultaneous
instruction fetching, decoding, and executing and
memory management.
It allows user to switch between different OS such as
DOS and UNIX
Operates in Real, Protected and Virtual 8086 mode.
Memory management, Multitasking and Protection.
• This Features of 80386 Microprocessor has memory
management unit with a segmentation unit and a paging
Unit.
• It operates in real, protected and virtual real mode. The
protected mode of 80386 is fully compatible with 80286.
• The 80386 can run 8086 applications under a protected
mode in its virtual 8086 mode of operation.
• The 80386 processor supports Intel 80387 numeric data
processor.
It compatible with 8086, 8088, 80186, 80286 architecture.
It has different data types like bits, byte, word, double
word, Quadword, Tenbytes integer (signed and unsigned
form).
It has Separate pins for its address and data line, this result
in higher performance and easier hardware design.
Prefetch unit permits to prefetch upto 16bytes of
instruction code. Therefore fetch time for most instruction
is hidden, increase the performance.
Architecture of
80386
It has 6 functional units which are as follows:
1. Bus Interface Unit
2.Code Fetch Unit
3. Instruction Decode Unit
4. Execution Unit
5.Memory Management Unit
The Internal Architecture of 80386 is divided into 3
sections.
1 Central processing unit(CPU)
a. Code Fetch Unit
b. Instruction Unit
c. Execution Unit
2 Memory management unit(MMU)
a. Segmentation Unit
b. Paging Unit
3 Bus interface unit(BIU)
1. Bus Interface Unit
The bus interface unit or BIU holds a 32-bit bidirectional data
bus as well as a 32-bit address bus. Whenever a need for
instruction or a data fetch is generated by the system then the
BIU generates signals (according to the priority) for activating
the data and address bus in order to fetch the data from the
desired address.
The BIU connects the peripheral devices through the memory

unit and also controls the interfacing of external buses with the
coprocessors.
2. Code Prefetch Unit
This unit fetches the instructions stored in the memory by
making use of system buses. Whenever the system generates a
need for instruction then the code prefetch unit fetches that
instruction from the memory and stores it in a 16-byte prefetch
queue. So to speed up the operation this unit fetches the
instructions in advance and the queue stores these instructions.
The sequence in which the instructions are fetched and gets

stored in the queue depends on the order they exist in the
memory.
Code prefetching holds lower priority than data transferring.
As whenever a need for data transfer is generated by the
system then immediately the code prefetcher leaves control
over the buses. So that the BIU can transfer the required data.
3. Instruction Decode Unit
We know that instructions in the memory are stored in the
form of bits. So, this unit decodes the instructions stored in the
prefetch queue. Basically the decoder changes the machine
language code into assembly language and transfers it to the
processor for further execution.
4. Execution Unit
The decoded instructions are stored in the decoded instruction
queue. So, these instructions are provided to the execution unit
in order to execute the instructions. The execution unit controls
the execution of the decoded instructions. This unit has a 32-
bit ALU, that performs the operation over 32-bit data in one
cycle. Also, it consists of 8 general purpose as well as 8 special
purpose registers. These are used for data handling and
calculation of offset address.
5. Memory Management Unit
This unit has two separate units within it. These are
1. Segmentation Unit and
2. Paging Unit
Segmentation unit: The segmentation unit plays a vital
role in the 80836 microprocessor. It offers a protection
mechanism in order to protect the code or data present in
the memory from application programs.
It gives 4 level protection to the data or code present in
the memory. Every information in the memory is assigned
a privilege level from PL0 to PL3. Here, PL0 holds the
highest priority and PL3 holds the lowest priority.
Paging Unit: The paging unit operates only in protected mode
and it changes the linear address into a physical address. As
the programmer only provides the virtual address and not the
physical address.
The segmentation unit controls the action of the paging unit, as
the segmentation unit has the ability to convert the logical
address into the linear address at the time of executing an
instruction. Basically, it changes the overall task map into
pages and each page has a size of 4K. This allows the handling
of tasks in the form of pages rather than segments.
Operating modes of 80386
80286 supports two operating modes. The first is real
address mode while the second is the protected virtual
address mode. However, 80386 supports 3 operating
modes: real, protected, and virtual real mode.
Requires the resetting of the microprocessor in order to

switch to real mode from protected mode. This drawback
was eliminated in 80386 that allows the switching
between the modes using software commands.
Real Mode:
• Power on Default mode
• 1 MB memory is accessible
• Upward compatibility
• Faster 8086: Higher Clock Frequency
• No multitasking , no protection
Protected Mode:
• Natural 32-bit environment of the 80386 processor.
• 4 level Protection Mechanism
• 32 new instruction(for Protected mode management)
• Multiprogramming Environment
• Segment size : 1 to 4G
• OS can use feature line paging
Protected Mode:
Virtual Mode:
• Virtual mode flag is set then enters into protected
mode.
• Multiprogramming environment
• Paging and Protection capabilities are available
• Address Mechanism same as 8086
Register
Organization
General Purpose Register
Pointer register
Index register
Segment Register
Eflags
System Address/Memory management Registers
Control Register
Debug Register
Test Register
General Purpose Register
◦ The 32-bit general-purpose registers (EAX, EBX,
ECX, EDX).
◦ The 16-bit general-purpose registers (AX, BX, CX,
DX).
◦ The 8-bit general-purpose registers (AH, BH, CH,
DH, AL, BL, CL, or DL).
Pointer Register
◦ The 32 bit pointer register (EBP, ESP)
◦ The 16-bit Pointer registers (BP, SP)
Index Register
◦ The 32 bit Index register (ESI, EDI)
◦ The 16-bit Pointer registers (SI, DI)
Instruction Pointer
◦ The 32 bit Instruction pointer (EIP)
Segment Registers
◦ The 16- bit segment registers (CS, DS, SS, ES, FS,
and GS).
Index
Register
General
Purpose Pointer
Register Register
Segment
Register
Flag Register of 80386: The Flag register of 80386 is a
32 bit register. Out of the 32 bits, Intel has reserved bits
D18 to D31, D5 and D3, while D1 is always set at 1.Two
extra new flags are added to the 80286 flag to derive the
flag register of 80386. They are VM and RF flags.
Six Conditional Flags
◦ Carry Flag (CF)
◦ Parity Flag (PF)
◦ Auxiliary Flag( AF)
◦ Zero Flag (ZF)
◦ Sign Flag (SF)
◦ Overflow Flag (OF)
Three Control Flags
◦ Interrupt Flag (IF)
◦ Trap Flag (TF)
◦ Direction Flag (DF)
Four System Flags
◦ Input/output privilege level (IOPL)
◦ Nested Task (NT)
◦ Resume Flag (RF)
◦ Virtual Mode Flag (VM)
• IOPL (Input/Output Privilege Level, bits 12-13)– IOPL is used in protected
mode operation to select the privilege level for I./O devices. IFthe current privilege
level is higher or more trusted than the IOPL, I/O executed without hindrance. If
the IOPL is lower than the current privilege level, an interruptoccurs.
• NT (Nested Task, bit 14) – The nested task flag is used to indicated that the
current task is nested within another task in protected mode operation. This flag is
when the task I nested by software.
• RF (Resume Flag, bit 16)– If this flag set, the 80386enters the virtual mode
within the protected mode. In this mode, if any privileged instruction is executed,
an exception 13is generated.
• VM (Virtual 8086 Mode, bit 17) -The VM bit provides Virtual 8086 Mode
within Protected Mode. If set while the 80386 is in Protected Mode, the 80386
will switch to Virtual 8086 operation, handling segment loads as the 8086 does,
but generating exception 13 faults on privileged opcode
5/16/2023 PCCOE,Pune
➢ VM - Virtual Mode Flag:
➢ Indicates operating mode of 80386.
➢ When VM flag is set, 80386 switches from protected mode
to virtual 8086 mode.
RF- Resume Flag: The RF flag temporarily disables
debug exceptions so that an instruction can be restarted
after a debug exception without immediately causing
another debug exception.
The RF is automatically reset after successful execution
of every instruction, except for IRET and POP
instructions.
NT (Nested flag) :
◦ This flag is set when one system task invokes another
task.(i.e. nested task).
IOPL (l/O Privilege level) :
◦ IOPL is used in protected mode operation to select the
privilege level for I/O devices. IF the current privilege
level is higher or more trusted than the IOPL, I/O
executed without hindrance. If the IOPL is lower than
the current privilege level, an interruptoccurs.
The 386 supports four types of descriptor table:
• Global descriptor table (GDT),
• Local descriptor table (LDT),
• Interrupt descriptor table (IDT), and
• Task state segment descriptor (TSS).
Four special registers are defined to hold the base address of
these tables
• Global descriptor table Register (GDTR),
• Local descriptor table Register (LDTR),
• Interrupt descriptor table Register (IDTR), and
• Task state segment descriptor Register (TR).
Protected Mode Memory addressing:
• Segment register now acts as selector
• An additional table called a descriptor table uses the
selector as an index to provide additional information
known as descriptor.
Control Register(32- bit)
Control Register 0 (CR0)
CR0 contains system control flags, which control or indicate
conditions that apply to the system as a whole, not to an
individual task (Also know as MSW).
➢ PE (Protection Enable bit 0)
➢ Setting PE causes the processor to begin executing in

protected mode. Resetting PE returns to real-address mode
(PE=1 System in protected mode else in real mode)
➢ MP (Math Present, bit 1)
➢ The MP (monitor coprocessor) bit controls the function of

wait instruction, which makes the processor to wait for the
completion of the task by math coprocessor.
➢ EM (Emulation, bit 2) EM=1 to cause all coprocessor opcodes

to generate a coprocessor not available fault (Exception 11)
Control Register 0 (CR0)
➢ TS (Task Switch, bit 3)
➢ Indicate task has been switched to 80387 (TS=1 numeric
coprocessor cause type7 interrupt).CLTS instruction
➢ ET (Extension Type, bit 4)
➢ ET indicates the type of coprocessor present in the system
(80287 or 80387 ) . (ET=0 select 80287; ET=1 select
80387)
➢ PG(Paging , bit 31)
➢ PG indicates whether the processor uses page tables to
translate linear adreess to physical address
Control Register
➢ Control Register 1 (CR1).
➢ reserved by Intel
➢ Control Register 2 (CR2)

➢ Read only register. The 80386 itself writes the last 32 bit
linear address of page fault routine in this register. When
page fault occurs , processor generates exception 14 (page
fault) .
➢ This address is important for writing page fault routine.
➢ Control Register 3 (CR3)

➢ Control register 3 hold the base address of page
directory
➢ It also called Page Directory Base Register(PDBR)
Debug Register
➢ The debug registers bring advanced debugging
abilities to the 80386, including data breakpoints and
the ability to set instruction breakpoints without
modifying code segments.
Debug Register
➢ Intel has provide a set of 8 debug registers for
hardware debugging. Out of these eight registers DR0 to
DR7, two registers DR4 and DR5 are Intel reserved.
➢ The initial four registers DR0 to DR3 store four
program controllable breakpoint addresses, while DR6
and DR7 respectively hold breakpoint status and
breakpoint control information.
➢ Breakpoint address may locate an instruction or
data.
Debug Register
Debug Address Register (DR0-DR3)
➢ Each of these registers contains the linear address
associated with one of four breakpoint conditions. Each
breakpoint condition is further defined by bits in DR7.
➢ The debug address registers are effective whether or
not paging is enabled. The addresses in these registers
are linear addresses.
Debug Status Register(DR7)
❖ The debug status register permits the debugger to
determine which debug conditions have occurred.
❖ For each address in registers DR0-DR3, the
corresponding fields R/W0 through R/W3 specify
the type of action that should cause a breakpoint. The
processor interprets these bits as follows:
00 -- Break on instruction execution only
01 -- Break on data writes only
10 -- undefined
11 -- Break on data reads or writes but
not instruction fetches
Debug Status Register(DR7)
❖ The LE and GE bits control the "exact data
breakpoint match" feature of the processor. If either
LE or GE is set, the processor slows execution so
that data breakpoints are reported on the instruction
that causes them. It is recommended that one of
these bits be set whenever data breakpoints are
armed. The processor clears LE at a task switch but
does not clear GE.
6.TestRegisters
• The test registers are not a standard part of the 80386
architecture. They are provided solely to enable confidence
testing of the translation
• lookaside buffer (TLB), the cache used for storing

information from page tables
TestRegisters
6.TestRegisters
6.TestRegisters
6.TestRegisters
6.TestRegisters
6.TestRegisters
Systems Instructions
Systems instructions deal with such functions as:
1. Verification of pointer parameters:
ARPL ── Adjust RPL
LAR ── Load Access Rights
LSL ── Load Segment Limit
VERR ── Verify for Reading
VERW ── Verify for Writing
2. Addressing descriptor tables:

LLDT ── Load LDT Register
SLDT ── Store LDT Register
LGDT ── Load GDT Register
SGDT ── Store GDT Register
3. Multitasking:
LTR ── Load Task Register
STR ── Store Task Register
4. Coprocessing and Multiprocessing:
CLTS ── Clear Task-Switched Flag ESC
── Escape instructions
WAIT ── Wait until Coprocessor not Busy
LOCK ── Assert Bus-Lock Signal
5. Input and Output:

IN ── Input
OUT ── Output
INS ── Input String
OUTS ── Output String
6. Interrupt control:
CLI ── Clear Interrupt-Enable Flag
STI ── Set Interrupt-Enable Flag
LIDT ── Load IDT Register
SIDT ── Store IDT Register
7. Debugging:
MOV ── Move to and from debug registers
8. TLB testing:
MOV ── Move to and from test registers
9. System Control:
SMSW ── Set MSW
LMSW ── Load MSW
HLT ── Halt Processor
MOV ── Move to and from control registers
• The instructions SMSW and LMSW are provided for compatibility with the
80286 processor. 80386 programs access the MSW in CR0 via variants of
the MOV instruction. HLT stops the processor until receipt of an INTR or
RESET signal.
Real, protected and virtual mode
Segmentation = memory management scheme
Segment = block of memory.
A logical address consists of:

• base address
• offset (relative address within the segment)
Real, protected and virtual mode
➢ Advantages of the segmentation
• shorter addressing part of the instruction (only the
offset of the operand is encoded in the instruction,
the base address is in a base register)
• instructions are separated from data
➢ Segment types
code segment – holds machine instructions
data segment
stack segment – holds: o return addresses,
parameters and local variables of procedures,
temporary results of mathematical operations
Real mode
Processor 8086 – works only in real mode.
20-bit address bus => memory ??
Offset ... 16-bit value =>
Protected mode
32-bit address bus => memory??
Offset ... 16-bit or 32-bit value
Linear address = base address + offset
Virtual mode
• Processor runs in protected mode, but simulates real
mode: a 20-bit linear address is translated by paging
to a 32-bit physical address.
• A processor is switched to virtual mode when
running a DOS application under Windows operating
system
Memory
Management
Memory Management
➢ The 80386 transforms logical addresses (i.e.,
addresses as viewed by programmers) into physical
address (i.e., actual addresses in physical memory)
in two steps:
➢ Segment translation, in which a logical address
(consisting of a segment selector and segment offset)
are converted to a linear address.
➢ Page translation, in which a linear address is
converted to a physical address. This step is optional,
at the discretion of systems-software designers.
Memory Management
Segment Translation
➢ To perform this translation, the processor uses the
following data structures:
➢ Descriptors
➢ Descriptor tables
➢ Selectors
➢ Segment Registers
Segment Translation
Segment Translation
➢ Segment register contains a selector that
selects a descriptor from the descriptor table.
➢ The descriptor contains information about the
segment, e.g., it's base address, length and access
right
➢ The offset can be 32-bits.
Segment Selector – 16 bit
A segment selector is loaded into a segment register (cs,
ds, etc.) to select one of the regular segments in the
system as the one addressed via that segment register.
Segment Descriptor – 64 bit
Segment Descriptor
➢ Base Address: Starting address of the memory
segment
➢ Limit:
• Length of the segment minus 1.
• 20-bits allows segments up to 1 MB.
• This value is shifted by 12 bits to the left when the
G (Granularity bit) is set to 1.
➢ G (Granularity) Bit:
When G=0, segments can be 1 byte to 1MB in length.
When G=1, segments can be 4KB to 4GB in length.
Segment Descriptor
➢ U bit:
User (OS) defined bit.
➢ X Bit:
Reserved by Intel
➢ D bit:
Indicates how the instructions (80386 and up) access
register and memory data in protected mode.
▪ When D=0, instructions are 16-bit instructions,
with 16-bit offsets and 16-bit registers. Stacks are
assumed 16-bit wide and SP is used.
▪ When D=1, 32-bits are assumed. Allows 8086-
80286 programs to run
Segment Descriptor(Access Right byte)
Types of Segment Descriptor
Non System Descriptor
S=1
Non System
System Descriptor
S=0
Type Defines Type Defines
System 0 Reserved by Intel 8 Reserved by Intel
Descripors 1 Available 80286 TSS 9 Available Intel 80286

TSS
2 LDT A Undefined
3 Busy 80286 TSS B Busy Intel 80386DX
4 80286 Call Gate C Intel 80386DX Call
gate
5 Task Gate D Undefined
6 80286 Interrupt Gate E 80386DX Interrupt
Gate
7 D8e0p2a8rt6mTernatpoGf aCto
e mputer F 80386DX Trap Gate
Descriptor Tables
➢ U bit:

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FEATURES OF 80386:

Two versions of 80386 are commonly available:

3) Address 4GB of memory 2) 16 MB of memory

The BIU connects the peripheral devices through the memory

The sequence in which the instructions are fetched and gets

Requires the resetting of the microprocessor in order to

➢ Setting PE causes the processor to begin executing in

➢ The MP (monitor coprocessor) bit controls the function of

➢ EM (Emulation, bit 2) EM=1 to cause all coprocessor opcodes

➢ Control Register 2 (CR2)

➢ Control Register 3 (CR3)

• lookaside buffer (TLB), the cache used for storing

2. Addressing descriptor tables:

5. Input and Output:

A logical address consists of:

Offset ... 16-bit value =>

Linear address = base address + offset

System 0 Reserved by Intel 8 Reserved by Intel

Descripors 1 Available 80286 TSS 9 Available Intel 80286

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