1. Draw the schematic diagram of the architecture of a single bus CPU, clearly showing the general purpose, Special purpose registers and the data path. Explain the function of each component. 2. Explain the working principle of DRAM cell 3. Write different mapping techniques in cache with their merits and demerits. 4. Write the sequence of control steps required for single bus CPU organization of the following instruction ADD R1, NUM
Set2- NNM23CS193 to NNM23CS205
5. Implement the LRU algorithm on the following data. Assume cache size is 3 blocks. 1,1,2,3,3,4,5,1,2,5 6. Write the sequence of control steps for the following instruction for multi bus CPU organization ADD (R1), R2 // R2←[R1]+R2 7. Design a 4M X 32 bits memory using 512X8 bits memory chip 8. A cache consists of a total of 128 blocks. The main memory contains 2K blocks, each consisting of 32 words. ( I )How many bits are there in each of the TAG, BLOCK and WORD field in case of direct mapping? ( ii )How many bits are there in each of the TAG, SET, and WORD field in case of 4-way set-associative mapping?
Set 3- NNM23CS205 to NNM23CS217
9. Explain the working principle of Hardwired control unit design along with neat diagram. Explain its advantages and disadvantages 10. What is the difference between memory access time and memory cycle time? 11. What is the need of locality of reference? Explain about the different types of locality of references 12. Draw and explain the working principle of microprogrammed control unit.
Set 4- NNM23CS218 to NNM23CS229
13. Differentiate between DRAM and SRAM
14. Define the role of cache memory in memory organisation. Why we use the mapping function? Specify the different mapping function name. 15. Find out the number of page fault in the following strings of pages used by CPU using the page replacement algorithm LRU and LIFO [taking 3 page frames] 1,1,3,5,3,4,2,2,2,1,8 16. What is virtual memory ? Discuss the virtual memory organization.
Set 5- NNM23CS230 to NNM23CS293
17. Illustrate the address translation mechanism in virtual memory. Explain the role of TLB. 18. Memory mapped I/O VS I/O mapped I/O 19. How does the processor resolvs among simultaneous interrupt requests? Set 6- DIP24CS19 to DIP24CS25
20. What is the vectored interrupt technique of performing I/O operation?
21. Explain Direct Memory Access method with it's requirement 22. Explain Program-Controlled I/O technique. Why interrupt driven I/0 is more advantageous over it?
