8086 Microprocessor

SUBHAJIT BHOWMICK
 Microprocessor Fifth Generation Pentium

Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology ⇒ Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors ⇒ 40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology ⇒ Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors ⇒ 40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors ⇒ 16 pins nesting
8 and 16 bit processors ⇒ 40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are 2
multiplexed Intel 8085 (8 bit processor)
8086 Microprocessor
Overview

First 16- bit processor released by

INTEL in the year 1978

Originally HMOS, now manufactured

using HMOS III technique

Approximately 29, 000 transistors, 40

pin DIP, 5V supply

Does not have internal clock; external

asymmetric clock source with 33% duty
cycle

20-bit address to access memory ⇒ can

address up to 220 = 1 megabytes of
memory space.

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8086 Microprocessor
Architecture

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
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8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Dedicated Adder to generate

20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Segment Registers >> 7

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SEGMENT16 FFFFF
F0000
SEGMENT15 EFFFF
E0000
SEGMENT14 DFFFF
D0000
SEGMENT13 CFFFF
C0000
SEGMENT12 BFFFF
B0000
SEGMENT11 AFFFF
A0000
SEGMENT10 9FFFF
90000
SEGMENT9 8FFFF
80000
SEGMENT8 7FFFF
EXTRA SEGMENT 70000
SEGMENT7 6FFFF
60000
SEGMENT6 5FFFF
STACK SEGMENT 50000
SEGMENT5 4FFFF
40000
SEGMENT4 3FFFF
CODE SEGMENT 30000
SEGMENT3 2FFFF
DATA SEGMENT 20000
SEGMENT2 1FFFF
10000
SEGMENT1 0FFFF 9
00000
SEGMENT16 FFFF (OFFSET ADDRESS) 64 KB
F000 0000
SEGMENT15 FFFF (OFFSET ADDRESS) 64 KB
E000 0000
SEGMENT14 FFFF (OFFSET ADDRESS) 64 KB
D000 0000
SEGMENT13 FFFF (OFFSET ADDRESS) 64 KB
C000 0000
SEGMENT12 FFFF (OFFSET ADDRESS) 64 KB
B000 0000
SEGMENT11 FFFF (OFFSET ADDRESS) 64 KB
A000 0000
SEGMENT10 FFFF (OFFSET ADDRESS) 64 KB
9000 0000
SEGMENT9 FFFF (OFFSET ADDRESS) 64 KB
8000 0000
7000 FFFF (OFFSET ADDRESS) 64 KB
EXTRA SEGMENT 0000
SEGMENT7 FFFF (OFFSET ADDRESS) 64 KB
6000 0000
SEGMENT6 FFFF (OFFSET ADDRESS) 64 KB
5000 0000
SEGMENT5 FFFF (OFFSET ADDRESS) 64 KB
4000 0000
CODE SEGMENT FFFF (OFFSET ADDRESS) 64 KB
3000 0000
DATA SEGMENT FFFF ( OFFSET ADDRESS) 64KB
2000 0000
SEGMENT 2 FFFF (OFFSET ADDRESS) 64 KB
1000 0000
SEGMENT 1 FFFF (OFFSET ADDRESS) 64 KB
0000 0000 10
2000:0000
Segment address: Offset address(start)
2000:FFFF
Segment address: Offset address(end)

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 8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment
Registers

• 8086’s 1-megabyte • The 8086 can directly • Programs obtain access

memory is divided address four segments to code and data in the
into segments of up (256 K bytes within the 1 segments by changing
to 64K bytes each. M byte of memory) at a the segment register
particular time. content to point to the
desired segments.

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8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Code Segment Register

Registers
•16-bit

•CS contains the base or start of the current code segment; IP

contains the distance or offset from this address to the next
instruction byte to be fetched.

•BIU computes the 20-bit physical address by logically shifting

the contents of CS 4-bits to the left and then adding the
16-bit contents of IP.

•That is, all instructions of a program are relative to the

contents of the CS register multiplied by 16 and then offset is
added provided by the IP.

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8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Data Segment Register

Registers
•16-bit

•Points to the current data segment; operands for most

instructions are fetched from this segment.

•The 16-bit contents of the Source Index (SI) or Destination

Index (DI) or a 16-bit displacement are used as offset for
computing the 20-bit physical address.

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8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Stack Segment Register

Registers
•16-bit

•Points to the current stack.

•The 20-bit physical stack address is calculated from the Stack

Segment (SS) and the Stack Pointer (SP) for stack
instructions such as PUSH and POP.

•In based addressing mode, the 20-bit physical stack address

is calculated from the Stack segment (SS) and the Base
Pointer (BP).

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8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Extra Segment Register

Registers
•16-bit

•Points to the extra segment in which data (in excess of 64K

pointed to by the DS) is stored.

•String instructions use the ES and DI to determine the 20-bit

physical address for the destination.

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8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Instruction Pointer

Registers
•16-bit

•Always points to the next instruction to be executed within

the currently executing code segment.

•So, this register contains the 16-bit offset address pointing to

the next instruction code within the 64Kb of the code
segment area.

•Its content is automatically incremented as the execution of

the next instruction takes place.

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8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Instruction queue

• A group of
First-In-First-Out (FIFO)
in which up to 6 bytes of
instruction code are pre
fetched from the memory
ahead of time.

• This is done in order to

speed up the execution
by overlapping
instruction fetch with
execution.

• This mechanism is known

as pipelining.

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8086 Microprocessor
Architecture Execution Unit (EU)

EU decodes and
executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 19
DX can be used as DH and DL
8086 Microprocessor
Architecture Execution Unit (EU)

EU Accumulator Register (AX)

Registers
•Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.

•AL in this case contains the low order byte of the word, and
AH contains the high-order byte.

•The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

•Multiplication and Division instructions also use the AX or AL.

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8086 Microprocessor
Architecture Execution Unit (EU)

EU Base Register (BX)

Registers
•Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.

•BL in this case contains the low-order byte of the word, and
BH contains the high-order byte.

•This is the only general purpose register whose contents can

be used for addressing the 8086 memory.

•All memory references utilizing this register content for

addressing use DS as the default segment register.

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8086 Microprocessor
Architecture Execution Unit (EU)

EU Counter Register (CX)

Registers
•Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

•When combined, CL register contains the low order byte of

the word, and CH contains the high-order byte.

•Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.

Example:

The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.

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8086 Microprocessor
Architecture Execution Unit (EU)

EU
Registers

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8086 Microprocessor
Architecture Execution Unit (EU)

EU Stack Pointer (SP) and Base Pointer (BP)

Registers
•SP and BP are used to access data in the stack segment.

•SP is used as an offset from the current SS during execution

of instructions that involve the stack segment in the external
memory.

•SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH instruction.

•BP contains an offset address in the current SS, which is used

by instructions utilizing the based addressing mode.

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8086 Microprocessor
Architecture Execution Unit (EU)

EU Source Index (SI) and Destination Index (DI)

Registers
•Used in indexed addressing.

•Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.

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8086 Microprocessor
Architecture Execution Unit (EU)

EU Source Index (SI) and Destination Index (DI)

Registers
•Used in indexed addressing.

•Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.

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5000:2050
SEGMENT ADDRESS:OFFSET ADDRESS

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8086 Microprocessor
Architecture Execution Unit (EU)
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction

Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 31
2235: 0010 0010 0011 0101
6F24: 0110 1111 0010 0100

0010 0010 0011 0101

+0110 1111 0010 0100
---------------------------
1001 0001 0101 1001

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8086 Microprocessor
Architecture

8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

into 4 groups OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

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8086 Microprocessor
Architecture Registers and Special Functions

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic

operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic

operations

BX Base register Used to hold base value in base addressing mode

to access memory data

CX Count Register Used to hold the count value in SHIFT, ROTATE

and LOOP instructions

DX Data Register Used to hold data for multiplication and division

operations

SP Stack Pointer Used to hold the offset address of top stack

memory

BP Base Pointer Used to hold the base value in base addressing

using SS register to access data from stack
memory

SI Source Index Used to hold index value of source operand (data)

for string instructions

DI Data Index Used to hold the index value of destination

operand (data) for string operations 34
 8086

MEMORY BANK
The 8086’s 1MByte memory address space is divided in to two independent 512
KByte banks: the low (even) bank and the high (odd) bank.
Address bits A1 through A19 select the storage location that is to be accessed.
They are applied to both banks in parallel.
A0 pin and Bus high enable (BHE) pin are used as bank-select signals.

BHE AO PROCESSING
0 0 BOTH BANKS ACTIVE 16 BIT WORD(data transfer through D0-D15
lines)
0 1 Only high bank active (data transfer through D8-D15 lines)
1 0 Only low bank active (data transfer through D0-D7 lines)
1 1 NO bank active

00000 00001
00002 00003
00004 00005
00008 00009
10000 10001
20000 20001
40000 80001 36
FFFFE FFFFF
When a byte of data at an even address (such as X) is
to be accessed

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• A0 is set to logic 0 to enable the low
bank of memory.
• BHE is set to logic 1 to disable the
high bank.

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When a byte of data at an odd address (such as X+1)
is to be accessed

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• A0 is set to logic 1 to disable the low
bank of memory.
• BHE is set to logic 0 to enable the
high bank.

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When a word of data at an odd address (misaligned
word) is to be accessed

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• During the first bus cycle, the odd
byte of the word (in the high bank) is
addressed
• A0 is set to logic 1 to disable the low
bank of memory
• BHE is set to logic 0 to enable the
high bank.

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• During the second bus cycle, the odd
byte of the word (in the low bank) is
addressed.
• A0is set to logic 0 to enable the low
bank of memory.
• BHE is set to logic 1 to disable the
high bank.

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