SIGNAL CONVERSION AND PROCESSING

Digital to Analog (D/A): A digital-to-analog converter (D/A) performs the function of DECODING on a
digital-coded input. The output of the D/A converter is an analog signal, usually in the form of a current
or a voltage. A D/A is needed as an interface between a digital channel or digital computer and an analog
device. A D/A is also known as a DECODER.

Analog to Digital Convertor Converter (A/D). An analog-to-digital converter (A/D) is a device

which converts an analog signal to a digital-coded signal. The device is necessary as an interface
between an analog system or component whose output is to be processed by a digital processor
or computer.
Sample-and-Hold (S/H). A sample-and-hold (S/H) is used for many purposes in discrete-data
and digital systems. A S/H makes a fast acquisition of an analog signal and then holds this signal
at a constant value until the next acquisition (sample) is made. We shall show later that S/H is an
integral part of an A/D converter.
Multiplexer. When signals from several sources are to be processed by the same processor or
communication channel, a multiplexer is used to couple the signals to the processor in some
prescribed sequence. This way, the processor is time-shared by all the incoming signals. For
example, if several digital-data sources are to be processed by a central computer unit, these
input signals are usually coupled to the computer by a multiplexer through a common set of
parallel lines.

DIGITAL SIGNALS AND CODING

Each of the binary digits (0 or 1) is referred to as a bit. The bit itself, however, is too small a number to be
considered the basic unit of information. Typically, bits are strung together to form larger, more useful
units; with 8 bits placed together to form a byte. Several of these 8-bit bytes may be placed together to
form a word.

Digital signals in a computer can be represented as fixed-point numbers or floating-point numbers. These
number systems are discussed as follows.

In general, an n-bit binary word representing a fixed-point integer number N is written as

where the coefficients ai' i == 0,1,2, ... ,n - 1 are either 0 or 1.

Let us consider a three-bit binary word,

Thus, for instance, the binary number 01011.101 is equivalent to the decima number
Negative numbers may be represented by assigning the first bit of the binary word as a sign bit; i.e., 0 for
"+" and 1 for "-".

DATA CONVERSIONS AND QUANTIZATION

In D/A and A/D conversions the MSB and the LSB and the weight of each bit in a digital-coded
word are important in the understanding of the conversion process. For a three-bit binary
fractional code the MSB has a weight of 1/2 of full scale (FS); the second bit has a weight of 1/4
FS; and the LSB has a weight of 1/8 FS. For an n-bit binary fractional code the MSB still has a
weight of 1/2 FS, but the LSB has a weight of 2-n FS.
 Fig. 2-7 illustrates the resolution of 2 -3 = 1/8 of a three-bit binary fractional code. The LSB in
this case is 1/8 and full scale is 1. Resolution may be improved by using more bits.
One of the major operations in the. A/D conversion is quantization. Since the digital output can
assume only a finite number of levels, it is necessary to quantize or round off the analog number
into the nearest digital level.
As shown in Fig. 2-8, the analog signal has decision levels at the values of 0.5q, 1.5q, 2.5q, ... ,
6.5q. In other words, the digital output number D is related to the analog number A through the
relationships shown in Table 2-3. The parameter q which is equal to the least significant bit
(LSB) is known as the quantization level. For this three-bit digital word, the LSB is 1/8 FS, as
indicated in Table 2-4. The difference between the analog signal and the digital output is called
the quantization error. The quantization error in general depends upon the number of
quantization levels or the resolution of the quantizer. Figure 2-8 shows that the quantization error
is zero when the analog signal value is equal to an integral multiple of q before reaching
saturation. In general, the maximum quantization error is ±q/2 before reaching saturation.
One important aspect with respect to the saturation level of the quantization process, as depicted
in Fig. 2-8 and Table 2-4, is that the maximum digital output, which corresponds to the binary
number 111, is 7/8 FS, not FS. This would not have any effect on the accuracy of the A/D
conversion as long as the values of the analog inputs do not exceed 7/8 FS + q/2, since under this
condition the maximum quantization error will be bounded by ±q/2. For instance, if the full-scale
reference voltage of a three-bit digital conversion process is set at 10 volts, referring to Fig. 2-8,
FS = 10 volts;

Then, the maximum value of the analog signal that the quantizer can convert without exceeding
the quantization error of ±0.625 volt is

SAMPLE-AND-HOLD DEVICES

A sampler in a discrete-data or digital system is a device which converts an analog signal into a train of
amplitude-modulated pulse or a digital signal.

Sample-and-hold devices are used extensively in digital systems. The main applications of sample-and-
hold is to "freeze" fast-moving signals during all types of conversion operations. Another common usage
of S/H is for the storage of multiplexer outputs while the Signal is being converted. The opening and
closing of the switch or sampler is controlled by a SAMPLE COMMAND.
When the switch is closed the S/H output samples and TRACKS the input signal e s(t). When the switch is
opened, the output is held at the volt age that the capacitor is charged to. Figure 2-10 illustrates typical
input and output signals of the simple S/H shown in Fig. 2-9 when the source resistance is zero.

The time interval during which the sampler is closed is called the sampling duration p. In practice, the
resistance Rs is not zero, and the capacitor will charge toward the sampled input signal with a time
constant RsC. Furthermore, the operation of the sampler is not instantaneous as it would take time for It to
respond to the sample-and-hold commands.

In practice a sample-and-hold has many imperfections and errors, and the output of the device may
deviate considerably from the Ideal waveform illustrated in Fig. 2-10.
Figure 2-11 illustrates a typical input signal es(t) and the corresponding S/H output of a practical S/H. The
typical output signal of the S/H is characterized by several sources of time delays and imperfect holding
during the hold mode. These characteristics are illustrated in Fig. 2-11 and are defined m the following.

Acquisition Time (Ta): When the SAMPLE COMMAND is given to the S/H the unit does not begin
to track the input signal instantaneously. The acquisition time is measured from the instant SAMPLE
COMMAND is given to the time when the output of the S/H enters and remains within a specified error
band (say ± 1 %) around the input signal.

Aperture Time (T): When the HOLD command is given to the sample-and hold while it is in the
sample (track) mode, it will stay in the sample mode before reacting. The time between the issuance of
the HOLD command and the time the sampler is opened is called the aperture time. For example, the
aperture time of a typical commercial S/H unit may be on the order of 10 nanoseconds.

Settling Time (Ts): In switching from the sample mode to the hold mode, transient caused by
capacitance feedthrough from the digital logic circuitry through the electronic switch to the analog signal
path can occur. The time required for the transient oscillation to settle to within a certain percent of FS is
called the settling time.

Hold Mode Droop: During the HOLD mode the output voltage of the S/H may decrease slightly, due
to the leakage currents with the FET switch and the buffer amplifier of the input circuit.
The droop in the output of the S/H can be greatly reduced by using a buffer amplifier with a very high
input impedance at the output of the S/H. Similarly, we may use an input buffer amplifier so as to keep
the input current of the S/H relatively constant.

In digital systems the sample-and-hold operation is often controlled by a periodic clock.

Figure 2-13 illustrates a uniform-rate sample-and-hold operation. Both the actual and the ideal S/H
outputs are shown for the given input analog signal. The time duration between the sample commands is
called the sampling period.

System Block Diagram Representation of S/H

The sample-and-hold is available commercially as one unit. Figure 2-15 illustrates an equivalent block
diagram which isolates the sample-and-hold functions and the effects of all the delay times and transient
oscillations.
The sampler which can be regarded as a pulse-amplitude modulator has a pulse or sampling duration of p.
The hold device simply holds the sampled signal during the holding periods. The pure time delay, Td ,
approximates the acquisition time and the aperture time delays, whereas the filter is for the representation
of the finite time constant and dynamics of the buffer amplifiers. In general, the transfer function of the
filter can be expressed as

The delay times of the S/H are also comparatively small so that these can also be neglected from the
standpoint of the system dynamics. For example, the aperture time may be only 10 nanosec, and the
acquisition time is 300 nanosec, of a given S/H. The settling time may be another 100 nanosec; i.e., the
transient oscillations will decay to a prescribed accuracy within 100 nanosec. Thus, the total time delay is
only 410 nanosec, which may be neglected. Therefore, for all practical purposes, if p«T, and the time
delay due to sample-and-hold is small, the S/H can be modelled by the block diagram shown m FIg. 2-16.

In this case the sampler is called an ideal sampler since it is assumed to have a zero sampling duration;
that is, p = 0.
DIGITAL-TO-ANALOG (D/A) CONVERSION

The basic elements of a D / A are represented by the block diagram shown in Fig. 2-18. The function of
the logic circuit is to control the switching of the precision reference voltage or current source to the
proper in put terminals of the resistor network as a function of the digital value of each digital input bit.

The function of the logic circuit is to control the switching of the precision reference voltage or current
source to the proper in put terminals of the resistor network as a function of the digital value of each
digital input bit.

When a binary 1 appears at the control logic circuit of a switch it closes the switch and connects the
resistor to the reference voltage. On the other hand, a binary 0 connects the resistor to ground. For the
high-gain operational amplifier the input impedance is very low so that the voltage at the summing point
0 is practically zero.
The main disadvantage of the weighted-resistor type of D/ A shown in Fig. 2-19 is that the accuracy and
stability of the conversion depend on the accuracy and temperature stability of the resistors. A more
practical D/A is the R -2R ladder network. Figure 2-20 illustrates a D/A of this type for a three-bit digital
word. Since all resistors have values of either R or 2R, they are easy to match and select.
Sampling Process Modelled as a Pulse-Amplitude Modulator
For an input signal f(t) which is a function of the continuous-time variable t, the output of the sampler,
designated as f*p(t), is a train of finite-width pulses whose amplitudes are modulated by the input f(t).
Figure 2-30 shows an equivalent block diagram representation of the sampler as a pulse-amplitude
modulator. In this case, the input f(t) is considered to be multiplied by a carrier signal p(t) which is a train
of periodic pulses, each with unit height. Figure 2-31 illustrates the typical waveforms of the input signal
f(t), the carrier signal p(t), and the output f*p(t).

There are sampling operations which may be described by a pulse width modulation (PWM) sampler.
Typical input and output signals of a pulse width modulator are illustrated in Fig. 2-32. A still more
elaborate scheme is one in which the amplitudes as well as the widths of the output pulses vary as some
function of the input signal at the sampling instants. This type of sampler is known as a Pulse width-
pulse-amplitude modulator.
For the uniform-rate finite-pulse width sampler described in Figs. 2-29, 2-30 and 2-31, the output signal
in response to an input f(t) can be regarded as the product of f(t) and the carrier p(t) which is a unit pulse
train with period T. The unit pulse train p(t) contains pulses each with unit magnitude. Thus, p(t) can be
expressed as
In the present case we assume that the sampling operation begins at t = -α and the leading edge of the
pulse at t = 0 coincides with t = 0, as shown in Fig. 2-33.

The output of the sampler is written as

Substituting Eq. (2-31) into Eq. (2-33), we get,

Equation (2-34) gives a time-domain description of the input-output relation of the uniform-rate finite-
pulse width sampler.

Representation as an Infinite Impulse Train in the Time Domain:

The Ideal sampler reproduces in its output the spectrum of the continuous input f(t) as well as the
complementary components at integral multiples of the sampling frequency, and all components have the
same amplitude of 1/T.
Assuming that the amplitude spectrum of the continuous input signal is as shown in Fig. 2-38(a), the
corresponding amplitude spectrum of the sampled signal f*(t) when ωs > 2ωc is shown in Fig. 2-38(b),
where ωs is the sampling frequency and ωc is the highest frequency contained in f(t). Again, if the
sampling frequency is less than 2ωc, distortion will occur in the output spectrum because of the
overlapping of the sidebands in |F*(jω)| .
Ideal Sampling