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Extraction &OFM — LowPower | Physical Design Vis Interview Questions viatnvsy ne | Aten | Recommended eo | Paper | vs | ~ Used to estimate the interconnect wire delay during pre-layout in a design eycle + Wite load information is based on statistics from physical layout parasitic + Information from the statistics is used in both conservative and aggressive tables + The conservative tables are based on “mean valuc” plus 3-sigm; the aggressive tables on “mean value” plus I-sigma, + Different for different technology. + Wire load models are approximated from one technology to another based on scaling factors. ‘Due to these approximations, he accuracy ofthese models diminish over multiple technology nodes + Deseribes effect of wire length and fanout on + Resistance © Capacitance © Area of the nets, + Allatsibutes (R, C and Area) are given per unit length wire + Slope value is used to characterize linear fanout. + Basically a set of tables «+ Net fanout vs load + Net fanout vs resistance + Net fanout vs area ‘One example of such type of table is Nat] Resistance | Capacitance Fanout | Ka DE T | e004 | o00s12 Z| nraes_| 0.00812 3 [ ono] oars 4 [oozes [ort Asper this In above circuit - The RC value is estimated and represented as per WLM, ‘The following are few snepshot ofthe different format of wire load model ie_Joad("WLMI") resistance © 0.0006, ->R per unit length capacitance : 0.0001 > C per unit length xy Google Send feedback | Why hs 36? © area 0.1 po Area per unit length slope 15 > Used fr linear extrapolation 12,763,707 Peon Pe Imegirayes secon sean a Sora (St Sateen ‘wc rmrgany ccinjenee Borat Tora artes iS ety ee Le (Giajomecteans ety eta Sa eora pees (CamanoVLSIBanle STASI Extraction BOF Low Power | PhyicalDesign Visi lterviow Questions Video Lectures | Vishny nit | atetue | Remmi eo | Pape | vs | HENNE VOT, anout_length(4, 0.015); fanout_length(S, 0.020); fanout_length(7, 0.028); fimnout_length(8, 0.030); fanout_length(9, 0.035); fanout_length(10, 0,040); ) -> at fanout “7” length of the Toad"WLM2") { fanout_Jength( 1,1) fanout_length( 2,2); fanout_capacitancet 1, 0.002 ; fmout_eapacitance( 2, 0.004 j; fanout_capacitancet 3, 0.006 fanout_capacitancet 4, 0.008 ); fanout capacitance 5, 0.010 ); {fanout_eapacitance( 6, 0.013 ) fanout_eapacitance( 7, 0.015 j; fanout_eapacitance( 8, 0.019 ) fanout_eapacitancet 9, 0.023 ) fanout_eapacitance( 10, 0.027); fanout resistance 1, 0.01 ); fanout_resistance( 2, 0.015}; fanout_resistance( 3, 0.022 }: fanout_resistance( 4, 0.026 ); £mout resistance 5, 0.030 ); fanout_resistance( 6, 0.035 ); fanout_resistance( 7, 0.039 }: fanout_esistance( 8, 0.048 ): fanout_resistance{ 9, 0.057 fnout_resistance( 10, 0.06 fanout_area( 1, 0.11); fanout_area( 20, 2.20 ); ) Here — ‘Area, Resistance and Capacitance are in per unit length of the interconnect. ‘The slope is the extrapolation slop to be used for data points that are not specified inthe fan-out length table. ox Bihl+Wiedemann ‘Simple solutions are often the best - AS Interface solutions from Bihl+Wiedemat Bihl+Wiedemann GmbH Learn In general, not all fanouts are mentioned in a given WLM lookup table, For example, in above WLM1 and WLM2 lookup table, capacitance and resistance values for fanouts 1, 2,3, 4, $,7, 8,9, 10s given. If we want to estimate the values at fanouts in the gaps (e.g. trom 6) or outside the fanout range specified in the table (e.g Fanout 20), we have to calculated those value using (iear) interpolation and extrapolation. For WLML For Fanout=20Home | VLSIBasic STABSI Extraction AOFM Low Power | PhysicalDesign Vater Questions Video Lectures visio ne | ateatue | Recommend eo | Pape | vs be | Capacitance = x Capacitance value per unit length [Net length = 0.040 + 10 x 1.5 (slope) = 15.04 > length of net with fanout of 20 Resistance = 15,04 x 0,0006 ~ 0.009024 units Capacitance = 15.04 x 0.0001 = 0,001504 units For Fanout=6 Since i's between 5 and 7 and corresponding fanout Vs length is available, we can do the interpolation Net length Resistance (net length at fanout 5) + (net length at fanout 7)) /2 new calculated Net length at fanout 20> x Resistance value per unit length Capacitance = x Capacitance value per unit lengih [Net length = (0,0020 + 0,0028)/2=0,0048)/2=0.0024 Resistance = 0,0024 x 0.0006 = 0.00000144 units > length of net with fanout of 6 (Capacitance = 0.0024 x 0.0001 ~ 0.00000024 units In the similar way we can caleulate the WLM for any no of fanout value, WLMs are often used in pre-placement optimization to drive speedups of critical paths. Since timing-driven placement plausibly makes nets on critical paths shorter than average, some optimisin may be incorporated into the WLM. Thus, a WLM may actually cousist of more than one lookup table, with each table corresponding to a different optimism level. There are several ways to incorporate the optimism level. If we use the WLMs that ccome from the (ASIC vendor's) design library, usually there are several tables from which we ean select. We ean also increase the optimism level of « WLM by multiplying all values in the WLM by some factor less than 1.2 For example, we ean use 0.25, 05, of 0.75, WLM Types For flows that run iming-based logic optimization before placement, there are three basi types of WLM tat can be use +.Statisticl WEMs «Are based on averages over many similar designs using the same or similar physical libraries, 2. Structural WLMs « Use information about neighboring nets, ater than just fanout and mode size information 2.Custom WLMs « Are based on the curent design afer placement and routing, but before the cument iteration of replacement synthesis, [Now the Question is: Where do the wire load models come from? Normally the semiconductor vendors will develop the modets AS-Interface Simple solutions are often the best - AS: Interface solutions from Bihl+Wiedemar Bihl+Wiedemann GmbH ASIC veudors typically develop wircload models based on statistical information taken from a variety of ‘example designs. For all the nets with a particular fanout, the number of nets with a given capacitance is plotted as a histogram. A single eapacitance Value is picked to represent this fanout value in the wireload model. Ifa very conservative wireload model is desired, the 90% decile might be picked (i.e. 90% of the nets inthe sample have a capacitance smaller than that value),Home | VLSIBasic STABS! Extraction AOFM Low Power | PhysicalDesign Vater Questions Video Lectures visti ne | Aten | Recommend Bec | Pape | vs | In this example 90% of nets have a capacitance smaller then 0.198pf. So in the WLM table, you will notice that fanout_eapacitance( 3, 0.198 ) la statistics are gathered for resistance and net ares. Usually the vendor supplies a family of wireload models, each to be used for a different size design. This is called area-based wireload selection ‘ew Advance concepts: Till now we have discussed that for a particular Net you can estimate the RC value as per the WLM. Let me ask you one question. What if your design is hierarchical? Do you think even in that ease you can use the same WLM for a particular net whieh is crossing the hierarchical boundaries? Short ANS is: you ean use it but you will lose the accuracy. Just to solve this problem, Vendors usually supplies multiple WLMs. There ate different Modes for WLM analysis- few important are: WLM analysis has three modes: 1. Top: «+ Consider the design a it has no hieroeracy and use the WLM for the top module to caleulate delays forall modules. «Any low level WEM is ignored 2.Enelosed: + Use the WLM of the module which completely encloses the net to compute delay for that net. 8. Segmented: + Ifa net goes across several WLM, use the WLM that corresponds to that portion ofthe net whieh it encloses only. untied (Previous) nex undetned et Pasay Relea 6 Sa 30 comments: =e say Anonymous foi 20°23 aay ting fre es ne ely