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Real Time Issues and Process of Fixing

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238 views7 pages

Real Time Issues and Process of Fixing

Uploaded by

RA NDY
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Documentation on Real time Issues and process of fixing

(7nm &28nm)
REAL-TIME SCENARIOS

Min sequential issue at CTS stage

Issue: Got a problem related to frequency(min sequential period) i.e before 1ns was the design
time period and after due to some constraints issue top level leads changed the frequency from
1ns to 0.8ns due to that issue popped up at the macro clock pins. We have an issue of not getting
the clock properly at the clock pin of the macro.(violation : 0.176ps)

Macro

clk

Clk gater buf 1 buf 2

Fixing:

Case 1: I tried to to upsize the logic level one (buff 2) from macro but some moderate change in
the value 166ps.and again I had tried the logic level 2 (buff 1) from the macro no change in the
value.

Case 2: now my I had tried upsize the clock gater. Before that I have to check the clock gater
flavour cells by using the command

## get_lib_cells /*CLK_GAT*

It show only X8 & X16. Preferred X8 change cell I had done .now the issue got resolved.

ecoChangecell -cell_name <name> -buffer list

total no of violation I got 32 each cell I had done change cell method.
Placement stage:

PIN EDITOR
 Performed pin editor to see the block worst-case timing and congestion
 I had done experimental i.e. setting the ports to the left side to see the connectivity
and timing-related violation.
 After one iteration I have seen DRC vio i.e. shorts.
 Didn’t get any timing and congestion issues.
TIMING DEBUG
 Next I had analysed the timing by using the timing debugging technique
 Three paths are violating but Those paths are showing UNCONNECTED in the
reports.
 I had seen the launch,data & capture paths by tracing the report.
 Below screenshots show the
 By tracing the report I had analyzed the schematic view.
 Below snippet shows the highlighted path.
 By analyzing the timing debug option we can see the constraining part related to report.

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