Unit-II: Processor Organization and Architecture

• CPU Architecture
• Register Organization
• Instruction cycle
• Instruction Formats

• Control Unit Design-

• Hardwired and Micro-programmed Control
• Vertical and Horizontal Micro-Instructions
• Nano-programming
• Comparison between CISC and RISC architectures
Difference Between computer architecture and organization
Computer Architecture Computer Organization
• Functional description of requirements and design • operational units and their interconnections that
implementation of various parts of computer implement the architecture specification.
system
• deals with the functional behavior of computer • deals with how the components of a computer
systems. system are arranged and how they interact to
perform operations.
• involves decisions about the organization of
• focuses on the physical implementation of the
hardware components, such as the instruction set architecture design.
architecture, data path design, and control unit
design.
• primary concern is optimizing performance to • Primary concern is the interconnection of different
ensure efficient execution of instructions. units.
• Deals with high-level design issues. • Handles low-level design issues.
• When designing a computer, architecture is fixed • organization explains how it accomplishes those
before organization tasks.
• architecture describes what the computer does • Organization changes with changing technology
• May span many years and encompass a number of
different computer models.
Processor Does:
• Fetch Instruction: from memory
• Interpret Instruction
• Fetch Data: From memory or I/O
• Process Data
• Write Data
• Processor needs some internal memory to-
• Store some data temporarily
• Location of the last instruction
• Instructions and data
• Instruction i.e. currently being executed
Internal Structure of CPU

Along with the Data

and control bus one
more bus i.e. Internal
Processor Bus

This internal bus

is needed to
transfer data
between the ALU
and the registers.

ALU operates only

on the data stored in
Internal processor
memory
Register Organization
• computer system employs a memory hierarchy
• higher levels of the hierarchy, memory is faster, smaller, and more
expensive
• Within the processor, there is a set of registers that function as a level
of memory above main memory and cache memory.
• Two types of registers.
• User-Visible registers
• Control and status register.
• User-Visible registers:
• Always referenced using the machine language.
User- Visible registers:
1. General Purpose registers:
• Variety functionalities given by programmer
• Can contain any of the operand
• Can contain any opcode
• Can be used for addressing functions i.e.register,indirect,displacement

2. Data Register
• Used only to hold the data
• Can not be used in calculation of operand address

3. Address registers
• Segment Pointers: Points to base address of the segment
• Index Registers :index address
• Stack Pointer
User-register variables continued..
• 4. Conditional Codes: CC
• Partially visible to the user

• Referred as flag

• Bits set by the processor hardware to indicate the result of operation.

• Different flags: zero, overflow, carry, positive, negative

• CC’s information is collected in one register

• Control register has a part of CC’s

Control and Status Registers
• Control the operation of the processor
• Not visible to the user
• Four registers are essential to instruction execution:
• Program counter (PC):
• Contains the address of an instruction to be fetched
• Instruction register(IR):
• Contains the instruction most recently fetched
• Memory address register (MAR):
• Contains the address of a location in memory
• Memory buffer register (MBR):
• Contains a word of data to be written to memory or the word most recently
read
Status Register
• PSW: Program Status Word
• Contains status information
• Contains conditional codes and additional status information
• Sign: Contains the sign bit of the result of the last arithmetic operation.
• Zero: Set when the result is 0.
• Carry: Set if an operation resulted in a carry (addition) into or borrow
(subtraction) out of a high-order bit.
• Equal: Set if a logical compare result is equality.
• Overflow: Used to indicate arithmetic overflow.
Interrupt Enable/Disable: Used to enable or disable interrupts.
 Register Organization Comparison
MC68000 8086

32-bit registers Every register is special

eight data registers(D0-D7) Four 16 bit data registers

with 16 bit address
Nine address registers (A0- Four 16 bit pointer and
A7(twice)) index registers
Allows 8,16,32 bit Four 16 bit segment
operations registers
32 bit address register Instruction pointer

2 SPs one for OS and one 1 bit control and status

for user (A7) one at a time flag
32 bit PC and 16 bit Status Segment register carries
register base address of segment
 Instruction Cycle
• The processing required for a single instruction is called an instruction cycle
• Instruction Processing consists of two parts-
• Instruction Fetch
• Instruction Execute

• Instruction Fetch:
• Fetches instruction from memory
• PC co-ordinates fetching of Instructions
• IR holds the instruction being executed
• 1st at 300 and then at 301,302,303,304
Instruction Execution
• Fetched instruction is stored in IR

• Processor interprets the instruction and performs the required action

• Processor-memory: Data transferred from processor to memory or from

memory to processor.

• Processor-I/O: Data transferred to or from a peripheral device by

transferring between the processor and an I/O module.

• Data processing: The processor may perform some arithmetic or logic

operation on data.

• Control: An instruction may specify that the sequence of execution be

altered.
 Instruction Cycle State Diagram

• Some null
states.
• Some states
visited more
than once
Different states in Instruction cycle
• Instruction Address Calculation(iac):
• Determine address of the next instruction to be executed
• If instruction of 16 bits and memory organization of 16 bits then add 1 to
previous address.
• If memory is organized as 8 bits, then add 2 to the previous address

• Instruction fetch (if):

• Read instruction from its memory location into the processor

• Instruction Operation Decoding (iod):

• Instruction analysis
• Types of operands to use
• Type of operation to be performed.
States in Instruction Cycle
• Operand Address Calculation(oac):
• If the operation involves reference to an operand in memory
• Determines the address of the operand

• Operand fetch (of): Fetch the operand from memory or read it in from
I/O.

• Data operation (do): Perform the operation indicated in the

instruction.

• Operand store (os): Write the result into memory or out to I/O.
Instruction Cycle with Interrupts
Machine Instructions
• The operation of a processor –determined by the instruction it
executes
• Instruction Set: Collection of different instructions processor can
handle
• Instruction Format:
• Each instruction must contain the information required by the processor for
execution
• Elements of Machine Instruction:
• Operation Code(opcode):
• specifies the operation to be performed
• Binary code representing the operation of instruction is an opcode
• e.g. ADD,I/O
Elements of Machine Instruction
• Source operands:
• Operation may involve one or more source operands
• Operands are input to the operation

• Result operand reference:

• Operation produces result
• May be a memory location to store the result

• Source and result operand may be at

• Main or virtual memory
• Processor register
• Immediate: contains the instruction itself
• Memory mapped I/O

• Next Instruction Reference:

• Tells the processor where to fetch the next instruction
• Address of the next instruction may be a real or a virtual address
Instruction Format
• Represented by sequence of bits
• Difficult to deal with binary representations of machine instructions
• Common practise to use symbolic representation
• Opcodes represented by abbreviations called mneumonics.

• ADD→ Add
• SUB→ Subtract
• MUL→ Multiply
• DIV→ Divide
• LOAD→Load data from memory
• STORE→Store data to memory
Instruction format
• Operands are also represented Symbolically
• A simple program would
• accept this symbolic input
• convert opcodes and operand references to binary form
• construct binary machine instructions.
• Today most programs use high-level language
• ADD R,Y
However, symbolic machine language remains a useful tool for describing
machine instructions.
Instruction Types Memory
Address
Data

• Consider high-level language instruction 513 X

• X=X+Y 514 Y

• How might this be accomplished with machine

instructions?
• assume a simple set of machine instructions, this operation could be
accomplished with three instructions
• Load a register with the contents of memory location 513.
• Add the contents of memory location 514 to the register
• Store the contents of the register in memory location 513.
• Single high-level language instruction requires three machine instructions
• High-level language-expresses operations in a concise algebraic form,
using variables

• A machine-level language expresses the operations in a very basic

form, involving the movement of data to or from registers.

• High-level language → machine language

• So, sufficient machine instructions should be there to express any

high-level instruction
Instruction Types
• Data Processing: Arithmetic and Logical

• Data Storage: data transfer from register to memory or vice-versa

• Data movement: I/O data transfer

• Control: Test and Branch Instructions

• Test instructions test the value of a data word or the status of a

computation
• Branch to move control of the program:e.g.JUMP ADDR, CALL ADDR
 Control Unit Design
• Set of control signals are instruction dependent.
• Such intelligence → either stored or built inside the control unit
• Control unit→ supplies set of control signals required for the current
opcode

CPU Status Flags

Zero Carry
……………….

Current opcode
Control unit … Control
… Signals
Addressing mode

CLOCK
 Control Unit Design
• Machine Language Instructions------------------>Set
Control unit
of Control Signals.

• Two ways to design a control unit:

1. Hardwired
• The digital circuits generate the control signals
• Conventional design technique

2. Microprogrammed
• Control signals are stored as bit patterns in a ROM, inside the control unit
• Modern design technique
 Micro-programmed Control Unit
Hardwired Control Unit

Microcode stored in memory

Implementation Fixed set of logic gates and circuits

More flexible, easier to modify

Flexibility Less flexible, difficult to modify

Supports complex instruction sets

Instruction Set Supports limited instruction sets

Complex design, more difficult to

Complexity of Design Simple design, easy to implement implement

Slower operation due to microcode

Speed Fast operation decoding

Easier to debug and test

Debugging and Testing Difficult to debug and test

Larger size, higher cost

Size and Cost Smaller size, lower cost
Hardwired Control Unit
• Consists of a collection of combinational circuits to generate various
Opcode
control signals

Decoder

....... Decoded Instructions

ADD SUB
T1
T2 Each instruction can
T3 be partitioned into set of
T4 Combinational . microoperations
Timing
Clock T5 Digital .
Circuits
T6 circuits .
T7 .
T8 Each microoperation
needs a proper control
signal
Timing
Pulses Control Signals
 ADD SUB HALT

T1
Each dot represents a
T2 circuit that generates one
or more control signals
T3
Timing
Signals
T4

T5

T6

Instructions
A hardwired control unit
• uses a fixed set of logic gates and circuits to execute instructions.
• The control signals for each instruction are hardwired into the
control unit,
• The control unit has a dedicated circuit for each possible
instruction
• The control hardware can be viewed as a
• state machine that changes from one state to another in every clock cycle,
• depends on the contents of the instruction register, the condition codes,
and the external inputs.
• The sequence of the operation carried out by this machine is
determined by the wiring of the logic elements
 The step Decoder
provides separate
signal line for each
Step, or time slot in
Control sequence.

The instruction Decoder

consists of a separate
signal line for each
instruction.
 Microprogrammed Control Unit
• control unit that uses a microcode to execute instructions
• The microcode is a set of instructions that can be modified or updated
• Each line describes a set of micro-operations occurring at one time and is
known as a microinstruction.
• Sequence of microinstructions in microprogram/firmware
• The control signals for each instruction are generated by a
microprogram that is stored in memory.
• microprogram is midway between hardware and software. It is easier to design
in firmware than hardware
• The micro-programmed control unit is slower in speed because of the
time it takes to fetch microinstructions from the control memory.
How Microprogrammed Control Unit is designed?
• construct a control word in which each bit represents one control line

• Each micro-operation would be represented by a different pattern of 1s

and 0s in the control word

• The sequence of micro-operations is not fixed

• Control words are stored in memory with each word having a unique
address.

• There is an address field at the end of each control word.

• The address field gives the address of the next control word to be executed
if a certain condition is True.
Horizontal Microinstruction
• One bit for the internal processor control line
• One bit for the system bus control line
• Condition field indicates when branching should be initiated
• Address: address of next control word
• To execute this microinstruction:
• turn on all the control lines indicated by a 1-bit
• turn off all the control lines indicated by a 0-bit
• If the condition field indicates a false condition, execute the next
microinstruction in the sequence
• If the condition indicated by the condition bits is true, the next
microinstruction to be executed is indicated in the address field
Microinstructions arranged in control memory
• Concise representation
• Each microinstruction executed
sequentially
• Each routine ends with a jump or
branch
• Execute cycle→indicates ADD,AND will
be executed next
• Fetch, indirect, execute,Interrupt
Microprogrammed Control Unit
• Microinstructions→ Control Memory
• Control address register→ Address of next
instruction to be read
• Control Buffer register → Read Instruction
• Sequencing Logic→ Loads the control address
register and issues read command
• Lower decoder → only in vertical
microinstructions
• In horizontal: each bit indicates one control sig
• In vertical: a code is used for each
microinstruction
• This lower decoder translates this code into
individual control signals
RISC and CISC Architecture
RISC CISC
• Reduced Instruction Set • Complex Instruction Set
computer computer
• It uses only hardwired control • It uses both hardwired and
unit/ microprogrammed control unit
• An instruction is executed in a • Instruction may take more than
single clock cycle. one clock cycle
• An instruction can fit in one • Instructions are larger than the
word. size of one word
• Code size is large. • Code size is small
• The program written for the • The program written for the CISC
RISC requires more space in requires less space in memory
memory.
 RISC CISC
• The execution time for RISC is • The execution time for CISC is
very short longer
• RISC requires more RAM as • CISC requires a minimum
compared to CISC amount of RAM
• Software Centric design • Hardware-centric design
• Complexity lies in the compiler • Complexity lies in the processor
• Few addressing modes • 8-10 different addressing modes
• Few instructions(30-40) • 100-300 instructions
• Instructions are executed in • Instructions are executed
parallel (pipeline) sequentially
• Ex. ARM processors • Ex. AMD processors
mPM: Microprogra
memory
mPC: Micrprogramm
Control Unit
CPU Architectures
CPU Architectures
• Von Neumann • Harvard
• It is a theoretical design based on • It is based on modern computer
a stored program concept architecture.
• It uses the same physical memory • It uses separate memory
address for both instructions and addresses for instructions and data
data • Processor needs one clock cycle to
• A processor needs two clock cycles execute an instruction
to execute an instruction • Complex control unit design due to
• Simple control unit design separate buses

• Cheaper and Fast • Costly

• Data transfers and instruction • Data transfers and instruction
fetches can not be performed fetches can be performed
simultaneously simultaneously