LITERATURE SURVEY

1. Design and Implementation of 32-Bit Adders Using Various Full Adders

This paper explores key concepts and related works in the field of adder design and optimization. It
starts by introducing the conventional full adder (FA), a fundamental building block for adders, and
describes its basic structure and Boolean expressions. The survey then delves into three variations of
modified full adders: FA1, FA2, and FA3, referencing the work of different researchers. FA1 is noted
for its area efficiency in multiplier circuits, FA2 for its advantages in both area and power efficiency,
and FA3 for its superior performance in terms of delay and area reduction. This comprehensive
survey sets the stage for the paper's focus, which is the design and comparative analysis of 32-bit
adders using these full adder cells.

Authors: K. Anirudh Kumar Maurya, K.Bala Sindhuri, Y.Rama Lakshmanna, N.Udaya Kumar

DOI: https://doi.org/10.1109/IPACT.2017.8245176

2. Low Power High-Speed 1-bit Full Adder Circuit Design at 45nm CMOS Technology

The paper "Low Power High-Speed 1-bit Full Adder Circuit Design at 45nm CMOS Technology" by
Ashish Kumar Yadav, Bhavana P. Shrivatava, and Ajay Kumar Dadoriya delves into the design and
assessment of 1-bit full adder circuits, essential components in digital systems. In the literature
survey, it aligns with previous research, emphasizing the importance of low-power and high-speed
full adders. It acknowledges the extensive exploration of various CMOS-based full adder designs,
including pass-transistor logic and conventional CMOS topologies, to optimize power consumption,
speed, and area. Researchers have also focused on reducing power dissipation through designs with
reduced transistor counts, such as 14T and 10T full adders. Furthermore, the survey discusses
advanced technologies like 45nm CMOS implementation and highlights performance metrics such as
power delay product (PDP) for comprehensive evaluation. It also touches on alternative full adder
architectures like SERF and GDI full adders, addressing factors like power consumption, delay, and
output voltage swing. Finally, it underscores the importance of transient analysis in assessing full
adder behavior over time, including aspects like voltage swing.

DOI: https://doi.org/10.1109/RISE.2017.8378203

3. Two New Energy-Efficient Full Adder designs

The paper titled "Two New Energy-Efficient Full Adder designs" by Majid Amini Valashani and Sattar
Mirzakuchaki presents two novel full adder designs aimed at optimizing energy efficiency while
maintaining high-speed operation, addressing crucial concerns in VLSI systems. The authors provide
an extensive review of existing full adder designs, categorizing and evaluating them based on their
characteristics. They specifically focus on XOR-XNOR and multiplexer modules within these designs,
emphasizing the importance of achieving full-swing outputs. The proposed full adders, based on a
hybrid topology, are introduced, and their structures are discussed. Through comprehensive
simulations, the authors compare the performance of their designs with various existing alternatives,
highlighting reduced delay, lower power consumption, and improved power-delay product. The
paper concludes by emphasizing the significance of energy-efficient full adders in modern VLSI
systems and the contributions of their proposed designs to address this need, making it a valuable
addition to the field of VLSI circuit design. Future work may involve further optimization and
application-specific investigations.

DOI: https://doi.org/10.1109/IranianCEE.2016.7585603
 ABSTRACT

1. Design and Implementation of 32-Bit Adders Using Various Full Adders

Adders play a vital role in the digital signal processing systems. The design of 32-bit adders is of high
importance because 32-bit architecture is common and widely used in many digital systems and
processors. In this paper, the design and the implementation of various 32-bit adders like Ripple
Carry Adder (RCA), Carry Increment adder (CINA) and Carry bypass adder (CBYA) for different full
adder cells is done using the Verilog HDL. The results are obtained by executing Verilog code in Xilinx
14.5 ISE for the Spartan 3E family device with speed grade -5.

2. Low Power High-Speed 1-bit Full Adder Circuit Design at 45nm CMOS Technology

One-bit full adder cell is one of the most frequently used digital circuit component in arithmetic logic
unit (ALU) and it is the essential functional unit of all computational circuit. Till now lots of
improvement has been done in this area to refine the architecture and performance of full adder
circuit design. In this paper two designs of novel 1-bit full adder cell at 45nm CMOS technology is
implemented by using ten transistors (10-T) along with the three existing 1-bit full adder cell. Later
the complete comparison and verification is performed with the different existing and proposed
adder cells on different supply voltages at 100MHz operating frequency. From the simulation results
by performing the comparison among proposed adder cells and existing adder cells it is found that
the proposed adder cells are better than the existing adder cells in terms of power consumption,
delay and power delay product (PDP). From the simulation result it is observed that the first
proposed adder circuit using XOR module has achieved maximum saving of power 91.65%, saving of
delay 59.37% and saving of overall PDP of 91.64% when compared to existing Static Energy Recovery
Full (SERF) full adder and Gate Diffusion Input (GDI) full adder circuit respectively. When second
proposed adder circuit using XOR module is compared with existing SERF and GDI adder circuit
maximum saving of power 93.04%, saving of delay 76.76% and saving of overall PDP of 96.01% is
achieved. All above statistical analysis is given by performing the comparison between existing and
proposed adder circuits which have same number of transistors count (10-T) in designing at supply
voltage 1 volt.

3. Two New Energy-Efficient Full Adder designs

Full adder cells play a vital role in numerous VLSI circuits. Therefore, design of an energy-efficient full
adder which operates reliably in submicron technologies has become a great concern in recent years.
Some previously designed cells suffer from non-full swing outputs, high-power consumption and
low-speed issues. In this paper, two high-speed, low-power and full-swing full adder circuits are
designed in 90-nm CMOS technology. According to simulation results, the proposed circuits have rail
to rail output signals. Also, an improvement of 12%-52%, 7%-48% and 28%-68% has been achieved in
delay, power consumption and power-delay product (PDP), respectively.

References:

[1] K. A. K. Maurya, Y. R. Lakshmanna, K. B. Sindhuri and N. U. Kumar, "Design and implementation of

32-bit adders using various full adders," 2017 Innovations in Power and Advanced Computing
Technologies (i-PACT), Vellore, India, 2017, pp. 1-6, doi: 10.1109/IPACT.2017.8245176.

[2] A. K. Yadav, B. P. Shrivatava and A. K. Dadoriya, "Low power high speed 1-bit full adder circuit
design at 45nm CMOS technology," 2017 International Conference on Recent Innovations in Signal
processing and Embedded Systems (RISE), Bhopal, India, 2017, pp. 427-432, doi:
10.1109/RISE.2017.8378203
[3] M. A. Valashani and S. Mirzakuchaki, "Two new energy-efficient full adder designs," 2016 24th
Iranian Conference on Electrical Engineering (ICEE), Shiraz, Iran, 2016, pp. 655-660, doi:
10.1109/IranianCEE.2016.7585603.