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4931_Grace College of Engineering, Thoothukudi

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

B.E. Electronics and Communication Engineering

Anna University Regulation: 2021

EC3462 – Linear Integrated Circuits Laboratory

II Year / IV Semester

Lab Manual

Prepared by,
Mrs. S. Pricilla Mary, AP/ECE

EC3462_LIC_LAB_R2021

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4931_Grace College of Engineering, Thoothukudi

GRACE COLLEGE OF ENGINEERING

MULLAKADU, THOOTHUKUDI

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

LABORATORY MANUAL

FACULTY NAME : S. PRICILLA MARY

SUB CODE : EC3462
SUBJECT TITLE : LINEAR INTEGRATED CIRCUITS
LABORATORY
SEMESTER : IV
YEAR : II
DEPARTMENT : ELECTRONICS AND COMMUNICATION
ENGINEERING

EC3462_LIC_LAB_R2021

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EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

EC3462 – Linear Integrated Circuits Laboratory L P T C 0 0 3 1.5

LIST OF EXPERIMENTS

DESIGN AND ANALYSIS OF THE FOLLOWING CIRCUITS

1. Series and Shunt feedback amplifiers-Frequency response, Input and output
impedance calculation
2. RC Phase shift oscillator and Wien Bridge Oscillator
3. Hartley Oscillator and Colpitts Oscillator
4. RC Integrator and Differentiator circuits using Op-Amp
5. Clippers and Clampers
6. Instrumentation Amplifier
7. Active low-pass, High pass & Band pass filters
8. PLL Characteristics and its use as frequency multiplier, clock synchronization
9. R-2R ladder type D-A Converter using Op-Amp

SIMULATION USING SPICE (Using Transistor):

1. Tuned Collector Oscillator
2. Twin -T Oscillator / Wein Bridge Oscillator
3. Double and Stagger tuned Amplifiers
4. Bistable Multi-vibrator
5. Schmitt Trigger circuit with Predictable hysteresis
6. Analysis of power Amplifier.

TOTAL : 45 PERIODS

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EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

CONTENTS

Page
Sl. No. Name of the Experiment
No.
DESIGN EXPERIMENTS
1.a Current series feedback amplifier 4
1.b Voltage shunt feedback amplifier 9
2.a RC phase shift oscillator 14
2.b Wein-Bridge oscillator 17
3.a Hartley’s oscillator 20
3.b Colpitt’s oscillator 23
4 RC Integrator and Differentiator circuits using Op-Amp 26
5 Clippers and Clampers 30
6 Instrumentation Amplifier 35
7 Active low-pass, High pass & Band pass filters 38
8 PLL Characteristics and its use as frequency multiplier, clock 44
synchronization
9 R-2R ladder type D-A Converter using Op-Amp 48
SIMULATION USING SPICE EXPERIMENTS
9 Tuned Collector oscillator 52
10 Twin T Oscillator 55
11 Double and Stagger tuned Amplifier 57
12 Bistable Multivibrator 60
13 Schmitt Trigger circuit with Predictable hysteresis 62
14 Analysis of power amplifier 64
CONTENT BEYOND THE SYLLABUS
15 Voltage and Current Time base circuits 67

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EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

Ex. No.: 1.a

CURRENT SERIES FEEDBACK AMPLIFER
Date:

AIM:
To design a negative feedback amplifier and to draw its frequency response.

REQUIREMENTS:

S.No EQUIPMENTS RANGE QUANTIT Y

1 AFO (0-1) MHz 1
2 CRO (0-20) MHz 1
3 Resistors 1.5 K, 6KΏ, 2K, 14k, 2.3K, 10K Each one
4 Power supply (0-30V) 1
5 Transistors BC 107 1
6 Capacitors 28F, 10F, 720F 1

Design examples:
VCC= 15V, IC=1mA, AV= 30, fL= 50Hz, S=3, hFE= 100, hie= 1.1KΩ
Gain formula is,
AV= - hFE RLeff / hie
Assume, VCE = VCC / 2 (transistor in active region) VCE = 15/2=7.5V
VE = VCC / 10= 15/10=1.5V
Emitter resistance is given by, re =26mV/ IE Therefore re =26 Ω
hie= hfe re
hie =2.6KΩ
(i) To calculate RC:
Applying KVL to output loop,
VCC= IC RC + VCE+ IE RE (1)
Where RE = VE / IE (IC= IE)
RE = 1.5 / 1x10-3= 1.5KΩ
From equation (1), RC= 6KΩ
(ii) To calculate RB1&RB2:
Since IB is small when compared with IC,
IC ~ IE
VB= VBE + VE= 0.7 + 1.5=2.2V
VB= VCC (RB2 / RB1+ RB2) (2)
S=1+ (RB / RE)
RB= 2KΩ
We know that RB= RB1|| RB2
RB= R B1RB2/ RB1+RB2 (3)
Solving equation (2) & (3), Therefore,
RB1 = 14KΩ
From equation (3), RB2= 2.3KΩ
(iii) To find input coupling capacitor (Ci):
XCi = (hie|| RB) / 10 XCi = 113
XCi= 1/ 2пf Ci
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Ci = 1 / 2пf XCi
Ci = 1/ 2X3.14X 50 X 113=28µf
(iv) To find output coupling capacitor (CO):
XCO= (RC || RL) / 10, (Assume RL= 10KΩ)
XCO= 375
XCO= 1/ 2пf CO
CO = 1/ 2x 3.14x 50 x 375=8µf =10 µf
(v) To find Bypass capacitor (CE):
(Without feedback)
XCE = {(RB+hie / 1+ hfe) || RE}/ 10 XCE = 4.416
CE= 1 / 2пf XCE
CE = 720 µf
Design with feedback:
To design with feedback remove the bypass capacitor (CE).
Assume RE = 10KΩ

CIRCUIT DIAGRAM:

WITHOUT FEED BACK:

WITH FEEDBACK:

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EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

MODEL TABULATION:

Without feedback:
Vi=
Frequency Output Voltage Gain = 20log(V0/Vi)
Sl. No Gain = V0/Vi
(Hz) (V0) (volts) (dB)

With feedback:
Vi=
Frequency Output Voltage Gain = 20log(V0/Vi)
Sl. No Gain = V0/Vi
(Hz) (V0) (volts) (dB)

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EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

MODEL GRAPH:

THEORY

Negative feedback in general increases the bandwidth of the transfer function stabilized by
the specific type of feedback used in a circuit. In Voltage series feedback amplifier, consider a
common emitter stage with a resistance R’ connected from emitter to ground. This is a case of voltage
series feedback and we expect the bandwidth of the trans resistance to be improved due to the
feedback through R’. The voltage source is represented by its Norton’s equivalent current source
Is=Vs/Rs.

PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Set VCC = 10V; set input voltage using audio frequencyoscillator.
3. By varying audio frequency oscillator take down output frequency oscillator voltage for
difference in frequency.

4. Calculate the gain in dB

5. Plot gain Vs frequency curve in semi-log sheet.
6. Repeat the steps 1 to 6 with feedback
7. Compare this response with respect to the amplifier without feedback.

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EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

INFERENCE:
Thus current series feedback amplifier is designed and studied its
performance.

Parameters Theoretical Practical

With Feed Without Feed With Feed Without Feed
Back Back Back Back
Input Impedance
Output Impedance
Gain(midband)
Bandwidth

VIVA QUESTIONS:
1. What is feedback?
2. What are the parameters used to design the amplifier.
3. Compare the input impedance for with and without feedback?
4. Compare the theoretical and practical bandwidth for with feedback.
5. Calculate the value of output impedance with and without feedback.

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EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

Ex. No.: 1.b

VOLTAGE SHUNT FEEDBACK AMPLIFIER
Date:

AIM:
To design and study frequency response of voltage shunt feedback amplifier.

REQUIREMENTS:
S. Equipment
Name Range Quantity
No List
Signal generator (0-30) MHz 1
CRO (0-20) V 1
1 Equipment’s
Regulated Power Supply (0-30) V 1
2 Components Resistor 3kΩ, 1.1kΩ,5kΩ, 2.5kΩ,1kΩ 1
Capacitor 66F,30F,58 µf 1
Transistors BC 107 1
Bread board - 1
Other
3 Connecting Wires As
accessories Single strand required

DESIGN PROCEDURE:
Given specifications:
VCC= 10V, IC=1.2mA, AV= 30, fI = 1 kHz, S=2, hFE= 150, β=0.4
The feedback factor, β= - 1/RF= +1/0.4=2.5KΩ
(i) To calculate RC:
The voltage gain is given by, AV= -hfe (RC|| RF) / hie h ie = β re
re = 26mV / IE = 26mV / 1.2mA = 21.6 hie = 150 x 21.6 =3.2KΩ
Apply KVL to output loop,
VCC= IC RC + VCE+ IE RE (1)
Where VE = IE RE (IC= IE)
VE= VCC / 10= 1V
Therefore RE= 1/1.2x10-3=0.8K= 1KΩ
VCE= VCC/2= 5V
From equation (1), RC= 3 KΩ
(ii) To calculate R1&R2:
S=1+ (RB/RE)
RB= (S-1) RE= R1 || R2 =1KΩ
RB= R 1R2 / R1+ R2 (2)
VB= VBE + VE = 0.7+ 1= 1.7V VB= VCC R2 / R1+ R2 (3)
Solving equation (2) & (3),
R1= 5 KΏ & R2= 1.1KΩ
(iii) To calculate Resistance:
Output resistance is given by, RO= RC || RF
RO= 1.3KΩ
input impedance is given by,
Ri = (RB|| RF) || hie = 0.6KΩ

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EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

Trans-resistance is given by,

Rm= -hfe (RB|| RF)( RC || RF) / (RB|| RF)+ hie Rm= 0.06KΩ
AC parameter with feedback network:
(i) Input Impedance:
Rif = Ri /D (where D= 1+β Rm)
Therefore D = 25 Rif= 24
Input coupling capacitor is given by, Xci= Rif / 10= 2.4 (since XCi << Rif)
Ci = 1/ 2пfXCi =66µf
(ii) Output impedance:
ROf= RO/ D = 52
Output coupling capacitor: XCO= Rof /10= 5.2
CO = 1/ 2пfXCO= 30µf
(iii) Emitter capacitor:
XCE << R’E = R’/10
R’E= RE|| {(hie +RB) / (1+hfe)} XCE= 2.7
Therefore CE= 58µf
WITHOUT FEED BACK

CIRCUIT DIAGRAM:

WITH FEED BACK:

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EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

MODEL TABULATION:

Without feedback:
Vi=
Frequency Output Voltage Gain = 20log(V0/Vi)
Sl. No Gain = V0/Vi
(Hz) (V0) (volts) (dB)

With feedback:
Vi=
Frequency Output Voltage Gain = 20log(V0/Vi)
Sl. No Gain = V0/Vi
(Hz) (V0) (volts) (dB)

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MODEL GRAPH:

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EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

THEORY:
Negative feedback in general increases the bandwidth of the transfer function stabilized by
the specific type of feedback used in a circuit. In Voltage shunt feedback amplifier, consider a
common emitter stage with a resistance R’ connected from collector to base. This is a case of voltage
shunt feedback and we expect the bandwidth of the Trans resistance to be improved due to the
feedback through R’. The voltage source is represented by its Norton’s equivalent current source
Is=Vs/Rs.

PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Set VCC = 10V; set input voltage using audio frequency oscillator.
3. By varying audio frequency oscillator take down output frequency oscillator voltage for
difference in frequency.
4. Calculate the gain in dB
5. Plot gain Vs frequency curve in semi-log sheet.
6. Repeat the steps 1 to 6 with feedback
7. Compare this response with respect to the amplifier without feedback.

INFERENCE:

Thus voltage shunt feedback amplifier is designed and studied its performance.

Parameters Theoretical Practical

With Feed Without Feed With Feed Without Feed
Back Back Back Back
Input Impedance
Output Impedance
Gain(midband)
Bandwidth

VIVA QUESTIONS:
1. Compare the bandwidth of feedback amplifier.
2. Give the stability of gain with feedback.
3. Which sampling and mixing network is used in Voltage shunt feed back
amplifier,
4. Calculate the input impedance for with feed back.
5. What type of feedback is used in amplifier?

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EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

Ex.No.:2.a
RC PHASE SHIFT OSCILLATOR
Date:
AIM:
To design a RC phase shift oscillator and to find the frequency of oscillation

REQUIREMENTS:

S.
REQUIREMENTS RANGE QUANT ITY
No
1 Resistors 7.5k,1.4 k 4.8K,1.2K, 19K, .5K 1each, 3
2 Power supply (0-30)V 1
3 Transistor BC107 1
4 Capacitors 1.3f , 2.1f, 1.3f, 0.01F 1,1,3
5 CRO (0-30)MHz 1
6 Bread board - 1

Design Example:
Specifications:
VCC = 12V, ICq =1mA, =100, Vceq = 5V, f=1 KHz, S=10, C=0.01 µf, hfe= 330, AV= 29
Design:
(i) To find R:
Assume f=1 KHz, C=0.01µf
f=1/2πRC
R=1/2x3.14 6 x 1x103x 0.01x10-6=6.5KΩ
Therefore R=6.5KΩ
(ii) To find RE & RC:
VCE = VCC /2 = 6V
re= 26mV / IE= 26
hie = hfe re= 330 x 26= 8580
On applying KVL to output loop,
VCC=ICRC + VCE + IERE (1)
VE = IE RE
RE = VE / IE =1.2/ 10-3 =1.2K

From equation (1), 12= 10-3(RC+ 1200) +6

RC=4800=4.8K
(iii) To calculate R1 & R2:
VBB= VCC R2 / R1+ R2 (2)
VB= VBE +VE = 0.7+12 =1.9V
From equation (2), 1.9= 12 R2 / R1+ R2 R2 / R1+ R2= 0.158 (3)
S = 1+ RB / RE= RB = 1.2K RB =R1 || R2
0.15R = 1.2x10-3=7.5K
1

R2 =0.158 R1 + 0.158 R2, R2= 1.425K

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EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

(iv) To calculate Coupling capacitors:

(i) XCi= {[hie + (1+hfe) RE] || RB }/ 10 = 0.12K
XCi= 1 / 2πf Ci = 1.3f
(ii) XCO= RLeff / 10 [ AV = - hfe RLeff /hie] RLeff = 0.74K,
XCO=0.075 K
XCO= 1 / 2𝜋 f CO , CO= 2.1f
(iii) XCE= RE / 10 = 1.326 f XCE = 1 / 2∏ f CE=49.27f
(iv) Feed back capacitor, XCF = Rf / 10 Cf = 0.636f = 0.01f

CIRCUIT DIAGRAM:

MODEL GRAPH:

TABULATION:

Time Period Frequency(Hz)

(ms)
Amplitude

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EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

THEORY:
The low frequencies RC oscillators are more suitable. Tuned circuit is not an essential

requirement for oscillation. The essential requirement is that there must be a 180o phase shift around

the feedback network and loop gain should be greater than unity. The 180 o phase shift in feedback
signal can be achieved by suitable RC network.

PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Set VCC = 15V.
3. For the given supply the amplitude and time period is measured from CRO.
4. Frequency of oscillation is calculated by the formula f=1/T
5. Amplitude Vs time graph is drawn.
INFERENCE:

Thus the RC-phase shift oscillator is designed and constructed for the given
frequency.

Theoretical frequency :

Practical frequency :

VIVA QUESTIONS:

1. What is an oscillator?
2. What is barkhausen criterion for oscillation?
3. Which feedback is used in oscillators?
4. Give the frequency of oscillation for RC-phase shift oscillator?
5. Give the disadvantages of phase shift oscillator.

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EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

Ex. No.:2.b WEIN- BRIDGE OSCILLATOR

Date:

AIM:
To design a Wein-bridge oscillator using transistors and to find the frequency of oscillation.
EQUIREMENTS:

S.No REQUIREMENTS RANGE QUANTITY

1 Resistors 1KΩ,10KΩ, 3
2.2KΩ, 2
3KΩ,33KΩ,0.8KΩ 1
2 Power supply 5V 1
3 Transistor BC107 1
4 Capacitors 0.01µF,10µF 2
100µF 1
5 CRO - 1
6 Bread board - 1

DESIGN EXAMPLE:
Assume f=1 KHz, C=0.1µf
f = 1/ 2πRC; R= 1/2πfC
R =1/2x3.14x1x103x0.1x103 = 1.59KΩ
To calculate R1:
R1= 10R =10x1.5 =15.9KΩ
To calculate Rf (Feedback resistor): Rf = 2R1
Rf = 2(15.9x103) =31.8KΩ ≈ 33KΩ
CIRCUIT DIAGRAM

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EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

MODEL GRAPH:

MODEL TABULATION:

Amplitude (V) Time(μs) Frequency (Hz)

THEORY:
Generally, in an oscillator, amplifier stage introduces 180o phase shift and feedback network

introduces additional 180o phase shift, to obtain a phase shift of 360o around a loop. Thisis a
condition for any oscillator. But Wein bridge oscillator uses a non-inverting amplifier and hence

does not provide any phase shift during amplifier stage. As total phase shift requires is 0o or 2n
radians, in Wein bridge type no phase shift is necessary through feedback. Thus, the total phase shift

around a loop is 0o. The output of the amplifier is applied between the terminals 1 and 3, which are
the input to the feedback network. While the amplifier input is supplied from the diagonal terminals
2 and 4, which is the output from the feedback network. Thus, amplifier supplied its own output
through the Wein bridge as a feedback network.
The two arms of the bridge, namely R1, C1 in series and R2, C2 in parallel are called frequency
sensitive arms. This is because the components of these two arms decide the frequency of the
oscillator. Advantage of Wein bridge oscillator is that by varying the two-capacitor values
simultaneously, by mounting them on the common shaft, different frequency ranges can be provided.
PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Set VCC = 5V.
3. For the given supply the amplitude and time period is measured from CRO.
4. Frequency of oscillation is calculated by the formula f=1/T
5. Amplitude Vs time graph is drawn.

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INFERENCE:

Thus the Wein – bridge oscillator is designed for the given frequency of
oscillation.
Theoretical frequency :
Practical frequency :

VIVA QUESTIONS:

1. Give the condition for maximum oscillation.

2. What is the frequency of oscillation under balanced condition?
3. In which way high gain is obtained in wein bridge oscillator.
4. How to improve the amplitude stability of output waveform.

5. What is the frequency of oscillation?

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Ex. No.: 3.a

HARTLEY’S OSCILLATOR
Date:

AIM:
To design and construct a Hartley oscillator at the given operating frequency.

REQUIREMENTS:

S.No EQUIPMENTS RANGE QUANTITY

1 Resistors 1KΩ, 2KΩ, 22KΩ, 100KΩ 1

2 RPS (0-30)V 1
3 Transistor BC107 1
4 Capacitors 0.01µF, 2
0.1µF,3.2nF 1
5 Inductor 10mH 2
6 CRO 30MHz 1
7 Bread board - 1

Design Example:
Design of feed back Network:
Given L1= L2=10mH, f=20 KHz, VCC=12V, IC=3mA, S=12
f = 1/2π√(𝐿1 + 𝐿2)𝐶
C= 3.2nf
Amplifier design:
(i) Selection of RC:
Gain formula is, AV= - hfe RLeff / hie
Assume VCE=VCC/2 (Transistor active) VCE= 12/2= 6V
VE=IERE= VCC/10=1.2V; VCC=ICRC + VCE + IERE
RC= (VCC- VCE -IERE) / IC
Therefore RC = 1.6K=2 K

(ii) Selection of RE:

IC= IE=3mA RE= VE/IE
RE= 1.2 / 3x10-3=400 =1K

(iii) Selection of R1 & R2:

Stability factor S=12 S=1+ (RB/ RE) 12=1+ (RB/1x103) RB=11K
Using potential divider rule,
RB=R1R2 / R1+R2 & VB= (R2/ R1+R2) VCC RB /R1= R2/ R1+R2
Therefore RB/R1= VB/VCC
VB=VBE+ VE= 0.7+1.2=1.9V=2V R1= (VCC/ VB )RB
R1= (12/2)x 11x103=66K=100K VB/VCC
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=R2 / R1+R22/ 12=R2 / 100x103+R2 (100x103) +R2 =R2/0.16=19K

R2=19K=22 K
(iv) Output capacitance (CO):
XCO=RC/10=2x103/10=200 1/2πfCO=200
CO=1/2x3.14x20x103x200
CO=0.039=0.01µf
(v) Input capacitance (Ci):
XCin= RB/10=11x103/10=1.1x103
1/2πfCin=1.1x103 Cin=1/2x3.14x20x103x1.1x103 Cin= 0.007=0.01µf

(vi) By pass Capacitance (CE):

XCE=RE/10=1x103/10=100 1/2∏fCE=100

CE= 1/2x3.14x20x103x100 CE =0.079µf = 0.1µf

THEORY:
Hartley oscillator is very popular and is commonly used as local oscillator in radio
receivers. The collector voltage is applied to the collector through inductor L whose reactance is
high compared with X2 and may therefore be omitted from equivalent circuit, at zero frequency,
however capacitor Cb acts as an open circuit.

PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Set VCC = 12V.
3. For the given supply the amplitude and time period is measured from CRO.
4. Frequency of oscillation is calculated by the formula f=1/T

5. Verify it with theoretical frequency, f= 1/2π√(𝐿1 + 𝐿2)𝐶 Amplitude Vs time graph

is drawn.

CIRCUIT DIAGRAM:

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MODEL GRAPH:

MODEL TABULATION:

Amplitude (V) Time(μs) Frequency (Hz)

1.5 40 25

INFERENCE:

Thus the Hartley oscillator is designed and constructed for the given frequency.
Theoretical frequency:

Practical frequency :

VIVA QUESTIONS:

1. How does an oscillator differ from an amplifier?

2. What is the approximate value of hfe in a Hartley oscillator using BJT?
3. Mention the expression for frequency of oscillation?
4. Mention the reasons why LC oscillator is preferred over RC oscillator
at radio frequency?
5. How the Hartley oscillator satisfy the barkhausen criterion.

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Ex. No: 3.b

COLPITT’S OSCILLTOR
Date:
AIM:
To design and construct a Colpitt’s oscillator at the given operating frequency.
REQUIREMENTS:

S.No EQUIPMENTS RANGE QUANTITY

1 Resistors 100KΩ, 22KΩ, 2KΩ, 1KΩ 1
2 RPS (0-30)V 1
3 Transistor BC107 1
4 Capacitors 0.01µF, 3
0.1µF 1
5 Inductor 10mH 1
6 CRO 30MHz 1
7 Bread board - 1

Design of feedback Network:

Given C1= 0.1 F, L=10mH, f=20 KHz, VCC=12V, IC=3mA, S=12
𝐶1+𝐶2
f = 1/2π√ , C2= 0.01F
𝐿𝐶1𝐶2
Amplifier design:
(i) Selection of RC:

Gain formula is,

AV= - hfe RLeff / hie,
Assume VCE=VCC/2 (Transistor active) VCE= 12/2= 6V
VE=IERE= VCC/10=1.2V
VCC=ICRC + VCE + IERE RC= (VCC- VCE -IERE) / IC
Therefore RC= 1.6K=2 K
(ii) Selection of RE:
IC= IE=3mA
RE= VE/IE= 1K
(iii) Selection of R1 & R2:
Stability factor S=12 S=1+ (RB/ RE)
12=1+ (RB/1x103) =11k
Using potential divider rule,
RB=R1R2 / R1+R2 & VB= (R2/ R1+R2) VCC RB /R1= R2/ R1+R2
Therefore RB/R1= VB/VCC
VB=VBE+ VE= 0.7+1.2=1.9V=2V
R1= (VCC/ VB ) RB=66K=100K
VB/VCC =R2 / R1+R2
2/ 12=R2 / 100x103+R2 R2=19K=22 K
(iv) Output capacitance (CO):
XCO=RC/10=2x103/10=200 1/2πfCO=200

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CO=1/2x3.14x20x103x200=0.039=0.01µf
(v) Input capacitance (Ci):
XCin= RB/10=11x103/10=1.1x103
1/2πfCin=1.1x103
Cin=1/2x3.14x20x103x1.1x103=0.0101µf
(vi) By pass Capacitance (CE):
XCE=RE/10=1x103/10=100 1/2πfCE=100
CE= 1/2x3.14x20x103x100=0.079µf = 0.1µf
THEORY:
Colpitt’s oscillator is very popular and is commonly used as local oscillator in
radio receivers. The collector voltage is applied to the collector through inductor L whose reactance
is high compared with X2 and may therefore be omitted from equivalent circuit, at zero frequency;
The circuit operates as Class C. the tuned circuit determines basically the frequency of oscillation.

PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Set VCC = 12V.
3. For the given supply the amplitude and time period is measured from CRO.
4. Frequency of oscillation is calculated by the formula f=1/T 5 .
5. Amplitude Vs time graph is drawn

CIRCUIT DIAGRAM:

MODEL GRAPH:

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MODEL TABULATION:

Amplitude (V) Time(μs) Frequency (Hz)

INFERENCE:
Thus the Collipit’s oscillator is designed and constructed for the given
frequency.
Theoretical frequency :
Practical frequency :

VIVA QUESTIONS:

1. What is the approximate value of hfe in a colpitt’s oscillator using BJT

for sustained oscillation?

2. What is Tank circuit?

3. Mention the expression for frequency of oscillation?
4. What are the essential parts of an oscillator?
5. Name two high frequency oscillators?

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Ex. No.: 4
RC INTEGRATOR AND DIFFERENTIATOR USING OP-AMP
Date:
AIM:
To design and test the performance of integrator and differentiator circuits usingOp-amp.

REQUIREMENTS:

Equipment Quantity
S.No Name Range
List
Signal generator 1
1 CRO (0-30)MHz 1
Equipments
Dual power supply (0-30)V 1
Resistors 1 k k 1
2 Components Op-amp IC741 1
Capacitor 0.1 µF, 0.01 µF 1
Other Breadboard - 1
3 accessories Connecting wires Single strand As
required

THEORY:
Integrator:
In an integrator circuit, the output voltagE is integral of the input signal.The output voltage of an integrator
1 𝑡
is given by 𝑉𝑂 = − 𝑅 𝐶 ∫0 𝑉𝑖 𝑑𝑡. At low frequencies the gain becomes infinite, so the capacitor is fully
1 𝐹
charged and behaves like an open circuit. The gain of an integrator at low frequency can be limited by
connecting a resistor in shunt with capacitor.
One of the simplest of the operational amplifier that contains capacitor is differential amplifier.As the
sugg.ests, the circuit performs the mathematical operation of differentiation.the output is the derivative
of the given input signal voltage.The minus sign indicates a 1800 phase shift of the output waveform Vo
with respect to the input signal.
Differentiator:
In the differentiator circuit the output voltage is the differentiation of the input voltage.
𝑑𝑉
The output voltage of a differentiator is given by 𝑉0 = −𝑅𝑓 𝐶1 𝑖 .The input impedance of this circuit
𝑑𝑡
decreases with increase in frequency, thereby making the circuit sensitive to high frequency noise. At high
frequencies circuit may become unstable.
Op-amps allow us to make nearly perfect integrators such as the practical integrator the circuit
incorporates a large resistor in parallel with the feedback capacitor. This is necessary because real op-
amps have a small current flowing at their input terminals called the "bias current". This current is typically
a few nanoamps, and is neglected in many circuits where thecurrents of interest are in the microamp to
milliamp range. The feedback resistor gives a path for the bias current to flow. The effect of the resistor
on the response is negligible at all but thelowest frequencies.

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DESIGN:
INTEGRATOR:
Given :
R1= 10 KΩ ; f= 4 kHz
Cf = 1/ (2πRf)Rf
= 10 R
= 100 KΩ
Cf = 0.039 µF=0.01 µF
DIFFERENTIATOR:
Given:
C1 = 1 µf ; f1 = 150 kHzRf
= 1/ (2πC1f1)
= 1/ (2*3.14*1*10-6*150)Rf =
1.06 KΩ
Cf = R1C1/Rf
= 1.06*10-3*0.1*10-6

10.6 * 103
Cf = 0.01 µF
Rf = 100KΩ

Circuit Diagram:

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TABULATION:
Input Voltage(V) Output Voltage(V)
Circuit Time(s) Time(s)
Waveform waveform
Sine Cosine
Integrator
Square Triangle
Differentiator Sine Cosine

Square Spike
MODEL GRAPH:
DIFFERENTIATOR

DIFFERENIATOR:
PROCEDURE:
Integrator:
1. Connections are made as per the circuit diagram.
2. Apply the square or sine input signal at high frequency using AFO.
3. Note the corresponding output waveforms and plot the
graph.Differentiator:
1. Connections are made as per the circuit diagram.
2. Apply the square or sine input signal at low frequency using AFO.
3. Note the corresponding output waveforms and plot the graph.

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INTEGRATOR

Applications:
1.The DC voltage produced by the differentiator circuit could be used to drive a comparator which would
signalas alarm or active a control if the rate of change exceeded a pre-set level. 2.Waveform Generators
Viva questions and answers:
1. What are the limitations of the basic differentiator circuit:
At high frequency, a differentiator may become unstable and break into oscillations. The input
impedancedecreases with increase in frequency , thereby making the circuit sensitive to high
frequency noise.
2. Write down the condition for good differentiation :-
For good differentiation, the time period of the input signal must be
greater than or equal to Rf C1 ,T > R f C1 Where, Rf is the feedback resistance
3. What is an IC:
The term IC refers to complex Electronic circuits consisting of a large number of components on a
singlesubstrate.
4. What are the advantage of IC:
Cost reduction,Increased operating speed,Reduced power consumption and Improved functional
performance.
5. What are the different IC technologies:
Monolithic technology and Hybrid technology

INFERENCE:
Thus, the integrator and differentiator are constructed and output waveform observed and

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readings were tabulated.

Ex. No.: 5
CLIPPER AND CLAMPER CIRCUITS
Date:
AIM:
To construct and design the clipper and clamper circuits using diodes.

REQUIREMENTS:

S. Equipment
Name Range Quantity
No List
Function generator (0-30)MHz 1
1 Equipments CRO (0-20)V 1
Regulated Power Supply (0-30)V 1
Diode IN4007 1
2 Components Resistor 1k 1
Capacitor 1uf 2
Other Bread board - 1
3
accessories Connecting Wires Single strand As required

DESIGN PROCEDURE:
Given f=1 kHz, T=t=1/f=1x10-3 sec=RC Assume, C=1uF

Then, R=1KΩ

POSITIVE CLIPPER

CIRCUIT DIAGRAM:

MODEL TABULATION:

Positive Negative Time (ms)

Cycle (V) Cycle ( V)

Input
Output

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MODEL GRAPH:

NEGATIVE CLIPPER: CIRCUIT DIAGRAM:

MODEL TABULATION:

Positive Cycle (V) Negative Cycle( V) Time (ms)

Input
Output

MODEL GRAPH:

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CLAMPER CIRCUIT:

POSITIVE CLAMPER CIRCUIT DIAGRAM:

Vin=5V

MODEL TABULATION:

Positive Negative Time (ms)

Cycle (V) Cycle( V)
Input
Output

MODEL GRAPH:

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NEGATIVE CLAMPER CIRCUI DIAGRAM:

Vin=5V

MODEL TABULATION:

Positive Negative Time

Cycle Cycle( V) (ms)
(V)
Input
Output

MODEL GRAPH

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THEORY

CLIPPER:
A Clipper is a circuit that removes either the positive or negative part of a waveform. For a positive
clipper only the negative half cycle will appear as output.
CLAMPER:
A Clamper circuit is a circuit that adds a dc voltage to the signal. A positive clamper shifts the ac
reference level upto a dc level.
WORKING:
During the positive half cycle, the diode turns on and looks like a short circuit across the output
terminals. Ideally, the output voltage is zero. But practically, the diode voltage is 0.7 V while conducting.
On the negative half cycle, the diode is open and hence the negative half cycle appear across the
output.
APPLICATION:

• Used for wave shaping

• To protect sensitive circuits

PROCEDURE:
1. Connect as per the circuit diagram.
2. Set the signal voltage (say 5V, 1 KHz) using signal generator.
3. Observe the output waveform using CRO.
4. Sketch the output waveform.
INFERENCE:

Thus, the output waveform for Clipper and clamper was observed and its readings are tabulated.

VIVA QUESTIONS:

1. What are the other names of clipper circuits?

2. What is combinational clipper?
3. Why clippers are used in TV receivers.
4. Give one application of clamper.
5. What are biased clipper and clamper?

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Ex. No.: 6
INSTRUMENTATION AMPLIFIER
Date:
AIM:
To design and test the performance of instrumentation amplifier using Op-amp.

APPARATUS REQUIRED:

S.NO DESCRIPTION RANGE QUANTITY

1. Signal generator 1
2. CRO 1
3. Resistors 1K,50K,2K 1
Capacitor 0.1F
4. 1
Op-amp IC741
5. 1
Breadboard
6. Dual power supply 1
7. Connecting wires 1
8. AS REQURIED

THEORY:
An instrumentation amplifier is the intermediate stage of a instrumentation system. The signal source of the
instrumentation amplifier is the output of the transducer. Many transducersoutput do not have the ability or
sufficient strength to drive the next following stages.
Therefore, instrumentation amplifiers are used to amplify the low-level output signal of the transducer so
that it can drive the following stages such as indicator or displays. The major requirements of a
instrumentation amplifier are precise, low-level signal amplification where low-noise, low thermal and time
drifts, high input resistance & accurate closed-loop gain, lowpower consumption, high CMRR & high slew
rate for superior performance.

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Circuit Diagram:

TABULATION
Freque Differential mode Commonmode CMRR
ncy Vd= Vc=
(Hz) Vd Ad= Vd Ad= Vc Ac= Vc / Ac= Ad / Ac 20 log
/Vin 20 log Vd / Vin 20 log Vc / Ad /
Vin Vin Ac
(in dB) (in dB) (in dB)

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GRAPH

PROCEDURE:
1. Select the entire resistor with same value of resistance R. Let R be the gain varying resistorwith different
values of resistance for simplicity let R, be a constant value.
2. Connect the circuit as shown in the circuit diagram.
3. Give the input V1 & v2 to the non-inverting terminals of first & second op- amprespectively.
4. By varying the value of RG, measure the output voltage for common mode and differentialmode
operation. Since R is selected as constant value, provide different input value of V1 & V2.
5. Calculate the differential mode gain A calculate the CMRR

RESULT:
Thus the instrumentation amplifier was designed and tested and the outputs were plotted successfully.

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Ex. No.: 7
LOW PASS, HIGH PASS AND BAND PASS FILTERS
Date:

AIM:
To design and obtain the frequency response of First order Low Pass Filter(LPF)
First order High Pass Filter (HPF) Band pass filter

APPARATUS REQUIRED:

S.NO DESCRIPTION RANGE QUANTITY

1 IC 741 1
2 Resistors Variable 10k ohm 3
Resistor 1
20kΩ pot
3 Capacitors 0.01μf 1
4 Cathode Ray Oscilloscope (0 – 20MHz) 1
5 Regulated Power supply (0 – 30V),1A 1
6 Function Generator (1Hz – 1MHz) 1

THEORY:
a) LPF:
A LPF allows frequencies from 0 to higher cut of frequency, fH. At fH the gain is 0.707 Amax, and after
fH gain decreases at a constant rate with an increase in frequency. The gain decreases 20dB each time the
frequency is increased by 10. Hence the rate at which the gain rolls off after fH is 20dB/decade or 6 dB/
octave, where octave signifies a two fold increase in frequency. The frequency f=fH is called the cut off
frequency because the gain of the filter at this frequency is down by 3 dB from 0 Hz. Otherequivalent
terms for cut-off frequency are 3dB frequency, break frequency, or corner frequency.
b) HPF:
The frequency at which the magnitude of the gain is 0.707 times the maximumvalue of gain is
called low cut off frequency. Obviously, all frequencies higher than fL are pass band frequencies with
the highest frequency determined by the closed –loop band width all of the op- amp.
c) BAND PASS FILTER:
A band pass filter has a pass band between two cutoff frequencies fH and fL such that fH > fL. Any
input frequency outside this pass band is attenuated. There are two types of band-pass filters. Wide
band pass and Narrow band pass filters. We can define a filter as wide band pass if its quality factor Q
<10. If Q>10, then we call the filter a narrow band pass filter. A wide band pass filter can be formed
by simply cascading high-pass and low-pass sections. The order of band pass filter depends on the
order of high pass and low pass sections.

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DESIGN:

First Order LPF:

To design a Low Pass Filter for higher cut off frequency fH = 4 KHz and passband gain of 2
fH = 1/( 2πRC )
Assuming C=0.01 µF, the value of R is found fromR=
1/(2πfHC) Ω =3.97KΩ
The pass band gain of LPF is given by AF = 1+ (RF/R1)= 2
Assuming R1=10 KΩ, the value of RF is found from
RF=( AF-1) R1=10KΩ
First Order HPF:
To design a High Pass Filter for lower cut off frequency fL = 4 KHz andpass band gain of 2
fL = 1/( 2πRC )
Assuming C=0.01 µF,the value of R is found from
R= 1/(2πfLC) Ω =3.97KΩ
The pass band gain of HPF is given by AF = 1+ (RF/R1)= 2
Assuming R1=10 KΩ, the value of RF is found from
RF=( AF-1) R1=10KΩ
Band pass filter:
To design a band pass filter having fH = 4KHz and fL = 400Hz and passband gain of 2.
As shown in Fig, the first section consisting of Op Amp,RF,R1,R and C is the high pass filterand second
consisting of low pass filter. The design of low pass and high pass filters.
Low Pass Filter Design:
Assuming C’=0.01μf, the value of R’ is found from
R’ = 1/(2πfH C’) Ω =3.97KΩ
The pass band gain of LPF is given by ALPF = 1+ (R’ F / R’1 )=2
Assuming R’1=5.6 KΩ, the value of R’F is found from R’F =( AF-1) R’1=5.6KΩ
High Pass Filter Design:
Assuming C=0.01μf, the value of R is found from
R = 1/(2πfLC) Ω =39.7KΩ
The pass band gain of HPF is given by AHPF = 1+ (RF / R1 )=2
Assuming R1=5.6 KΩ, the value of RF is found
RF = ( AF-1) R1=5.6KΩ

PROCEDURE:
• First Order LPF & HPF
• Connections are made as per the circuit diagram
• Apply sinusoidal wave of constant amplitude as the input such that op-amp does notgo into
saturation.
• Vary the input frequency and note down the output amplitude at each step as shown inTable Plot the
frequency response
• Band pass filter:
• Connect the circuit as per the circuit diagram shown in Fig
• Apply sinusoidal wave of 0.5V amplitude as input such that opamp does not go intosaturation
(depending on gain). Vary the input frequency from 100 Hz to 100 KHz and note down the output amplitude
at eachstep as shown in Table.
• Plot the frequency response

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CIRCUIT DIAGRAM:

Fig 1: Low pass filter

Fig 2: High pass filter

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Fig 3:Wide band pass filter

Model graphs :

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TABULATION

a. LPF b) HPF
Input voltage Vin = V
Frequency O/P Gain Gain
Frequency O/P Voltage Gain
Voltage Vo/V i in dB
Voltage(V) Gain indB Vo(V)
Vo/Vi

d) BPF

Frequency O/P Voltage Gain

Voltage(V) Gain indB
Vo/Vi

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Viva questions and answers:

1. What is the relation between fC & fH, fL?

2. How do you increase the gain of the wideband pass filter?

By increasing the gain of either LPF or HPF

3. What is the difference between active and passive filters?
Active filters use Op Amp as active element, and resistors and capacitors as the passiveelements.
4. What is the effect of order of the filter on frequency response characteristics?
Each increase in order will produce -20 dB/decade additional increases in roll off rate.
5. What modifications in circuit diagrams require to change the order of the filter?
Order of the filter is changed by RC network.

RESULT:
Thus, the active LPF, HPF, BPF were designed and tested and the outputs were plottedsuccessfully.

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Ex. No.: 8 PLL CHARACTERISTICS AND FREQUENCY MULTIPLIER USING

Date: PLL
AIM:
To construct and study the operation of frequency multiplier using IC 565.
APPARATUS REQUIRED:

S.NO DESCRIPTION RANGE QUANTITY

1 IC 565,IC 7490,2N2222 - 1
2 Resistors 20 K , 2k , 1
4.7k ,10k
3 Capacitors 0.001 F 1 each
10 F
4 Function Generator 1 Hz – 2 MHz 1
(Digital)
5 C.R.O - 1
6 Dual Power Supply 0- 30 V 1
THEORY
In a frequency multiplier using PLL 565, a divided by N network is inserted between theVCO output
and the phase comparator input. Since the output of the comparator is locked tothe input frequency fin the
VCO is running at a multiple of the input frequency. Therefore in the locked state the VCO output
frequency is given by, f0 = Nfin
PROCEDURE:
1. The connections are given as per the circuit diagram.
2. The circuit uses a 4- bit binary counter 7490 used as a divide-by-5 circuit.
3. Measure the free running frequency of VCO at pin 4, with the input signal Vi set equal tozero.
Compare it with the calculated value = 0.25 / (RT CT).
4. Now apply the input signal of 1 VPP square wave at 500 Hz to pin 2.
5. Vary the VCO frequency by adjusting the 20k potentiometer till the PLL is
locked.Measure the output frequency.It should be 5 times the input frequency.
6. Repeat steps 4, 5 for input frequency of 1 kHz and 1.5 kHz.

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CIRCUIT DIAGRAM:

Design Procedure:
If 𝐶 = 0.01𝜇𝐹 and the frequency of input trigger signal is 2KHz, output pulse width of 555 in
Monostable mode is given by
1.1𝑅𝐴 𝐶 = 1.2𝑇 = 1.2/𝑓
1.2
𝑅𝐴 = = 54.5𝐾Ω
1.1𝐶𝑓
𝑓𝐼𝑁 = 𝑓𝑂𝑈𝑇 /𝑁
Under locked conditions,
𝑓𝑂𝑈𝑇 = 𝑁𝑓𝐼𝑁 = 2𝑓𝐼𝑁 = 4𝐾𝐻𝑧

Theory:
The frequency divider is inserted between the VCO and the phase comparator of PLL. Since the output of
the divider is locked to the input frequency 𝑓𝐼𝑁 , the VCO is actually running at a multiple of the input
frequency. The desired amount of multiplication can be obtained by selecting proper divide-by-N network,
where N is an integer. To obtain the output frequency 𝑓𝑂𝑈𝑇 = 2𝑓𝐼𝑁 , 𝑁 = 2 is chosen. One must determine
the input frequency range and then adjust the free running frequency 𝑓𝑂𝑈𝑇 of the VCO by means of R1 and
C1 so that the output frequency of the divider is midway within the predetermined input frequency range.
The output of the VCO now should be 2𝑓𝐼𝑁 . The output of the VCO should be adjusted by varying
potentiometer R1. A small capacitor is connected between pin7 and pin8 to eliminate possible oscillations.
Also, capacitor C2 should be large enough to stabilize the VCO frequency.

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PLL AS FREQUENCY MULTIPLIER

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PROCEDURE:

1. The circuit is connected as per the circuit diagram.

2. Apply a square wave input to the pin 2 of the 565.
3. Observe the output at pin4 of 565 under locked condition.
4. Give the output of 565 to the pin2 of 555 IC.
5. Observe the output of 555 at pin3.
6. Now give the output of 555 as feedback to the pin5 of the 565.
7. Observe the frequency of output signal fo at pin4 of 565 IC.
8. Plot the waveforms in graph.

Viva questions and answers

1. Mention the applications of PLL

Frequency multiplier, Frequency synthesizer, Frequency translation,Clock and data recovery

2. What is a voltage-controlled oscillator?

Voltage controlled oscillator is a free running multivibrator operating at a set frequency called the free
running frequency. This frequency can be shifted to either side by applying a dc control voltage and the
frequency deviation is proportional to the dc control voltage.

3. What are the applications of VCO?

VCO is used in FM, FSK, and tone generators, where the frequency needs to becontrolled by
means of an input voltage called control voltage.
4. What is PLL?
PLL is a control system that generates an output signal whose phase is related to thephase of input
Reference signal.
5. List the basic building blocks of PLL
*Phase detector/comparator *Low pass filter *Error amplifier *Voltage controlled oscillator
6. What are the three stages through which PLL operates?
*Free running *Capture *Locked/ tracking
7. Define lock-in range of a PLL.
The range of frequencies over which the PLL can maintain lock with the incoming signal iscalled the
lock-in range or tracking range. It is expressed as a percentage of the VCO free running frequency.

RESULT:
Thus, the PLL Characteristics are designed and tested and Frequency multiplier using IC
565 is constructed and tested.

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Ex. No.: 09
R-2R LADDER TYPE D- A CONVERTER USING OP-AMP.
Date:

Aim:
To design R-2R Ladder Type D- A Converter using Op-amp and observe the output.

Apparatus required:

S.No Components Specification Quantity

1. Op-amp
2. Resistor

3. Regulated Power supply

4. DC power supply

5. Multimeter

Theory:
A digital-to-analog converter (DAC, D/A, D2A or D-to-A) is a circuit that converts digital data(usually binary)
into an analog signal (current or voltage). One important specification of a DAC is its resolution. It can be
defined by the numbers of bits or its step size. Wide range of resistors used Weighted Resistor type DAC. This
can be avoided by using R-2R ladder type DAC where only two values of resistors are required.

Basic Block diagram of DAC.

DAC

The output voltage of DAC;

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To design 3 bit R-2R Digital to Analog converter to convert analog voltage of binary bit 100.

Theoretical Calculation:

If binary bit 011 :

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Tabul
ation:
Vref = -5V

d1 d2 d3 Theoretical V0 Practical V0

0 0 0

0 0 1

0 1 1 -2.4

0 1 1

1 0 0

1 0 1

1 1 0 -1.89

1 1 1

Procedure:

1. Check the component using multi meter.

2. Setup the circuit stage by stage on the breadboardVerify the working of circuit separately.
3. Complete the circuit and apply -5V ref if bit=1.Observe the output using multimeter.
4. Plot the output wave form on the graph sheet.

Result:
Thus R-2R Ladder Digital to Analog Converter circuit is designed and output is verified

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SIMULATION USING PSPICE

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Ex. No.: 10
TUNED COLLECTOR OSCILLATOR
Date:

AIM:
To simulate a tuned collector oscillator using PSPICE.

REQUIREMENTS:
1. PC
2. PSPICE software

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THEORY:
Tuned collector oscillation is a type of transistor LC oscillator where the tuned circuit (tank)
consists of a transformer and a capacitor is connected in the collector circuit of the transistor. Tuned
collector oscillator is of course the simplest and the basic type of LC oscillators. The tuned circuit
connected at the collector circuit behaves like a purely resistive load at resonance and determines the
oscillator frequency. The common applications of tuned collector oscillator are RF oscillator circuits,
mixers, frequency demodulators, signal generators etc.,

PROCEDURE:
1. Double click the PSPICE software icon the following screen will appear.
2. Schematic window will open and draw the given circuit by choosing the components from place
part.
3. Finish the circuit and save it.
4. Create new simulation profile and give simulation file name as tuned oscillator.sch
5. In simulation settings window set transient time initial value as 1ms and final value as 10ms and the
input voltage as AC=0.5V, DC=0V and offset voltage as 0V and appropriate amplitude and
frequency value.
6. Set the probe at the output and click Run.

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CIRCUIT DIAGRAM:

OUTPUT WAVEFORM:

INFERENCE:
Thus the tuned collector oscillator is simulated using PSpice.

VIVA QUESTIONS:

1. What is PSpice?
2. What is the use of Pspice?
3. What are the different types of analysis done using Spice?
4. List the limitation of Pspice
5. What are the different output commands?

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Ex. No.: 11
TWIN-T OSCILLATOR
Date:

AIM:
To simulate Twin-T Oscillator Circuit by using PSPICE.

REQUIREMENTS:
1. PC
2. PSPICE software
PROCEDURE:

1. Click on the start menu and select the pspice simulation software
2. Select the parts required for the circuit from the parts menu and place them in the work space
3. Connect the parts using wires
4. Save the file and select the appropriate analysis
5. Simulate the circuit and observe the corresponding output waveforms

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CIRCUIT DIAGRAM:

MODEL GRAPH:

INFERENCE:
Thus the Wein Bridge Oscillator is simulated using Pspice.

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Ex. No.: 12
Date: DOUBLE AND STAGGERED TUNED AMPLIFIER

AIM:
To simulate double and staggered tuned amplifiers.

REQUIREMENTS:
1. PC
2. PSPICE software
THEORY:

A double-tuned amplifier is a tuned amplifier with transformer coupling between the amplifier
stages in which the inductances of both the primary and secondary windings are tuned separately with
a capacitor across each. The scheme results in a wider bandwidth than a single tuned circuit would
achieve. There is a critical value of transformer coupling coefficient at which the frequency response
of the amplifier is maximally flat in the pass band and the gain is maximum at the resonant
frequency. Designs frequently use a coupling greater than this (over- coupling) in order to achieve an
even wider bandwidth at the expense of a small loss of gain in the centre of the pass band. Staggered
tuning is a technique used in the design of multi-stage tuned amplifiers whereby each stage is tuned
to a slightly different frequency. In comparison to synchronous tuning (where each stage is tuned
identically) it produces a wider bandwidth at the expense of reduced gain.

It also produces a sharper transition from the passband to the stopband. Both staggered tuning
and synchronous tuning circuits are easier to tune and manufacture than many other filter types. The
function of stagger-tuned circuits can be expressed as a rational function and hence they can be
designed to any of the major filter responses such as Butterworth and Chebyshev. The poles of the
circuit are easy to manipulate to achieve the desired response because of the amplifier buffering
between stages.

PROCEDURE:
1. Click on the start menu and select the pspice simulation software
2. Select the parts required for the circuit from the parts menu and place them in
the work space
3. Connect the parts using wires
4. Save the file and select the appropriate analysis
5. Simulate the circuit and observe the corresponding output waveforms

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CIRCUIT DIAGRAM:
DOUBLE TUNNED AMPLIFIER

MODEL GRAPH:

DOUBLE TUNNED AMPLIFIER

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STAGGER TUNED AMPLIFIER

OUTPUT WAVEFORM:

INFERENCE:
Thus the double and staggered tuned amplifier is simulated.

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Ex. No.: 13
BI-STABLE MULTIVIBRATOR
Date:

AIM:
To simulate an Bi-stable multi-vibrator using PSPICE.

REQUIREMENTS:
1. PC
2. PSPICE software
THEORY:
Bi- stable multivibrator contains two stable states and no quasi states. It requires two clock
or trigger pulses to change the states. It is also called as flip flop, scale of two toggle circuit, trigger
circuit. It is used in digital operations like counting, storing data’s in flip flops and production of
square waveforms.

PROCEDURE:
1. Click on the start menu and select the pspice simulation software
2. Select the parts required for the circuit from the parts menu and place them in
the work space
3. Connect the parts using wires
4. Save the file and select the appropriate analysis
5. Simulate the circuit and observe the corresponding output waveforms
CIRCUIT DIAGRAM:

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MODEL GRAPH:

INFERENCE:
Thus the Bi-stable multi-vibrator is simulated using PSpice.

VIVA QUESTIONS:

1. Define storage time of bi-stable multi-vibrator?

2. What are the different types of triggering of bi-stable multi-vibrator?
3. List the application of bi-stable multi-vibrator.
4. What is the use of triggering in bi-stable multi-vibrators?
5. Give the differences between three multi-vibrators.

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Ex. No.: 14 SCHMITT TRIGGER CIRCUIT WITH PREDICTABLE

Date: HYSTERESIS

AIM:
To simulate Schmitt Trigger circuit with Predictable hysteresis.

REQUIREMENTS:
1. PC
2. PSPICE software
THEORY:

A Schmitt trigger is a comparator circuit with hysteresis, implemented by applying positive

feedback to the input of an amplifier. It is an active circuit which converts an analog input signal to
a digital output signal. The circuit is named a "trigger" because the output retains its value until the
input changes sufficiently to trigger a change. In the non-inverting configuration, when the input is
higher than a certain chosen threshold, the output is high. When the input is below a different (lower)
chosen threshold, the output is low, and when the input is between the two levels, the outputretains
its value. This dual threshold action is called hysteresis and implies that the Schmitt trigger possesses
memory and can act as a bi-stable circuit (latch or flip-flop). There is a close relation between the two
kinds of circuits: a Schmitt trigger can be converted into a latch and a latch can be converted into a
Schmitt trigger.

Schmitt trigger devices are typically used in signal conditioning applications to remove noise
from signals used in digital circuits, particularly mechanical switch bounce. They are also used in
closed loop negative feedback configurations to implement relaxation oscillators, used in function
generators and switching power supplies.
PROCEDURE:

1. Click on the start menu and select the pspice simulation software
2. Select the parts required for the circuit from the parts menu and place them in
the work space
3. Connect the parts using wires
4. Save the file and select the appropriate analysis
5. Simulate the circuit and observe the corresponding output waveforms

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CIRCUIT DIAGRAM:

MODEL GRAPH:

INFERENCE:
Thus the Schmitt trigger is simulated using PSpice.

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Ex. No.: 15
ANALYSIS OF POWER AMPLIFIER
Date:

AIM:
To design and test the performance of power amplifier.

REQUIREMENTS:

S.No EQUIPMENTS RANGE QUANTITY

1 Resistors
2 RPS (0-30)V 1
3 Transistor BC107 1
4 CRO (0-30)MHz 1
5 Capacitor 3.2nf,25pf Each 1
6 Bread board - 1

DESIGN EXAMPLE:
Given specifications:
VCC= 12V; hfe = 200; f=1 KHz; I c = 2mA; Vce (sat) = 0.2v; VBB= - 2V,
(i) To calculate RC:
RC =VCC - Vce (sat) / IC
RC = 12 – 0.2 / 2x10-3=5.9KΩ

(ii) To calculate R:
IB2(min)=IC2 / hfe= 2x10-3 / 200 = 10µ A Select IB2 > IB1(min) (say 25µ A)

Then R = VCC – V BE (sat) / IB2 Therefore R= 12-0.7/25x10-6=452KΩ

(iii) To calculate C:
T=0.69RC
1x10-3= 0.69x452x103x C; C=3.2nf
(iv) To calculate R1 & R2:
VB1= {(VBB R1/ R1 +R2) + (VCE (sat) R2 / R1+R2)}
Since Q1 is in off state, VB1 ≤ 0
Then (VBB R1/ R1 +R2) = (VCE (sat) R2 / R1+R2) VBB R1 = VCE (sat) R2
2 R1 = 0.2 R2
Assume R1=10KΩ, then R2=100 KΩ
Consider, C1= 25pf (commutative capacitor)

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THEORY:
An electronic amplifier is used for increasing the power of a signal. It does this by taking
energy from a power supply and controlling the output to match the input signal shape but with a
larger amplitude. In this sense, an amplifier may be considered as modulating the output of the power
supply.

PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Give a negative trigger input to Q2.
3. Note the output of transistor Q2 and Q1.
4. Find the value of Ton and Toff.

CIRCUIT DIAGRAM:

MODEL GRAPH:

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EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

TABULATION:

Amplitude(V) Time period(msec)

TON TOFF

INFERENCE:
Thus the Power amplifier is designed and the performance is tested.
Theoretical period :
Practical period :

VIVA QUESTIONS:

1. Give the other names of power amplifier?

2. Write the importance of power amplifier?
3. What is the frequency of oscillation of power amplifier?
4. List the different types of power amplifier.
5. List the applications of power amplifier.

EC3462_LIC_LAB_R2021 66

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4931_Grace College of Engineering, Thoothukudi
EC3462-Linear Integrated Circuits Laboratory Dept of Electronics and Communication Engg

Ex. No.: 16
VOLTAGE AND CURRENT TIME BASE CIRCUITS
Date:

AIM:
To simulate voltage and current time base circuits by using PSPICE.
REQUIREMENTS:
1. PC
2. PSPICE software
THEORY:

A time base generator, or timebase, is a special type of function generator, an electronic

circuit that generates a varying voltage to produce a particular waveform. Time base generators
produce very high frequency sawtooth waves specifically designed to deflect the beam in cathode ray
tube (CRT) smoothly across the face of the tube and then return it to its starting position.

Time bases are used by radar systems to determine range to a target, by comparing the current
location along the time base to the time of arrival of radio echoes. Analog television systems using
CRTs had two time bases, one for deflecting the beam horizontally in a rapid movement, and another
pulling it down the screen 60 times per second. Oscilloscopes often have several time bases, but these
may be more flexible function generators able to produce many waveforms as well as a simple time
base.

PROCEDURE:
1. Click on the start menu and select the pspice simulation software
2. Select the parts required for the circuit from the parts menu and place them in the work
space
3. Connect the parts using wires
4. Save the file and select the appropriate analysis
5. Simulate the circuit and observe the corresponding output waveforms
CIRCUIT DIAGRAM:

VOLTAGE TIME BASE CIRCUIT

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CURRENT TIME BASE CIRCUIT

MODEL GRAPH:

CURRENT TIME BASE CRCUIT

INFERENCE:
Thus the Voltage and Current time base circuits are
simulated using Pspice.

EC3462_LIC_LAB_R2021

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