DesignWare Cores Mobile Storage Host

Controller
DWC_mshc / DWC_mshc_lite

Databook
DWC_mshc – Product Code: A555-0
DWC_mshc_lite – Product Code: B143-0

Version 1.90a
March 2021
 Mobile Storage Host Controller Databook

Copyright Notice and Proprietary Information

© 2021 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use,
reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals
of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and
to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE.
Trademarks
Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at
https://www.synopsys.com/company/legal/trademarks-brands.html
All other product or company names may be trademarks of their respective owners.
Free and Open-Source Software Licensing Notices
If applicable, Free and Open-Source Software (FOSS) licensing notices are available in the product installation.
Third-Party Links
Any links to third-party websites included in this document are for your convenience only. Synopsys does not endorse and is not
responsible for such websites and their practices, including privacy practices, availability, and content.

Synopsys, Inc.
www.synopsys.com

2 SolvNetPlus Synopsys, Inc. Version 1.90a

DesignWare March 2021
Mobile Storage Host Controller Databook

Contents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Databook Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Related Product Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Web Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Synopsys Statement on Inclusivity and Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 1
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1 General Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.2 System-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.4 Supported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4.1 General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4.2 Supported Features for Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5 Unsupported Features and Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6 Standards Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6.1 Memory Capacities Supported by the SD Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.7 Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.8 Interoperability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.9 Speed and Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.10 Compliance with Quality Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.10.1 Coding and Design Guidelines and Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.10.2 Testing and Development Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.11 Hardware and Software Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Chapter 2
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.1 Overview of Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2 Device and Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.1 Overview of the Device and Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.2 Configuring the Device and Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.3 SD/UHS-II Register Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.4 SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.5 UHS-II Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.6 eMMC Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Version 1.90a Synopsys, Inc. SolvNetPlus 3

March 2021 DesignWare
Contents Mobile Storage Host Controller Databook

2.2.7 Output Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.2.8 Input Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.3 Master Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.3.1 Overview of the Master Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.3.2 Configuring the Master Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.3.3 AXI Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.3.4 AHB Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.4 AHB Slave Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.4.1 Overview of the AHB Slave Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.4.2 Description of AHB Slave Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.4.3 Configuring AHB Slave Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.5 Low-Speed SDR Support without PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.5.1 Overview of Low-Speed SDR Support without PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.6 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.6.1 Overview of JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.6.2 JTAG Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.6.3 Description of JTAG Registers Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.7 DMA vs Slave Mode of Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.7.1 Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.7.2 Slave-Only Mode of Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.8 DMA Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.8.1 Overview of the DMA Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.8.2 Configuring DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.8.3 Selecting the DMA FIFO Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.9 SRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.9.1 Overview of SRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.9.2 SPRAM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.10 Data Flow for Card Read in DWC_mshc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.10.1 Packet Buffer Size Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.11 Tuning in DWC_mshc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.11.1 Overview of Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.11.2 Tuning Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.11.3 Mode 1 Re-Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.11.4 Software Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.11.5 Auto-Tuning or Mode 3 Re-Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.11.6 Signals Related to Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.11.7 Registers Related to Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.11.8 Programming Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.11.9 Implementation Guidelines While Using Auto-Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.11.10 PHY Timing and Placement Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.11.11 Internal Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.11.12 Technology-Specific Cells for Auto-Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
2.12 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
2.12.1 Packet Buffer Full/Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.13 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2.14 Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2.14.1 SD/eMMC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2.14.2 UHS-II Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.15 DFT Features for Synopsys SD/eMMC PHY Production Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4 SolvNetPlus Synopsys, Inc. Version 1.90a

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Mobile Storage Host Controller Databook Contents

2.15.1 Pseudo Random Pattern Generation (PRBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

2.15.2 Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
2.16 Debug User Sideband Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Chapter 3
Parameter Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Chapter 4
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Chapter 5
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Appendix A
Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
A.1 Signals Between Host and Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
A.2 Bus Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
A.3 Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
A.3.1 SD Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
A.3.2 UHS-II Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
A.3.3 eMMC Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
A.4 Range Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
A.5 Transaction Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
A.6 Control and Data Transaction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
A.7 UHS-II Interface Selection Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
A.8 Application Layer Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
A.8.1 ADMA2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
A.8.2 ADMA3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
A.8.3 Command Queueing Task Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
A.8.4 eMMC Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
A.9 SDIO Read Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
A.10 SDIO Card Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

Appendix B
Synchronizer and Technology Specific Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
B.1 Synchronizers Used in DWC_mshc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
B.1.1 Synchronizer 1: Simple Double Register Synchronizer (DWC_mshc_bcm21.v) . . . . . . . . . . . . . . 596
B.1.2 Synchronizer 2: Pulse Synchronizer (DWC_mshc_bcm22.v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
B.1.3 Synchronizer 3: Simple Multiple Register Synchronizer with Configurable Polarity Reset . . . . . 601
B.1.4 Synchronizer 4: Dual Independent clock FIFO (DWC_mshc_bcm74.v) . . . . . . . . . . . . . . . . . . . . . 601
B.1.5 Synchronizer 5: Pulse Synchronizer with Acknowledge (DWC_mshc_bcm23.v) . . . . . . . . . . . . . 602
B.2 Technology-Specific Cells in DWC_mshc DWC_mshc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
B.2.1 The DWC_mshc_clk_mux_2x1.v Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
B.2.2 The DWC_mshc_ddr_mux_2x1.v Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
B.2.3 The DWC_mshc_clk_gate.v Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
B.2.4 The DWC_mshc_clkgate_cell.v Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
B.2.5 The DWC_mshc_bcm21.v Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
B.2.6 The DWC_mshc_ddr_mux_sel Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

Appendix C
Power Consumption and Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609

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C.1 Clock Gating Types Used for Generating Power and Area Numbers for Non-AXI Configuration (AHB
Master and AHB slave port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
C.2 Technology Libraries Used to Generate Power and Area Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
C.2.1 Power and Area for an SD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
C.2.2 Power and Area for a UHS-II Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
C.2.3 Power and Area for an eMMC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
C.2.4 Maximum Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
C.2.5 Area in Slave-Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
C.2.6 Area and Power With Context Sensitive Clock Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
C.2.7 Area Savings Without ADMA3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
C.2.8 Area Savings While Using Optimized Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
C.3 Design for Testability for Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623

Appendix D
Clock and Data Crossing (CDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
D.1 DWC_mshc Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
D.2 Metastability Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
D.3 Asynchronous Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
D.4 Naming Convention Used for CDC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
D.5 Naming Convention Used for Synchronizer (BCM) Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
D.5.1 Context-Sensitive Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
D.5.2 Optimized Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Appendix E
Clock Domain for Individual Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631

Appendix F
Frequently Asked Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

Appendix G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Terms and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

Chapter H
Internal Parameter Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

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Revision History

The following table provides a summary of changes made to this Databook.

Date Release Description

March 2021 1.90a ■ Updated

- “Supported Features” on page 22
- Chapter 3, “Parameter Descriptions”
- Chapter 4, “Signal Descriptions”
- Chapter 5, “Register Descriptions”
- Chapter H, “Internal Parameter Descriptions”
■ Added
- “Output Data Path for HS400 with Data Output on Negedge
(DWC_MSHC_NEG_DATA_HS400_MODE = 1)” on page 37
- “The DWC_mshc_clkgate_cell.v Module” on page 605
- “Debug User Sideband Signals” on page 101

May 2019 1.80a ■ Updated

- “DWC_mshc_crypto Block Diagram” on page 16
- “Overview of Architecture” on page 26
- “Output Data Path” on page 31
- Appendix C, “Power Consumption and Area”
- “Parameter Descriptions” on page 99
- “Signal Descriptions” on page 157
- “Register Descriptions” on page 229
- “Internal Parameter Descriptions” on page 657
■ Added
- “Input Data/CMD Path in SD/eMMC mode
(DWC_MSHC_LS_NO_PHY_MODE = 0)” on page 35
- “Input Data/CMD Path in Low Speed SDR No PHY Mode” on
page 37
- “Low-Speed SDR Support without PHY” on page 51
- “JTAG Interface” on page 52
- Appendix E, “Clock Domain for Individual Registers”

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Date Release Description

October 2017 1.70a ■ Added

- “Pseudo Random Pattern Generation (PRBS)” on page 96
- “Loopback Mode” on page 96
- “DFT Features for Synopsys SD/eMMC PHY Production Tests”
on page 96
- “The DWC_mshc_ddr_mux_sel Module” on page 620
- “Synchronizer 5: Pulse Synchronizer with Acknowledge
(DWC_mshc_bcm23.v)” on page 616

April 2017 1.60a ■ Added

- “Threshold Based Selection Tuning Schema” on page 75
- “Largest Sampling Window Tuning Schema” on page 76
- “Clock Domain for Individual Registers” on page 536
- “Input Data” on page 39
- Related Parameters:
- DWC_MSHC_TUNE_WINTH_EN = 1
- DWC_MSHC_TUNE_WINTH_VAL = <as required for design>
- DWC_MSHC_TUNE_WINTH_EN = 1
- DWC_MSHC_TUNE_WINTH_VAL = 0
- DWC_MSHC_TUNE_WINTH_EN = 0
- DWC_MSHC_TUNE_WINTH_VAL = don't care
- Registers:
- AT_CTRL_R.SWIN_TH_EN = 1
- AT_CTRL_R.SWIN_TH_VAL = <as required for design
- AT_CTRL_R.SWIN_TH_EN = 1
- AT_CTRL_R.SWIN_TH_VAL = 0
- AT_CTRL_R.SWIN_TH_EN = 0
- AT_CTRL_R.SWIN_TH_VAL = don't care
■ Updated
- Auto-extracted chapters
■ Reorganized the “Architecture” chapter to contain Functional
Description chapter details.
■ Moved Implementation Guidelines information to the DWC_mshc
User Guide

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Date Release Description

June 2016 1.50a ■ Added:

- “Tuning in DWC_mshc” on page 71
- “Context-Sensitive Clock Gating” on page 498, “Optimized
Clocking Mode” on page 499 and “SD/UHS-II Register
Optimization” on page 499
- “DMA Configuration” on page 497
- “Naming Convention Used for CDC Signals” on page 640 and
“Naming Convention Used for Synchronizer (BCM) Instances”
on page 641
- “Implementation Guidelines While Using Auto-Tuning” on
page 503
- Definition for CG in “Clock Gating Types Used for Generating
Power and Area Numbers for Non-AXI Configuration (AHB
Master and AHB slave port)” on page 625
- “Area and Power With Context Sensitive Clock Gates” on
page 636
- “Area Savings Without ADMA3 Mode” on page 636
- “Area Savings While Using Optimized Clocking Mode” on
page 636
- “Technology-Specific Cells in DWC_mshc” on page 500
- Parameters:
- DWC_MSHC_CLKS_GROUP_EN
- DWC_MSHC_CLKS_GROUP_SEL
- DWC_MSHC_OPT_REGS
- DWC_MSHC_AXI_MAX_RD_REQUESTS
- DWC_MSHC_AXI_MAX_WR_REQUESTS
- Signals:
- autotuning_cclk_sel
- autotuning_cclk_sel_update
- drift_cclk_rx
- cresetn_drx

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Date Release Description

- Added registers:
- AT_CTRL_R
- AT_STAT_R
- MSHC_CTRL_R
- Terms BSYN and LSS in Appendix G, “Standard Terms and
Definitions”
■ Moved:
- The “Power Consumption and Area” section to Appendix C,
“Power Consumption and Area”
- The “Internal Parameter Descriptions” chapter to Appendix H,
“Internal Parameter Descriptions”
■ Updated:
- Auto-extracted chapters
- Signals:
- tuning_cclk_sel
- tuning_cclk_sel_update
- SD Part 1 Physical Layer Specification in “Standards
Compliance” on page 24
- “Frequently Asked Questions” on page 651

February 2016 1.40a ■ Added “System Bus Master Interface Overview” on page 49 to
explain support for AHB Master Bus interface
■ Updated following sections to include AHB master interface:
- “DWC_mshc supports the following interfaces:” on page 20
- “Standards Compliance” on page 24
- “Following are various modules in the Mobile Storage Host
Controller:” on page 32
■ Restructured tables for power and area in “Compliance with Quality
Metrics” on page 27
■ Created table for error type and categories in “SD/eMMC Mode” on
page 94 and “UHS-II Mode” on page 95
■ Added AHB Master Bus interface parameter in “Parameter
Descriptions” on page 99
■ Added AHB Master Bus interface signals in Chapter 4, “Signal
Descriptions”
■ Updated “Supported Features” on page 22 to include support for
slave-only mode configuration
■ Included Overview section in Chapter 5, “Register Descriptions”
■ Added “Configuration Options” on page 496 to explain the slave-
only mode of operation of DWC_mshc.
■ Added Appendix D, “Clock and Data Crossing (CDC)”.
■ Updated the “Standards Compliance” on page 24 section to
mention compliance with SD 5.0 and AMBA 2 AHB for Master port
specifications.

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Date Release Description

October 2015 1.30a ■ Updated “Supported Features” on page 22 to include support for
SDIO protocol, and AXI 64-bit data and address width.
■ Updated “Unsupported Features and Exceptions” on page 23,
“Standards Compliance” on page 24, “Speed and Clock
Requirements” on page 26
■ Updated power numbers in “Technology Libraries Used to
Generate Power and Area Numbers” on page 625 and added
following sections:
- “Default Configuration When AXI Data Width = 32 and AXI
Address Width = 32”
- “Default Configuration When AXI Data Width = 64 and AXI
Address Width = 32”
- “Default Configuration When AXI Data Width = 64 and AXI
Address Width = 64”
■ Updated area numbers in “Area” and modified Table 1-21 on page
30 and Table 1-22
■ Updated “Following are various modules in the Mobile Storage
Host Controller:” on page 32 to include support for AXI 64-bit data
bus width.
■ Added sections “” on page 37, “AHB Slave Interface” on page 48
and “AXI Master Interface” on page 40
■ Added section “Packet Buffer Size Calculation” on page 493
■ Reorganized “UHS-II Bus Protocol” on page 581
■ Added “eMMC Bus Protocol” on page 587
■ Modified “ADMA2 Operation” on page 595 and “ADMA3 Operation”
on page 596
■ Added “Command Queueing Task Descriptor” on page 599
■ Added “eMMC Data Structures” on page 600
■ Added “SDIO Read Wait” on page 606 and “SDIO Card Interrupt”
on page 606
■ Updated description for DWC_MSHC_PKT_BUFFER_DEPTH in
“Parameter Descriptions” on page 99
■ Updated description for signals hsize[2:0], htrans[1:0], and
hresp[1:0]
■ Modifications in “Register Descriptions” on page 209:
- Added the MSHC_VER_TYPE_R register
- Updated description for the MSHC_VER_ID_R.MSHC_VER_ID
bit
- Included SDIO-related note in description for
XFER_MODE_R.AUTO_CMD_ENABLE bit
- Changed “GP_IN” to “GP_OUT” for GP_OUT_R register
■ Updated “Standard Terms and Definitions” on page 655 to include
additional terms

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Date Release Description

July 2015 1.20a ■ Added eMMC 5.1 support.

■ Added support for UHS-II ADMA3 and HD modes.
■ Added Appendix A, “Protocol Overview”
■ Added Appendix G, “Standard Terms and Definitions”
■ Updated to include DWC_mshc_lite product information

March 2015 1.10a ■ Added eMMC 5.0 support.

■ Added GPIO support.
■ Added support for gating the clock to UHS-II module when it is not
enabled.

November 2014 1.00a First version of the document.

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Preface

This databook provides the general product description, system level overview and application level usage
model for the Synopsys DesignWare® Cores Mobile Storage Host Controller (DWC_mshc). The terms
“DWC_mshc”, "DWC_mshc_lite" and “hardware” all refer to the Mobile Storage Host Controller product.
The terms “system bus” and “SoC bus” are used interchangeably.
For more details on usage of the DWC_mshc/DWC_mshc_lite, refer to the DesignWare Cores Mobile Storage
Host Controller User Guide.

The DWC_mshc and DWC_mshc_lite products support features listed in “General Features”
Note on page 22, except that the Command Queuing Engine (CQE) features are applicable only to
the DWC_mshc product.
For information on licensing requirements for DWC_mshc and DWC_mshc_lite products, see
DesignWare Cores DWC_mshc Installation Guide.

This preface contains the following sections

■ “Product Description” on page 13
■ “Databook Organization” on page 13
■ “Related Product Information” on page 14
■ “Synopsys Statement on Inclusivity and Diversity” on page 15

Product Description
This document describes the Synopsys DesignWare Cores Mobile Storage Host Controller Core, known as
DWC_mshc/DWC_mshc_lite. It is a highly configurable and programmable high performance mobile
storage host controller with AXI/AHB as the bus interface for data transfer.
DesignWare DWC_mshc/DWC_mshc_lite core corresponds to DWC_mshc/DWC_mshc_lite in the
SolvNet database.

Databook Organization
The chapters of this databook are organized as follows:
■ Chapter 1, “Product Overview” introduces the DWC_mshc features, supported standards, and
architecture.
■ Chapter 2, “Architecture” provides an overview of the functionality of DWC_mshc.

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■ Chapter 3, “Parameter Descriptions” describes the DWC_mshc configuration options and parameters
■ Chapter 4, “Signal Descriptions”describes the DWC_mshc top-level signals.
■ Chapter 5, “Register Descriptions”, provides a memory map of DWC_mshc and the descriptions of
the programmable software registers.
■ Appendix A, “Protocol Overview”, provides an overview of protocols that are supported in the SD
and UHS-II mode of operations in DWC_mshc.
■ Appendix B, “Synchronizer and Technology Specific Cells”, documents the synchronizer methods
(blocks of synchronizer functionality) used in DWC_mshc to cross clock boundaries.
■ Appendix C, “Power Consumption and Area”discusses the power consumption and area for various
configurations of DWC_mshc
■ Appendix D, “Clock and Data Crossing (CDC)”, provides information about clocks and metastability
simulation in DWC_mshc.
■ Appendix H, “Internal Parameter Descriptions”, provides a list of internal parameter descriptions
that might be indirectly referenced in expressions in the Signals, Parameters, or Registers chapters.
■ Appendix F, “Frequently Asked Questions”, provides answers to frequency asked questions while
configuring DWC_mshc.
■ Appendix G, “Standard Terms and Definitions”, defines standard terms used in DWC_mshc
documentation.

Related Product Information

Refer to the following documentation:
■ Verification IP (VIP)
To run simulations in coreConsultant, the testbench uses the following:
❑ Synopsys emmc_svt VIP
■ Packaged with DWC_mshc coreKit
■ Installed when the DWC_mshc coreKit is unpacked and installed
❑ Synopsys Discovery SVT AXI VIP
■ Download from the SolvNet Download Center
For more information, refer DesignWare Cores DWC_mshc Installation Guide.
■ Synopsys Tools
❑ coreConsultant User’s Guide

Web Resources
■ DesignWare IP product information: http://www.designware.com
■ Your custom DesignWare IP page: http://www.mydesignware.com
■ Documentation through SolvNet: http://solvnet.synopsys.com (Synopsys password required)

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■ Synopsys Common Licensing (SCL): http://www.synopsys.com/keys

Synopsys Statement on Inclusivity and Diversity

Synopsys is committed to creating an inclusive environment where every employee, customer, and partner
feels welcomed. We are reviewing and removing exclusionary language from our products and supporting
customer-facing collateral. Our effort also includes internal initiatives to remove biased language from our
engineering and working environment, including terms that are embedded in our software and IPs. At the
same time, we are working to ensure that our web content and software applications are usable to people of
varying abilities. You may still find examples of non-inclusive language in our software or documentation
as our IPs implement industry-standard specifications that are currently under review to remove
exclusionary language.

Customer Support
To obtain support for your product, prepare the required files and contact the support center using one of
the methods described:
■ Prepare the following debug information, if applicable:
❑ For environment set-up problems or failures with configuration, simulation, or synthesis that
occur within coreConsultant or coreAssembler, select the following menu:
File > Build Debug Tar-file
Check all the boxes in the dialog box that apply to your issue. This option gathers all the
Synopsys product data needed to begin debugging an issue and writes it to the
<core tool startup directory>/debug.tar.gz file.
❑ For simulation issues outside of coreConsultant or coreAssembler:
■ Create a waveforms file (such as VPD or VCD).
■ Identify the hierarchy path to the DesignWare instance.
■ Identify the timestamp of any signals or locations in the waveforms that are not understood.
■ For the fastest response, enter a case through SolvNetPlus:
a. https://solvnetplus.synopsys.com

SolvNetPlus does not support Internet Explorer. Use a supported browser such
Note as Microsoft Edge, Google Chrome, Mozilla Firefox, or Apple Safari.

b. Click the Cases menu and then click Create a New Case (below the list of cases).
c. Complete the mandatory fields that are marked with an asterisk and click Save.
Make sure to include the following:
■ Product L1: DesignWare Cores
■ Product L2: Mobile Storage
■ Product L3: DWC_mshc /DWC_mshc_lite
d. After creating the case, attach any debug files you created.
For more information about general usage information, refer to the following article in SolvNetPlus:

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https://solvnetplus.synopsys.com/s/article/SolvNetPlus-Usage-Help-Resources
■ Or, send an e-mail message to [email protected] (your email will be queued and then,
on a first-come, first-served basis, manually routed to the correct support engineer):
■ Include the Product L1 and Product L2 names, and Version number in your e-mail so it can be
routed correctly.
■ For simulation issues, include the timestamp of any signals or locations in waveforms that are
not understood
■ Attach any debug files you created.
■ Or, telephone your local support center:
■ North America:
Call 1-800-245-8005 from 7 AM to 5:30 PM Pacific time, Monday through Friday.
■ All other countries:
https://www.synopsys.com/support/global-support-centers.html

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1
Product Overview

The DesignWare Cores DWC_mshc/DWC_mshc_lite, is a highly configurable and programmable, high

performance mobile storage host controller with AXI/AHB as the bus interface for data transfer. You can
use coreConsultant to configure your specific design implementation of the DWC_mshc controller. For
information on how to download and install the DWC_mshc, refer to the DesignWare Cores DWC_mshc
Installation Guide.

The DWC_mshc and DWC_mshc_lite products support features listed in “General Features”
Note on page 22, except that the Command Queuing Engine (CQE) features are applicable only to
the DWC_mshc product.
For information on licensing requirements for DWC_mshc and DWC_mshc_lite products, see
DesignWare Cores DWC_mshc Installation Guide.

This chapter provides a general description of the DesignWare DWC_mshc solution and includes the
following topics:
■ “General Product Description” on page 18
■ “System-Level Block Diagram” on page 20
■ “Applications” on page 21
■ “Supported Features” on page 22
■ “Unsupported Features and Exceptions” on page 24
■ “Standards Compliance” on page 25
■ “Deliverables” on page 27
■ “Interoperability” on page 27
■ “Speed and Clock Requirements” on page 27
■ “Compliance with Quality Metrics” on page 28
■ “Hardware and Software Partition” on page 28

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1.1 General Product Description

DWC_mshc is a configurable Secure Digital (SD) and eMMC host controller IP that is required to
communicate with memory cards targeted for the mobile/portable markets. DWC_mshc adheres to the SD
or eMMC specification and includes the following:
■ Mobile Storage Host Controller: It is highly configurable and programmable, and provides high
performance mobile storage host controller with AXI/AHB as the bus interface for data transfer
(master interface) and AHB as its slave interface.
■ Verification environment: It provides an example test bench that can help you run specific tests on
the DWC_mshc with your specific configuration, before integrating the DWC_mshc into your SoC
design.
For an overview of protocols that are supported in the SD and UHS-II mode of operations in DWC_mshc,
refer to “Protocol Overview” on page 563.
The coreConsultant and coreAssembler tools are available for automated configuration, simulation, and
synthesis of the DWC_mshc.
DWC_mshc is designed to be scalable towards evolution of the SD standard and also towards high speed
requirements. DWC_mshc is backward compatible with previous versions of the SD standards.
DWC_mshc supports 4-bit data bus width, and UHS-I interface towards the physical layer in the legacy SD
modes in addition to supporting the UHS-II interface with SD-TRAN. For the eMMC interface, DWC_mshc
also supports 4-bit, and 8-bit data bus widths.

DWC_mshc is compliant with SD Host Specifications and eMMC command

Note queuing (CQ) host controller interface (HCI) specifications. Therefore, standard
software drivers are expected to work on this IP.

DWC_mshc provides a flexible bus interface that enables you to integrate DWC_mshc into embedded
applications for system-on-a-chip (SoC) designs. DWC_mshc has an AXI and AHB master interface that
supports 32-bit and 64-bit address and data bus. Besides supporting non-DMA mode, DWC_mshc supports
various DMA options such as SDMA, ADMA2, and ADMA3 as specified in the SD Host Controller
Standard.
Based on the chosen configuration, DWC_mshc can have one of the following interface modes as shown in
Figure 1-1.

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Figure 1-1 Supported Interfaces in DWC_mshc

AXI/AHB Master

AXI/AHB Master
AHB Slave

AHB Slave
Controller Controller

SD/UHS-I/eMMC

SD/UHS-I/eMMC

UHS-II
Table 1-1 lists various modes supported in DWC_mshc.

Table 1-1 DWC_mshc Modes and their Usage

Mode Usage

SD Mode Supports SD, SDIO, and UHS-I modes but does not support UHS-II mode.

UHS-II Mode Supports SD and UHS-II modes.

eMMC Mode Supports eMMC version 5.1.

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1.2 System-Level Block Diagram

DWC_mshc bridges the SoC bus and UHS-II PHYs/Line drivers. DWC_mshc also includes RAM interfaces
for data storage. The descriptor caching and register caching are done internally. The data storage memory
must be instantiated external to DWC_mshc.

Figure 1-2 DWC_mshc Block Diagram

System CPU

SD/UHS-I/eMMC
Line Drivers
System Memory
Controller
UHS-II PHY

Application Processor

SPRAM

InterfacesDWC_mshc supports the following interfaces:

■ AHB slave interface
The AHB slave interface is designed to integrate with the AMBA High-Performance Bus (AHB) on
the application side. This is a slave interface to host CPU and is used for programming host controller
registers.
■ Master interface
DWC_mshc supports configurable master interfaces. You can either select AHB or AXI as a protocol
for the bus master interface.
❑ AHB master interface
The AHB master interface is designed to integrate with the AHB Master Bus Interface unit that is
compliant with the AMBA 2.0 Specification. The AHB master interface is used to translate
Read/Write transfers initiated by the DMA/CQE (using a generic master interface) into AHB-
compliant transfers on the system bus. The AHB interface transfers the data to and from the
system memory through AHB master interface.
❑ AXI master interface
The AXI interface is designed to integrate with AMBA Advanced Extensible Interface Bus (AXI)
on the application side. AMBA AXI 3 protocol for master interface is supported. The AXI master
interface is used for translates Read or Write transfers initiated by the DMA/CQE (using a
generic master interface) into AXI 3-compliant bus transfers. The AXI interface transfers the data
to and from the system memory through AXI master interface.
■ JTAG Interface
❑ The JTAG interface is used for programming MSHC registers in test mode only.
■ SD/eMMC interface

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The SD/eMMC interface is used to connect the SD/eMMC bus of the SD card. It consists of
command and data signals. SD supports a 4-bit interface and eMMC supports a 4-bit/8-bit interface.
■ UHS-II Link-PHY interface
The UHS-II Link-PHY interface is used to connect host controller to UHS-II PHY. It supports full
duplex and half-duplex modes. This interface is compliant with PHY-LINK I/F defined in Appendix
F of the UHS-II Addendum Version 1.01 specification.

1.3 Applications
DWC_mshc primarily targets host-controller and card-reader applications. In such instances, the device
memory card to which the DWC_mshc sends or receives data is typically a device for FLASH mass storage.
The DWC_mshc is optimized for the following applications and systems:
■ Portable electronic devices
■ High-speed storage applications
Specifically, DWC_mshc is targeted at these devices:
■ Mobile phones and laptops
■ Digital cameras and camcorders
■ Printer devices
■ Embedded applications

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1.4 Supported Features

The DWC_mshc controller supports the following features:
■ “General Features” on page 22
■ “Supported Features for Interfaces” on page 23

1.4.1 General Features

■ Supports SD memory and SD Input/Output (SDIO) digital interface protocol, and compliant with SD
HCI specification
■ Uses the same SD-HCI register set for eMMC transfers
■ Supports SD memory UHS-II interface protocol
■ Supports eMMC protocols including eMMC 5.1
■ Supports SD-HCI Host version 4 mode or less
■ Supports the following data transfer types for SD, eMMC, and UHS-II modes:
❑ CPU
❑ SDMA
❑ ADMA2
❑ ADMA3
■ Supports independent controller, Slave Interface and Master Interface clocks
■ Supports gating of controller base clock if Host Controller is inactive
■ Support context aware functional clock gates
■ Applications can gate the slave interface clock if Host Controller is inactive
■ Data Buffering
❑ Configurable buffer depth. Configurable in coreConsultant/coreAssembler.
❑ Automatic packing/unpacking of data to fit buffer width
■ Interrupt Outputs
❑ Combined and separate interrupt outputs
❑ Supports interrupt enabling and masking
■ Supports Command Queuing Engine (CQE) and compliant with eMMC CQ HCI
❑ Programmable scheduler algorithm selection of task execution
❑ Supports data prefetch for back-to-back WRITE operations
■ Supports Slave-Only mode as a configuration option for better area and power efficiency
■ Supports tuning:
❑ SD/eMMC Tuning using CMD19 (SD) or CMD21 (eMMC)

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❑ Mode 1 Re-Tuning – Host driver maintains the re-tune timer

❑ Fully Software driven Tuning/Re-tuning operations
❑ Auto-tuning or Mode 3 Re-tuning
■ Support for both Flip-flop based and Latch based clock gating.
■ Support for debug sideband signals db_*_task_id, db_*_pyld_descr in CQE mode.

1.4.2 Supported Features for Interfaces

■ SD
❑ Supports 4-bit interface
❑ Supports UHS-I mode
❑ Supports Default Speed (DS), high-speed (HS), SDR12, SDR25, SDR50 and SDR104 speed modes
❑ Supports SDIO read wait
❑ Supports SDIO card interrupts in both 1-bit and 4-bit modes
❑ Wake up on card interrupt
■ eMMC
❑ Supports 4-bit/8-bit interface
❑ Supports legacy, high-speed SDR, high-speed DDR, HS200, and HS400 speed modes
❑ Supports boot operation and alternative boot operation
■ UHS-II
❑ Supports 8-bit/16-bit data width for UHS-II Link-PHY interface
❑ Supports UHS-II FD156 (Full Duplex) and UHS-II HD312 (Half Duplex) modes
■ AHB Slave Interface
❑ Supports 32-bit data width and address width
❑ Transfer size (width) used for slave interface can be less than data bus width
■ AXI/AHB Master Interface
❑ Supports 32-bit and 64-bit address and data width
❑ Complies with the AMBA 3 AXI for Master Port specification
❑ Complies with the AMBA 2 AHB for Master Port specification

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1.5 Unsupported Features and Exceptions

The DWC_mshc does not support the following features:
■ Bus locking on master interface in AMBA AXI 3 mode
■ Wrap address transfers
■ eMMC boot operation in dual-data-rate mode
■ Suspend/Resume operation in an SDIO card
■ SDIO operation in UHS-II mode
■ Serial Peripheral Interface (SPI) protocol mode of operation
■ Interrupt input pins for embedded SD system
■ AHB slave back-to-back transfers (write followed by read with overlapping data phase of write and
address phase of read) to the same address for synchronous clock domains
■ UHS-III speed mode
■ CRC error due to UHSII-PHY error (uhs2_st[3]) for DWC_MSHC_PHY_LINK_WIDTH = 8 bits

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1.6 Standards Compliance

The DWC_mshc conforms to the following specifications or standards:
■ JEDEC eMMC 5.1 Specification - JESD84-B51, February 2015
❑ This specification describes the eMMC card design guidelines, protocol, electrical interface, its
environment, and handling.
■ SD Specifications Part A2 SD Host Controller Standard Specification Version 4.20, August 2015
❑ This specification describes guidelines for standard host controller drivers including the register
maps and the descriptor structures as well as the various DMA modes.
■ SD Specifications Part A2 Host Controller Version 4.20 Supplementary Notes Version 1.00 Draft 0.60
December, 2015
❑ This describes some clarifications and updates for the Host Controller Standard Specification
Version 4.20, August 2015.
■ SD Specifications Part 1 Physical layer Specification Version 6.00 February, 2017
❑ This specification describes the physical layer interface used by SD Memory card.
❑ This controller supports SD 6.0 Command Queuing
❑ When not using Synopsys SD/eMMC PHY, low voltage interface signaling support should be
managed externally.
■ SD Specifications Part E1 SDIO Specification Version 4.10 Sept 2014
❑ This specification defines the SD bus interface specification for SDIO and also provides register
specification. SDIO is based on the Physical Layer Specification and the SDIO specification
provides an extension and modification to the Physical Layer specification for SDIO card and
device.
■ SD Specifications Part 1 UHS-II Addendum Version 1.01, September 2013
❑ This specification describes the newly defined physical layer interface, UHS-II defined in SD 4.1
onwards.
■ AMBA 2 for AHB slave port
❑ This specification describes the AMBA specification and explains AHB.
■ AMBA 3 AXI for Master port
❑ This document describes the AMBA specification and explains AXI.
■ AMBA 2 AHB for Master port
❑ This document describes the AMBA specification and explains AHB.

1.6.1 Memory Capacities Supported by the SD Standard

The SD standard supports three capacities of memory:
■ Standard capacity SD memory Card (SDSC) (<=2GB)
■ High capacity SD memory Card (SDHC) (>2Gb, <=32GB)

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■ Extended Capacity SD Memory Card (SDXC) (>32GB, <= 2TB)

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1.7 Deliverables
DWC_mshc provides the following deliverables:
■ DWC_mshc Verilog RTL source code
■ coreConsultant tool for configuration, simulation, and synthesis
■ Test bench based on System Verilog UVM (SV-UVM)

1.8 Interoperability
The test bench packaged with the DWC_mshc is tested to work only with the Synopsys VCS simulator.

1.9 Speed and Clock Requirements

DWC_mshc requires a number of clock inputs and it is important to choose an appropriate frequency for
each clock to achieve better performance in terms of throughput and power. The bus width, bus clock and
RAM clock must be chosen to meet the required bandwidth. This section discusses the requirements of
these clocks.
For clocking requirement of SD, UHS-II, and eMMC modes, see the following sections in the DesignWare
Cores Mobile Storage Host Controller User Guide:
■ SD Mode of Operation
■ UHS-II Mode of Operation
■ eMMC Mode of Operation

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1.10 Compliance with Quality Metrics

1.10.1 Coding and Design Guidelines and Exceptions
DWC_mshc complies with the RTL coding practices specified in the Reuse Methodology Manual, Third
Edition.

1.10.2 Testing and Development Process

DWC_mshc development adhered to the following quality processes:
■ Randomized multi-configuration verification
■ Verification with an independently developed VIP as card model
■ Structured test plan with manual cross checking for coverage
■ Structured clock crossing implementation and checking
■ Self-documented clock domain crossing RTL coding style
■ Well-defined inter-module interfaces

1.11 Hardware and Software Partition

Figure 1-3 shows the hardware and software partitions for DWC_mshc.

Figure 1-3 DWC_mshc Hardware and Software Partitions

S/W Peripheral Stack

Customer software

Standard SD HCI
SD HCI Driver
Driver

System Bus Driver

Controller SP RAM

Hardware

SD/UHS-I/
eMMC UHS-II PHY
Line drivers

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2
Architecture

This chapter describes the functional details of the DWC_mshc component. It also provides an overview of
the protocols used for the SD, eMMC, and UHS-II modes of operation and discusses standards complied by
these modes of operation.
This chapter includes the following topics:
■ “Overview of Architecture” on page 30
■ “Device and Card Interface” on page 32
■ “Master Bus Interface” on page 46
■ “AHB Slave Bus Interface” on page 54
■ “Low-Speed SDR Support without PHY” on page 56
■ “JTAG Interface” on page 57
■ “DMA vs Slave Mode of Data Transfer” on page 65
■ “DMA Engine” on page 66
■ “SRAM Controller” on page 69
■ “Data Flow for Card Read in DWC_mshc” on page 71
■ “Tuning in DWC_mshc” on page 72
■ “Memory” on page 93
■ “Interrupts” on page 95
■ “Error Detection” on page 96
■ “DFT Features for Synopsys SD/eMMC PHY Production Tests” on page 98
■ “Debug User Sideband Signals” on page 101

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2.1 Overview of Architecture

This section describes the main functional building blocks of the DWC_mshc controller, represented in
Figure 2-1.

Figure 2-1 System-Level Block Diagram

AXI/AHB Master
Bus Interface Unit DMA Engine SD/UHS-I/
AXI/AHB
eMMC Unit SD/UHS-I/eMMC Interface
(TLU)

CQE

AHB Slave Bus

AHB
Interface

Host
Controller
Registers FIFO
UHS-II
Controller
MUX Unit UHS-II PHY-Link Interface
JTAG JTAG Interface (TLU)
SPRAM Interface

Mobile Storage Host Controller

Following are the various modules in the Mobile Storage Host Controller:
■ The Master Bus Interface Unit (MBIU)
This Master Bus Interface Unit (MBIU) implements the logic to transfer data on the AMBA Extensible
Interface Bus (AXI)/AMBA High-Performance (AHB) bus. The AXI/AHB interface transfers data to
and from the system memory through the AXI/AHB master bus interface, respectively.
■ The AHB Slave Bus Interface (SBI) module
The AHB slave bus interface (SBI) module implements the logic to primarily access the DWC_mshc
registers by using an external AMBA high-performance (AHB) bus. This module supports only the
little endian scheme for register accesses.
■ The JTAG Interface
The JTAG interface is used for programming MSHC registers in test mode only. In test mode, AHB
slave I/F is disabled and never used where the JTAG interface is used to access MSHC registers. It
follows indirect addressing scheme to access MSHC registers. AHB’s hclk input should be
synchronous (driven by same source) to tck when in testmode and hclk should remain active when

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accessing JTAG interface. However, MSHC’s registers are distributed across multiple clock domains,
and hence the respective clocks for these domains must be active when accessing registers.
■ DMA Engine
The DMA Engine unit handles data transfer between DWC_mshc and system memory
■ Host Controller Registers
❑ The host controller register unit comprises of the standard SD host controller registers as
specified in the SD Specifications Part A2 SD Host Controller Standard Specification Version
4.20a.It also includes Command Queuing registers compliance to JEDEC eMMC 5.1 HCI
specification.
❑ These registers are implemented in three clock domains namely, AXI master bus interface clock
(aclk, if AXI master interface is chosen in the configuration, else the AHB clk is used as the master
interface), AHB slave bus interface clock (hclk), and controller base clock (bclk). The non-transfer
related registers are implemented in the AHB slave clock domain, so that the controller base clock
can be gated for power savings.
■ SRAM Controller (Packet buffer interface)
The SRAM controller interfaces the packet buffer of the host and the transaction controller units (SD
and UHS-II).
■ SD/UHS-I/eMMC Unit
SD/UHS-I/eMMC unit manages the SD/eMMC interface protocols
■ UHS-II Unit
UHS-II unit consists of the following sub-units:
❑ UHS-II Transaction Controller Unit
❑ UHS-II Link Controller Unit
For more information, see “UHS-II Card Interface” on page 33.
■ Command Queuing Engine (CQE)
This module implements command queuing and includes the following:
❑ Task scheduler with the ability to prioritize execution of tasks
❑ Control logic for descriptor fetch
❑ Control and sequence task submission and execution
❑ Status polling
❑ Timers and counter dedicated for CQE operation
■ Interrupt coalescing logic

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2.2 Device and Card Interface

2.2.1 Overview of the Device and Card Interface
On the Physical layer/Link interface, DWC_mshc is compliant with the SD Specifications Part-1, Physical
Layer Specification. Therefore, all interface protocol and timings towards the PHY/Link interface are
compatible to that defined in the above standard.
■ For specifics of timing for SD/UHS-I/UHS-II interfaces, refer to appropriate sections in Chapter 4
and Chapter 6 in the SD Specifications Part-1, Physical Layer Specification.
■ For information specific to timing on an eMMC interface, refer to Section “Timing Values” in
UserGuide.

2.2.2 Configuring the Device and Card Interface

You can configure the required device or card interface from the Card Interface Type drop-down list from
the Basic Configuration tab in the coreConsultant user interface.

2.2.3 SD/UHS-II Register Optimization

DWC_mshc implements all the registers defined by the SD Host Controller Specification that defines
registers for SD, SDIO and UHS-II modes. Some of these registers are reused in the eMMC mode.
Additionally, DWC_mshc implements registers defined in the Host Controller Interface for Command
Queuing section of the eMMC Specification and also implements certain vendor-specific registers.
As per the standard, DWC_mshc can be connected to either an SD or UHS-II card and therefore, both SD
and UHS-II registers must exist in the controller. However, DWC_mshc may not support both SD and
UHSII interfaces at the same time based on the selected Card Interface Type.
If you choose an interface type, such as SD from the drop-down options, UHS-II registers need not exist in
the controller. This is called register optimization.
Following are the use cases for the selections:
■ When selected Card Interface Type is only "SD” or "SD + eMMC", “eMMC”, all UHS-II registers are
removed.
■ When selected Card Interface Type is only "UHS-II”, all SD registers are removed.
By default, none of these use cases are enabled. You can enable this option only when the Card Interface
Type is selected as "SD”, "UHS-II”, "SD+eMMC", or “eMMC”. In other configurations, all the SDHCI
registers exist in the controller.

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2.2.4 SD Card Interface

2.2.4.1 Overview of the SD Card Interface

SD unit is responsible for managing SD interface protocols.
The key features of this unit are to:
■ Generate DS/High-speed/UHS-I command and data packets
■ Generate CRC and check for command and data packets
■ Handle packet timeouts
■ Support 1-bit DAT and 4-bit DAT modes
■ Handle SDIO card interrupt
■ Supports Default Speed (DS), High-Speed (HS), SDR12, SDR25, SDR50 and SDR104 speed modes

2.2.4.2 Signals Related to the SD Card Interface

For more information, refer to Signal Descriptions chapter.

2.2.4.3 Registers Related to the SD Card Interface

For more information, refer to Register Descriptions chapter.

2.2.5 UHS-II Card Interface

2.2.5.1 Overview of UHS-II Card Interface

The UHS-II unit consists of the following sub-units:
■ UHS-II Transaction Controller Unit
The UHS-II transaction controller unit is responsible for the transaction layer protocol (CM-
TRAN and SD- TRAN) as specified in the UHS-II Addendum Version 1.01 specification.
The key features of this unit are as follows:
❑ Generate and process UHS-II/SD common packets
❑ Configuration mechanism
❑ Transaction management supporting multiple device connections
This unit generates all the UHS-II packets (except MSG packets) and sends them to the
transmitter side and analyzes received packets in the receiver side.
The UHS-II transaction controller unit implements the following state machines as specified in
the UHS-II Addendum version 1.01 specifications:
❑ Transaction Scheduling State Machine (TSSM)
❑ Transaction Buffer Management State Machine (TBSM)
❑ Transaction Processing State Machine (TPSM)
■ UHS-II Link Controller Unit

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UHS-II link controller unit is responsible for the link layer protocol as specified in the UHS-II
Addendum Version 1.01 specification. The key features of this unit are as follows.
❑ PHY Initialization
❑ Data Integrity
■ Packet framing with Start of Packet (SOP) and End of Packet (EOP)
■ Burst Framing with Start of Data Burst (SDB) and End of Data Burst (EDB)
■ CRC generation and checking
❑ Flow Control
■ Fixed window flow control for only data packet transfers
■ MSG packet generation and checking
❑ Power Management
■ Lane level power saving state (Electrical Idle (EIDL))
UHS-II link controller unit implements the following state machines as specified in the UHS-II
Addendum version 1.01 specifications:
❑ Data Link State Machine (DLSM)
❑ Physical Lane State Machine (PLSM)

2.2.5.2 Signals Related to the UHS-II Card Interface

■ pclk
■ presetn
■ uhs2_rdm
■ uhs2_rd
■ uhs2_rdtm
■ uhs2_rdt
■ uhs2_st
■ uhs2_mode
■ uhs2_ct
■ uhs2_tdm
■ uhs2_td
■ uhs2_tdrm
■ uhs2_tdr
For more information, refer to Signal Descriptions chapter.

2.2.5.3 Registers Related to the UHS-II Card Interface

For more information, refer to Register Descriptions chapter.

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2.2.6 eMMC Card Interface

2.2.6.1 Overview of eMMC Card Interface

eMMC unit is responsible for managing eMMC interface protocols.
The key features of this unit are to:
■ Generate eMMC bus command and data packets
■ Generate CRC and check for command and data packets
■ Handle packet timeouts
■ Support 1-bit DAT, 4-bit DAT, and 8-bit DAT modes
■ Support legacy, High Speed SDR, High Speed DDR, HS200, and HS400- modes

2.2.6.2 Signals Related to the eMMC Card Interface

For more information, refer to Signal Descriptions chapter.

2.2.6.3 Registers Related to the eMMC Card Interface

For more information, refer to Register Descriptions chapter.

2.2.6.4 Programming the eMMC Card Interface Setup

See the following Host Controller Setup Sequence for eMMC Device and Card Interface Setup Sequence for eMMC
Card sections in the Programming DWC_mshc chapter of the DesignWare Cores Mobile Storage Host Controller
User Guide.

2.2.7 Output Data Path

illustrates the DWC_mshc output data path structure for SD and eMMC modes.

2.2.7.1 Output Data Path in SD/eMMC Mode (DWC_MSHC_LS_NO_PHY_MODE = 0)

In SD and eMMC modes, the data bus width can be of 4-bit or 8-bit width. Based on the speed mode, the
output data can be valid on both edges of the clock. To support dual-data rate, the final output data is
combinatorially muxed in the DWC_mshc_ddr_mux_2x1 module.
When the DDR mode is enabled (using UHS_MODE_SEL in HOST_CTRL2 register), sd_dat_out are
combinatorially multiplex-ed and changes on both the edges. It is being control by ddr_mux_sel. However,
a half clock margin is maintained between the last stage data register and corresponding multiplex control.
This ensures that data is stable half cycle ahead before the multiplex control changes.The data valid window
for output DDR data is determined by the pulse width of "ddr_mux_sel" signal. It is highly recommended to
closely maintain the pulse width for level '0' and '1' of "ddr_mux_sel" signal.
Refer “The DWC_mshc_ddr_mux_sel Module” on page 607 for more details on the generation of
"ddr_mux_sel" signal.

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Figure 2-2 DWC_mshc Output Data Path Structure for SD and eMMC Modes

ddr_mode_en

data_shift_reg[7:0]
0
data_reg_p
data_shift_reg[15:8] 1
DWC_mshc_ddr_mux_2x1
0
sd_dat_out
data_shift_reg[7:0] data_reg_n
1
Device
SDCLK
cclk_tx
ddr_mux_sel

.
EN
cclk_tx

cresetn

EN

DWC_mshc_ddr_mux_sel

ddr_mode_en

■ A minimum pulse width synthesis constrain is applied on "ddr_mux_sel". The following is

Note the SDC sample:
create_generated_clock -name ddr_mux_sel_clk -divide_by 1 -
source cclk_tx -master_clock cclk_tx
U_DWC_mshc_sd4/U_DWC_mshc_sd4_data_tx/U_DWC_mshc_ddr_mux_sel/ddr_
mux_sel
set_min_pulse_width -low <cclk_tx_period * 0.48> ddr_mux_sel_clk
set_min_pulse_width -high <cclk_tx_period * 0.48> ddr_mux_sel_clk

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2.2.7.2 Output Data Path for HS400 with Data Output on Negedge
(DWC_MSHC_NEG_DATA_HS400_MODE = 1)
DWC_mshc has the option to send data out on negative edge of the TX clock(cclk_tx) in case of HS400 mode
of operation. Configure this option by setting DWC_MSHC_NEG_DATA_HS400_MODE = 1.
Set the MSHC_CTRL_R[NEGEDGE_DATAOUT_EN bit to enable this on the system.
Enable this option where the timing window is minimal because of the delays on board. The eMMC device
input timing for the lines CMD and DAT are different in case of HS400.
The device input timings for lines CMD is HS200, and lines DAT is HS400. Because of this difference, even a
minor delay in the system can cause timing issues. To ease the timing, the sd_dat_out from the controller is
sent on negedge keeping sd_cmd_out on posedge.

Figure 2-3 Enhanced HS400 Input Device Timing

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Figure 2-4 Output Datapath for HS400 Negedge Data Enhancement

■ Apply the following constraint on ddr_mux_sel signal with respect to inverted cclk_tx.
Note
create_generated_clock -name ddr_mux_sel_clk -divide_by 1 source
cclk_tx_inv -master_clock cclk_tx_inv
U_DWC_mshc_sd4/U_DWC_mshc_sd4_data_tx/U_DWC_mshc_ddr_mux_sel/ddr_
mux_sel set_min_pulse_width -low <cclk_tx_period * 0.48>
ddr_mux_sel_clk set_min_pulse_width -high <cclk_tx_period * 0.48>
ddr_mux_sel_clk
■ Even though the data sent out from the controller is on the Negative edge of cclk_tx, the
expectation of the device will not change. It will still sample the data on the positive edge of
SDCLK.

To meet the hold time of the device and to ensure that data is sampled in the middle of the data window for
DDR data, SDCLK can be phase delayed with respect to cclk_tx as shown in Figure 2-5.

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Figure 2-5 SDCLK Phase Delayed With Respect to cclk_tx

cclk_tx

data_reg_n 00 OD0 OD1 OD2

data_reg_p 00 ED0 ED1 ED2

ddr_mux_sel

sd_dat_out_en

sd_dat_out 00 OD0 ED0 OD1 ED1 OD2 ED2

SDCLK
Phase
delay

2.2.7.3 Output Data Path in Low-Speed SDR No PHY Mode

The output path for CMD/DAT undergoes changes when DWC_MSHC_LS_NO_PHY_MODE = 1. By
default, for SDR mode, the startbit and subsequent data/cmd are clocked out with respect to negative edge
of cclk_tx while the core logic still works on positive edge of cclk_tx. This ensures that device input setup
and hold time are met with respect to rising edge of SDCLK without any external need to delay the phase of
SDCLK. This applies for SDR data and CMD line. However, a programmable option MSHC_CTRL_R.
PEDGE_DRV_EN register bit is provided to clock out the startbit and subsequent data/cmd with respect to
positive edge of cclk_tx.

Figure 2-6 DWC_mshc Ouput Data Path Structure when in Low Speed SDR No PHY mode

data_shift_reg data_reg_p sd_dat_out

cclk_tx_inv
0 drv_cclk_tx
cclk_tx Device
1 SDCLK

s2tx_l_drv_posedge

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Figure 2-7 Posedge Driven DAT/CMD Line

cclk_tx

s2tx_l_drv_posedge

sd_dat_out_en
sd_dat_out
00 ED0 ED1 ED2

SDCLK

Tcg+To+Tl

Figure 2-8 Negedge Driven DAT/CMD Line

cclk_tx

s2tx_l_drv_posedge

sd_dat_out_en

sd_dat_out
00 OD0 OD1 OD2

SDCLK Tcg+To+Tl

When data/cmd are clocked with respect to negative edge of cclk_tx, there exists a half cycle path from
positive edge of cclk_tx to driving negative edge cclk_tx for the following destination registers
■ U_DWC_mshc_sd4.U_DWC_mshc_sd4_cmd.ccmd_out
■ U_DWC_mshc_sd4.U_DWC_mshc_sd4_cmd.ccmd_out_en
■ U_DWC_mshc_sd4.U_DWC_mshc_sd4_data_tx.data_reg_p
■ U_DWC_mshc_sd4.U_DWC_mshc_sd4_data_tx. cdat_out_en

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2.2.8 Input Data

2.2.8.1 Input Data/CMD Path in SD/eMMC mode (DWC_MSHC_LS_NO_PHY_MODE = 0)

In SD and eMMC modes, the data bus width can be of 4-bit or 8-bit width. The incoming "sd_dat_in" is
sampled using two sets of pipe registers, one at the rising edge and another at the falling edge of
"cclk_rx_ds_mux" to support dual data rate before pushing into the asynchronous data FIFO.
"cclk_rx_ds_mux" is the multiplex output between "cclk_rx" and "sd_dat_stb" based on the speed mode of
operation. The "sd_dat_stb" is available when the controller is configured to support eMMC Data Strobe.
Auto-tuning, when enabled, also monitors and samples the incoming "sd_dat_in" using "drift_cclk_rx"
The command line "sd_cmd_in" is also sampled using a pipe register before pushing into the asynchronous
command FIFO.
It is a must to balance clock and data path of all the sampling registers for incoming "sd_dat_in" and
"sd_cmd_in" to ensure accurate results while in operation.
The overall timing effort for data path skew balancing is eased since skew balancing is only applied to
reduced number of flops. Table 2-1 lists the path to be balanced.

Table 2-1 Data Path Skew Balancing

Path Hierarchy Path Endpoint Comments

U_DWC_mshc_tune.DWC_mshc_tune GEN_FST2.sample_meta[0] Where <n> varies from 0 to 7 when

_auto.DWC_mshc_tune_auto_dm.U_D SD_DAT_WIDTH is configured for 8
WC_mshc_tune_auto_dd.gen_drift_det bits; It <n> varies from 0 to 3 when
ect_<n>_.U_DWC_mshc_bcm21_drift_ SD_DAT_WIDTH is configured for 4
detect_sync bits.
Note: Auto tuning path is available only
when Mode3 Retuning-mode is selected in
coreConsultant GUI.

U_DWC_mshc_sd4.U_DWC_mshc_sd cdat_in_pe_pipe_r_reg[n] Where n varies from 0 to 7 when

4_sync.U_DWC_mshc_sd4_sample. SD_DAT_WIDTH is configured for 8
bits; It <n> varies from 0 to 3 when
U_DWC_mshc_sd4.U_DWC_mshc_sd cdat_in_ne_pipe_r_reg[n]
SD_DAT_WIDTH is configured for 4
4_sync.U_DWC_mshc_sd4_sample.
bits.

U_DWC_mshc_sd4.U_DWC_mshc_sd ccmd_in_pipe_r_reg
4_sync.U_DWC_mshc_sd4_sample.

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Figure 2-9 SD/eMMC Input Data Path

Controller

GEN_FST2.sample_meta[0]

U_Dwc_mshc_bcm21_drift_detect_sync drift_cclk_rx
gen_drift_detect_
U_Dwc_mshc_tune_auto_dd
U_Dwc_mshc_tune_auto_dm

U_Dwc_mshc_tune_auto

U_Dwc_mshc_tune

cdat_in_ne_pipe_r
Negedge Sampling Path

mem_a Combo
rray

cdat_in_pe_pipe_r
U_RAM

U_DWC_msh c_2clkfifo_pipe_data
Posedge Sampling Path
sd_dat_in
cclk_rx_ds_mux

0
cclk_rx

ccmd_in_pipe_r 1
sd_dat_stb

datastrobe_en

0
mem_a Combo
rray 1
U_RAM
enh_strobe_en
U_DWC_msh c_2clkfifo_cmd_sample

U_DWC_mshc_sd4_sample sd_cmd_in

U_DWC_mshc_sd4_sync
U_DWC_mshc_sd4

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■ "Ths dc.tcl script includes a command (set_clock_gating_check and

Note set_disable_clock_gating_check). The set_clock_gating_check command provides the
ability to check setup or hold margins for control inputs of clock-gating cells. These checks
ensure that the clock-gating signal stabilizes for the entire period of time when the gated
clock input has a non-controlling value. The dc.tcl is available in
<workspace>/syn/auxScripts and is sourced during synthesis.
■ "By default, clock gating check is done on the clock multiplex control the selects between
"cclk_rx" and "sd_dat_stb" when Synthesis is perform using coreConsultant flow. The clock
gating check is disable for "in1_clk" i.e "sd_dat_stb" since by design and protocol
specification "sd_dat_stb" is expected to be inactive while clock multiplex control changes.
The sample of SDC constrain is shown below and shall explicitly include these checks for
synthesis using any other flow if DWC_MSHC_DATASTROBE_EN=1
set_clock_gating_check -high
U_DWC_mshc_sd4/U_DWC_mshc_sd4_sync/U_DWC_mshc_sd4_sample/U_scan_c
lk_mux_2x1_cclk_rx_ds_mux_gen/clk_sel
set_clock_gating_check -high
U_DWC_mshc_sd4/U_DWC_mshc_sd4_sync/U_DWC_mshc_sd4_sample/U_scan_c
lk_mux_2x1_cclk_rx_ds_enh_mux_gen/clk_sel
set_disable_clock_gating_check
U_DWC_mshc_sd4/U_DWC_mshc_sd4_sync/U_DWC_mshc_sd4_sample/U_scan_c
lk_mux_2x1_cclk_rx_ds_mux_gen/in1_clk
set_disable_clock_gating_check
U_DWC_mshc_sd4/U_DWC_mshc_sd4_sync/U_DWC_mshc_sd4_sample/U_scan_c
lk_mux_2x1_cclk_rx_ds_enh_mux_gen/in1_clk

2.2.8.2 Input Data/CMD Path in Low Speed SDR No PHY Mode

When DWC_MSHC_LS_NO_PHY_MODE = 1, there is an additional programmable support bit to
internally select the sampling edge. Based on MSHC_CTRL_R. NEDGE_SMPL_EN bit, either the positive or
negative edge can be used to sample the DAT/CMD line into the pipe register. As shown in figure
Figure 2-9, there exists a half cycle path from ccmd_in_pipe_r register to CMD sampling FIFO while the
half cycle path from cdat_in_ne_p register to Data sampling FIFO can be ignored since DDR is not
supported. However, it is the responsibility of software driver to appropriately select the sampling edge for
positive results. It is recommended to use negative edge sampling only when the total output delay is
greater that (t_clockperiod - t_setup - t_diff) and limited to (1.5*t_clockperiod - t_setup - t_diff), where t_diff
is the phase difference between cclk_rx and SDCLK.

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Figure 2-10 Low Speed SDR Input Data Path

Controller

GEN_FST2.sample_meta[0]

Auto Tuning Path

U_Dwc_mshc_bcm21_drift_detect_sync drift_cclk_rx
gen_drift_detect_
U_Dwc_mshc_tune_auto_dd
U_Dwc_mshc_tune_auto_dm

U_Dwc_mshc_tune_auto

U_Dwc_mshc_tune

cdat_in_ne_pipe_r
Negedge Sampling Path

mem_a Combo
rray

cdat_in_pe_pipe_r
U_RAM

U_DWC_mshc_2clkfifo_pipe_data
Posedge Sampling Path
sd_dat_in
cclk_rx_ds_mux

cclk_rx_inv cclk_rx
ccmd_in_pipe_r

s2rx_l_smpl_negedge

mem_a Combo
rray

U_RAM

U_DWC_mshc_2clkfifo_cmd_sample

U_DWC_mshc_sd4_sample sd_cmd_in

U_DWC_mshc_sd4_sync

U_DWC_mshc_sd4

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Note The half cycle path from “cdat_in_ne_pipe_r” register to Data sampling FIFO can be ignored
if DWC_MSHC_LS_NO_PHY_MODE = 1

Figure 2-11 Positive edge Sampling

cclk_tx .

Tcg+To+Tl
SDCLK .

t_diff = Tl-Ti
cclk_rx .

Tcg+To+Ti
DAT/CMD

Total Delay = ToDly Sampling wrt +ve edge

+ Tl + Ti when total delay <
(t_clockperiod – t_setup –
t_diff)

Figure 2-12 Negative edge Sampling

cclk_tx .

Tcg+To+Tl
SDCLK .

t_diff = Tl-Ti
cclk_rx .

Tcg+To+Ti
DAT/CMD

Total Delay = ToDly

+ Tl + Ti Sampling wrt -ve edge when
total delay > (t_clockperiod
– t_setup – t_diff)

■ Tcg: Clock Gating delay

Note
■ To: Output Pad delay
■ Ti: Input Pad delay
■ Tl: External line delay
■ ToDly: Output delay time during data transfer inside card/device

For more information, on the timing values refer to section “Low Speed Mode” in DesignWare Cores
DWC_mshc User Guide.

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2.3 Master Bus Interface

2.3.1 Overview of the Master Bus Interface
All card interface types supported in DWC_mshc support the AMBA 3 AXI/AMBA 2 AHB protocol. You
can use the coreConsultant tool to configure the protocol type and also additional AXI/AHB settings, such
as address width, data bus width, AXI ID width, and AXI/AHB maximum burst length.
SoC designer can choose to either clock MBIU using an independent clock domain aclk which is
asynchronous with other clocks or use "clock modes" feature to merge MBIU clock with other clock
domains.
The AXI/AHB master interface unit supports a 32-bit and 64-bit data bus width.
DWC_mshc utilizes the Master Bus Interface Unit (MBIU) to initiate data traffic with the system memory.
The system memory Read/Write transfer requests are initiated by the DMA of DWC_mshc through a
Native Master Interface, which is the Generic Master (GM) interface. Irrespective of the selected system bus
protocol, the GM interface is used to interact between the DMA and the MBIU. DMA transfers utilize the
read descriptors to transfer (WRITE/READ) data from system memory.

2.3.2 Configuring the Master Bus Interface

DWC_mshc has a configurable master interface and uses the DWC_MSHC_MST_INTERFACE_TYPE
parameter to indicate the type of the master interface. You can configure the master interface as an AHB or
AXI interface. The AHB and AXI interfaces utilize interface gaskets to convert information from the GM
interface to AHB/AXI as shown in Figure 2-13.

Figure 2-13 Master Bus Interfaces

AHB Configuration AXI Configuration

DWC_mshc DWC_mshc

DMA DMA

GM GM
Interface Interface

AHB MBIU AXI MBIU

AHB AXI
Interface Interface

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The GM interface operates on a packet- or descriptor-level transfer. That is, each request represents a
descriptor or packet size transfer. In contrast, the AHB and AXI gaskets break the GM request into multiple
AHB/AXI transfers as appropriate for the interface. For example, the AHB gasket splits a 512 byte GM read
request into multiple INCR8/INCR4 bursts depending on the burst settings.
Wait cycles may appear on the master read or write data path. This happens if the RAM controller does not
have enough bandwidth to serve both the Transaction Layer Unit (TLU) and the DMA. It can also occur
during CQE as the DMA FIFOs are also utilized for message passing.

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2.3.3 AXI Master Interface

2.3.3.1 Overview of the AXI Master Interface

The AXI Master Interface is a gasket between the Native Master Interface (GM) and the AXI bus. DMA read
and write accesses are initiated by the DWC_mshc controller through the AXI master interface to read
Descriptors, and read/write transfer data. The read and write channels are independent and can be active
simultaneously. However, if a read access is dependent on a write access completing first, the controller
does not issue the DMA read until it receives the DMA write response from AXI.
In DWC_mshc, the DMA controller interfaces with the application through the AMBA 3 AXI interface. The
AMBA 3 AXI bus interface provides the characteristics to support highly-effective data traffic throughput.
The AXI master interface allows multiple burst requests to be queued for Read or Write operation.

2.3.3.2 AXI Memory Read

Figure 2-14 shows the AXI master read timings. Read requests with ID 0 are placed on the Read address
channel. A maximum of eight outstanding read requests can be put as shown in Figure 2-14. These requests
are of burst length 16. The Read data is received by the AXI master. The DMA in AXI master always ensures
that it has enough space in its FIFO to accept the requested burst of data.

Note Unaligned addresses are supported for data transfer.

Figure 2-14 AXI Memory Read Timings

2.3.3.3 AXI Memory Write

Figure 2-15 shows the AXI write interface diagram. There are four requests for ID 0. These requests are
issued with burst lengths of 16. The DMA ensures that it always has the requested burst of data available in
its FIFO before the request is generated. Therefore, there are no further latencies or delays in the data
transfer. If there is no delay in the acceptance of data by AXI slave, complete 64 beats of write data of the

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four requests can be transferred in 64 clocks. AXI write shown in Figure 2-15 is slowed down because of
lower acceptance rate of AXI slave (wready is low for longer duration).

Figure 2-15 AXI Memory Write Timings

Note Unaligned addresses are supported for data transfer.

2.3.3.4 Burst Splitting and Burst Selection

The AXI master of DWC_mshc splits the DMA requests into multiple bursts on the AXI system bus.
Splitting is based on the DMA transfer count and burst type. Burst type is always chosen as INCR. DMA
transfer count is decided by block size and block count. The AXI master also handles splitting the transfers
that cross 4 KB address boundary.

2.3.3.5 INCR Burst Type

The AXI master in DWC_mshc supports burst type of INCR. The AXI master chooses a burst length of any
value less than 16, which is the maximum burst length.

2.3.3.6 Outstanding Transactions

The AXI master supports up to eight outstanding Read or Write requests on the AXI bus by default. This
means the controller generates new requests even if it has reached one block boundary, irrespective of the
status of earlier outstanding transactions. This feature is effective when the data descriptor sizes are bigger
than the block size and when there are multiple requests for the same data descriptor.
Figure 2-16 shows the behavior of AXI when it is configured to support 8 Write Outstanding requests.

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Figure 2-16 AXI Write Outstanding Transfers

ACLK
OSR CNT 0 1 2 3 4 5 6 7 8 7 8

AWVALID
AWREADY

BRESP 0

BVALID
BREADY

In Figure 2-16:
■ OSR_CNT, gives the number of Outstanding Requests of the AXI.
■ On receiving AWVALID and AWREADY the Outstanding request gets incremented.
■ When the OSR_CNT value reaches eight, it waits for at the least one transfer to get completed
indicated by a valid OKAY Response.
■ This decrements the OSR_CNT to 7, which in turn causes the issue of the next pending transfer.
■ After a valid transfer is sent, the OSR_CNT value again increments to 8.
Figure 2-17 shows the behavior of AXI when it is configured to support 8 Read Outstanding requests.

Figure 2-17 AXI Read Outstanding Transfers

ACLK
OSR CNT 0 1 2 3 4 5 6 7 8 7 8

ARVALID
ARREADY

RLAST
RVALID
RREADY

In Figure 2-17:
■ OSR_CNT, gives the number of Outstanding Requests of the AXI.
■ On receiving ARVALID and ARREADY the Outstanding request will get incremented.
■ When the OSR_CNT value reaches eight, it waits for at the least one transfer to get completed.
■ This decrements the OSR_CNT to seven, which in turn causes the issue of the next pending transfer.
■ After a valid transfer is sent, the OSR_CNT value again increments to eight.
This behavior ensures that there are always transactions on the AXI bus as long as data is present to be
written/read into/from the system memory.

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2.3.3.7 Bursts Reordering and Data Interleaving

The AXI protocol allows reordering of data transfers with different AXI IDs with respect to the sequence of
requests. In DWC_mshc configurations with Command Queuing Engine (CQE) enabled, the requests from
DMA (Descriptor fetch and Data fetch) are generated with a different AXI ID. Therefore, reordering and
data interleaving can be performed as descriptor and data fetch operate independently, and are allocated
different address space on the slave memory.

2.3.3.8 AXI ID Translation

The DWC_mshc-AXI selects unique IDs for reading descriptor and data on the read channel when CQE
feature is enabled. The DWC_mshc-AXI selects the IDs as follows when CQE is enabled:
■ AXI Read Channel ID usage
❑ For CQE Task descriptor fetches, AXI ID = 1
❑ For remaining types of AXI Transfers, AXI ID = 0
■ AXI Write Channel ID usage
❑ AXI Write ID = 0

2.3.3.9 Endianness Support

The AXI master supports the little-endian mode on the AXI master ports. The AXI master does not support
narrow transfers and always performs full data-width transfers. For example, burst size is always fixed to 4
when AXI data bus width is configured to 32.

2.3.3.10 Error Response Handling

Whenever there is an error response from the AXI slave, ADMA error is generated. For more information on
the ADMA error, see Error Interrupt Status register for SD/eMMC mode and UHS-II Error Interrupt Status
register for UHS-II mode. The application can re-initialize that specific DMA and restart the operation after
recovering from the error. For more information on error handling, see the Error Recovery section in
Programming chapter of the DesignWare Cores Mobile Storage Host Controller User Guide.

2.3.4 AHB Master Interface

2.3.4.1 Overview of the AHB Master Interface

The AHB master interface is designed to integrate with the AHB Master Bus Interface unit that is compliant
with the AMBA 2.0 Specification. The AHB master interface translates Read/Write transfers initiated by the
DMA/CQE (using a generic master interface) into AHB-compliant transfers on the system bus.
The AHB master interface supports the following features:
■ 32-bit or 64-bit data bus
■ 32-bit addressing
■ Configurable and selectable burst types
■ Inserts busy cycles when the Master is not ready with data
■ Configurable and programmable selection/deselection of burst types
■ SPLIT and RETRY operations

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2.3.4.2 AHB Memory Read

Figure 2-18 shows the 64-bit descriptor read staring at an aligned host memory location.

Figure 2-18 AHB Memory Read Timings

2.3.4.3 AHB Memory Write

Figure 2-19 shows the write data transfer starting at an unaligned address with insertion of busy cycles.

Figure 2-19 AHB Memory Write Timings

2.3.4.4 Configurable and Selectable Burst Types

DWC_mshc AMBA AHB interface supports following burst types:
■ Single
■ INCR4
■ INCR8
■ INCR16
■ INCR (undefined length)
The default configuration of the controller selects all the burst types. Therefore, MBIU can choose to
generate the burst that it prefers. When INCR (undefined length) is enabled, the controller chooses this to
execute the complete request. This default behavior can be changed by using the following methods:

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■ By configuration: using DWC_MSHC_MBIU_BURST* configuration parameters

■ By programming: using MBIU_CTRL_R register
Following examples illustrate these behaviors.

Example 1
Consider using the starting address = 0, DMA transfer size = 512 bytes, AHB bus data width = 32 bits, burst
sizes INC4, INC8, and INC16 enabled, and INCR is Disabled.
The DMA transfers will be Address-0 BURST-16, Address-64 BURST-16,Address-128 BURST-16, Address-
192 BURST-16, Address-256 BURST-16, Address-320 BURST-16, Address-384 BURST-16, Address-448
BURST-16.

Example 2
Consider using the starting address = 0, DMA transfer size = 508 bytes, AHB bus data width = 32 bits, burst
sizes INC4, INC8, and INC16 enabled, and INCR is Disabled.
The DMA transfers will be Address-0 BURST-16, Address-64 BURST-16,Address-128 BURST-16,Address-
192 BURST-16,Address-256 BURST-16,Address-320 BURST-16,Address-384 BURST-16,Address-448 INCR
(15 beats).

Example 3
Consider using the starting address = 0, DMA transfer size = 508 bytes, AHB bus data width = 32 bits, burst
sizes INC4, INC8, are enabled. INC16 and INCR is Disabled.
The DMA transfers will be. Address-0 BURST-8, Address-32 BURST-8, Address-64 BURST-8, Address-96
BURST-8, Address-128 BURST-8, Address-160 BURST-8, Address-192 BURST-8, Address-224 BURST-8,
Address-256 BURST-8, Address-288 BURST-8, Address-320 BURST-8, Address-352 BURST-8,
Address-384 BURST-8, Address-416 BURST-8, Address-448 BURST-8, Address-480 INCR (7 beats)
Do note the exceptions specified here for Undefined length INCR as detailed in example2 and example3.
Because even when INCR (undefined-length) is disabled, MBIU can still decide to use INCR after a few
transfers if the remaining bytes cannot be completed using a single transfer of any of the enabled burst
types.
Consider example2 where 508 bytes has to be read, after completing 7 INCR16 transfers the module is left
with reading 60 more bytes. These cannot be completed using a single transfer of any of the enabled burst
types so it falls back to using INCR.

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2.4 AHB Slave Bus Interface

2.4.1 Overview of the AHB Slave Bus Interface
The Slave Bus Interface unit supports a 32-bit data bus width. The transfer size can be less than the data bus
width. Additionally, for low bandwidth applications, the Slave Bus Interface can be used as an alternative to
the Master Bus Interface to transfer data into and out of DWC_mshc registers. In such cases, certain
configuration options of DWC_mshc can be used to obtain better area and power efficiency. For more
information about these options, see “Slave-Only Mode of Data Transfer” on page 65.

2.4.2 Description of AHB Slave Bus Interface

The AHB slave interface supports the following features:
■ Fully compliant with AMBA 2.0 AHB slave
■ Single burst transfer
■ 32-bit, 16-bit, and 8-bit write or read transfers to DWC_mshc registers
■ Transfer response:
❑ OKAY, ERROR, and RETRY responses

2.4.2.1 Register Write

Figure 2-20 shows write access for three registers on the AHB slave port. The waveform is as per the AMBA
2.0 specification. The transfer size can be 8 bits, 16 bits or 32 bits. Data from appropriates byte lane is written
into the register based on address (haddr) and size of transfer (hsize). For example, for register write at
address 0x3e and transfer size of 16 bits, data in upper two bytes that is, d000 is written. While writing to
register at 0x00, hready_resp is de-asserted for some time and it is asserted again when this register is
written successfully.

Figure 2-20 Register Write Access on the AHB Slave Port

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2.4.2.2 Register Read

Figure 2-21 shows read access for three registers on the AHB slave port. These are same three registers
which were written in Figure 2-21.

Figure 2-21 Register Read Access on the AHB Slave Port

AMBA bus wider than 32-bit can be interfaced with 32-bit AHB slave port of DWC_mshc.
Note Extra logic described in Section 3-15 of AMBA 2.0 Specification is required to interface a wider
bus.

2.4.3 Configuring AHB Slave Bus Interface

The SBI can be configured to operate on an independent clock domain hclk, which is asynchronous with
other clocks or use "clock modes" feature to merge SBI clock with other clock domains.
The SBI can be also configured to provide 2-cycles AHB slave error response for non-existent register word
access.
Accesses to AHB slave when JTAG I/F is selected (DWC_MSHC_JTAGIF_EN =1) results in AHB response
error.

Note This controller does not support back to back write followed by read to the same address. You
can insert and dummy read to break the back-to-back operations as a workaround.

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2.5 Low-Speed SDR Support without PHY

2.5.1 Overview of Low-Speed SDR Support without PHY
Low-speed SDR support without PHY is intended only for SDR operation up-to 100Mhz. Because phase of
sampling clock cclk_rx cannot be altered, it does not support tuning operation. cclk_rx is the loopback
clock closely phase aligned with clock to the card/device. Table 2-2 and Table 2-3 show the device speed
mode and frequency of operation supported when parameter DWC_MSHC_LS_NO_PHY_MODE is set.

Table 2-2 eMMC

Speed mode Frequency of operation

Legacy 26 Mhz

High-speed SDR 52 Mhz

Table 2-3 SD+UHS1/SDIO

Speed mode Frequency of operation

Default 25 MHz

High Speed 50 MHz

SDR12 25 MHz

SDR25 50 MHz

SDR50 100 MHz

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2.6 JTAG Interface

2.6.1 Overview of JTAG Interface
The JTAG interface is used for programming DWC_mshc registers in test mode only. In test mode, AHB
slave interface is disabled and never used where the JTAG interface is used to access the registers. It follows
indirect addressing scheme to access the registers. AHB’s hclk input should be synchronous (driven by
same source) to tck when in testmode and hclk should remain active when accessing JTAG interface.
However, the registers are distributed across multiple clock domains, and hence the respective clocks for
these domains must be active when accessing registers. Table 2-4 shows the IR code to access DWC_mshc
register.

Table 2-4 IR Code

Instruction IR CODE DR width Description

TAP_BYPASS 0xF 1 TAP is in Bypass, tdo is connected to tdi using a single flop.

SEL_RACDR 0x3 50 TAP selects RACDR data register, MSHC’s registers can be
accessed using this register.

RESERVED All others 1 Reserved instructions, when undefined are mapped to select
Bypass Register

2.6.2 JTAG Registers

The JTAG tap controller in DWC_mshc does not have direct access to DWC_mshc registers, instead it uses
indirect addressing scheme to write and read data from DWC_mshc registers. Following are the only
registers that the JTAG Interface has access to.
1. IR (TAP Instruction Register)
2. RACDR (TAP Data Register)
3. BR (TAP Bypass Register)

2.6.2.1 IR – TAP Instruction register

■ Name: Instruction register
■ Description: is used to hold the JTAG instruction to the tap
■ Size: 4 bits

3:0

JTAGINST

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Table 2-5 Fields for Register: IR

Memory
Bits Name Access Description

3:0 JTAGINST R/W Value programmed here is decoded to either select DR or put IP in bypass
■ 0xF – Selects Bypass register
■ 0x3 – Selects RACDR (Data register)
■ Others – reserved, these are mapped to Bypass register
Value After Reset: 0xF

2.6.2.2 RACDR – Data register

■ Name: Register Access Data register
■ Description: Holds the MSHC register access instruction or the read back data
■ Size: 50 bits

49 48 47:46 45:34 33:32 31:0

WRn STATUS INTR [1:0] REGADDR REGSIZE [1:0] REGDATA [31:0]

[11:0]

Table 2-6 Fields for Register: RACDR

Memory
Bits Name Access Description

49 WRn RW Specifies if the MSHC register access Type is Write or Read

0x0 – Read access
0x1- Write access
Value After Reset: 0x0

48 STATUS R Specifies if the Status of previous Register Read/Write access. Similar to

AHB’s response HRESP
0x0 – Previous Register access is Okay
0x1- Previous Register access failed
Value After Reset: 0x0

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Table 2-6 Fields for Register: RACDR

Memory
Bits Name Access Description

47:46 INTR [1:0] R Critical interrupts of MSHC are mapped to these bits as it makes polling
easier.
INTR[0] – Indicates Normal interrupt. It is set to 1 if any interrupts in
NORMAL_INT_STAT_R[14:0] register is ‘1’
INTR[1] – Indicates Error interrupt. Set to 1 if NORMAL_INT_STAT_R[15]
register is ‘1’
These are cleared by clearing the respective interrupts in
NORMAL_INT_STAT_R and ERROR_INT_STAT_R
Value After Reset: 0x0

45:34 REGADDR R/W Specifies the address of the MSHC register that the JTAG I/F is trying to
[11:0] access.
Specify the offset of MSHC register address as defined in the databook here.
The offset remains the same irrespective of AHB I/F or JTAG I/F
Value After Reset: 0x0

33:32 REGSIZE R/W MSHC has registers of sizes 8bit, 16bit and 32bits. Hence this filed is
[1:0] necessary to specify the active length of the 4Byte REGDATA payload.
Only the Active Bytes are written into the addressed MSHC register. And
during READ only the content from Active Bytes are valid (others can be
masked). Refer
0x0 – Register size is Byte (8bits) hence only REGDATA[7:0] is valid.
0x1 – Register size is Half-Word (16bits) ) hence only REGDATA[15:0] is valid.
0x2 – Register size is Word (32bits) hence complete REGDATA [31:0] is valid.
0x3 – Reserved
Data bytes which are invalid should be padded with zeroes when Write
commands. During Reads, data on invalid bytes should be ignored/masked.
Value After Reset: 0x0

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Table 2-6 Fields for Register: RACDR

Memory
Bits Name Access Description

31:0 REGDATA R/W This is the data payload filed of the MSHC register access instruction.
[31:0]
When WRn is 1:
The valid bytes of REGDATA is written into MSHC register whose offset is
addressed by REGADDR. This is completed in a single JTAG DR-shift and
update

When WRn is 0:
This indicates to the IP that JTAG I/F wishes to read the data present in
register which is address by REGADDR.
A total of 2 JTAG instructions are needed to get data on tdo output.
The Update cycle of first JTAG Read instruction will inform IP the intent to
read, and the capture cycle of second JTAG Read instruction will load the data
from addressed MSHC register into RACDR.REGDATA. This will now be
shifted out on tdo during DR-SHIFT of second JTAG instruction.

Value After Reset: 0x0

2.6.2.3 BR – Bypass register

■ Name: TAP Bypass register
■ Description: Single bit register/flop that connects tdi to tdo
■ Size: 1 bit

BR

Table 2-7 Fields for Register: BR

Bits Name Memory Access Description

0 BR RW When selected, BR register connects tdi input to tdo via a single flop.
Value After Reset: 0x0

2.6.3 Description of JTAG Registers Access

2.6.3.1 RACDR's Register Access Instruction Format

RACDR is a 50-bit TAP Data register which is used to shift-in the register access instruction for JTIU. This
instruction is decoded by DWC_mshc to perform the corresponding register WRITE or READ operation.

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Figure 2-22 RACDR Format

50 bits
WRn STATUS INTR[1:0] REGADDR[11:0] REGSIZE[1:0] REGDATA[31:0]

Valid REGDATA Length:

DWC_mshc controller has registers of size Byte, Half-Word and Word sizes. Hence it is necessary to specify
the size of the register being accessed. The valid REGDATA for a transfer is determined by REGSIZE [1:0].
Following table shows how the data is packed based on the REGSIZE attribute. Correct behavior is
guaranteed only when REGDATA follows the format as shown in Table 2-8.
Byte lanes marked as "Valid" mean that data is valid on these lanes
Byte lanes marked as 'XX' mean these are don't care, these should be padded with zero for Write accesses
and the value on these should be ignored/masked on tdo for Read accesses.

Table 2-8 Register Data Selection

REGSIZE[1:0] REGDATA[31:24] REGDATA[23:16] REGDATA[15:8] REGDATA[7:0]

0x2 (word, 32bits) Valid Valid Valid Valid

0x1 (Half-Word) XX XX Valid Valid

0x0 (Byte) XX XX XX Valid

The JTIU module takes care of data alignment based on REGADDR [1:0]. Following are some register access
examples

Example 1: Register access to 16bit CMD_R register which is at offset 0xE

■ REGSIZE is 0x1 since it’s a 16bit register
■ REGADDR is 0xE, same as mentioned in databook
The valid bytes in this case are REGDATA[15:0] and the value to be written should be placed here.
■ Lets consider that its a WRITE access, in which case WRn is 1
■ Based on these the RACDR format looks like as shown in Figure 2-23
■ In case of a Read access the valid data would have been available in the same valid bytes

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Figure 2-23 RACDR Format 1

WRn Status & INTR REGADDR[11:0] REGSIZE[1:0] REGDATA[31:16] REGDATA[15:0]

1 0xE 0x1 XX CMD_R[15:0]

Example 2: Register access to 8bit TOUT_CTRL_R register which is at offset 0x2E

■ REGSIZE is 0x0 since it’s a 8bit register
■ REGADDR is 0x2E, same as mentioned in databook
■ The valid byte in this case is REGDATA[7:0] and the value to be written should be placed here.
■ Let’s consider that it’s a WRITE access, in which case WRn is 1
■ Based on these the RACDR format looks like as shown in Figure 2-24
■ In case of a Read access the valid data would have been available in the same active bytes i.e
REGDATA [7:0]

Figure 2-24 RACDR Format 2

WRn Status & INTR REGADDR[11:0] REGSIZE[1:0] REGDATA[31:24] REGDATA[7:0]

1 0x2E 0x0 XX TOUT_CTRL_R

2.6.3.2 WRITE Access Using RACDR

Figure 2-25 shows the write access for register RACDR. The write access in DWC_mshc register needs a
single RACDR shift operation. The value in active bytes of REGDATA are written into the address register
at the end of update cycle. However, a successive READ/WRITE operation should be spaced apart by 3
IDLE cycles if the destination register is synchronous and clocked by tck.
If the destination register is in a different clock domain, it is suggested that the frequency ratios to be
considered and an IDLE cycle delay equivalent of [10 register domain cycles + 10 tck cycles] is used.

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Figure 2-25 JTAG - Register Write Access

tck

~~ ~~
Capture-DR

Insert IDLE cycles

Shift-DR between two JTAG
transfers

Update-DR

RACDR xx shift shift shift New RACDR

New Write access decode & Sync

MSHC
Register Old Value New Value

2.6.3.3 Read Access Using RACDR

The read access needs two shift-DR operations. The update cycle at the end of first RACDR shift-DR informs
JTIU the intent to read from the addressed DWC_mshc register. The capture cycle at the beginning of
second RACDR’s shift-DR operation loads the register content into RACDR’s valid byte lanes. This is now
shifted out onto tdo during the shift-DR cycles of the second Shift-DR operation as shown in Figure 2-26.
■ The two operations should be spaced apart by the same cycle as mentioned for WRITE access
■ It is acceptable to pipeline a new register WRITE/READ access instruction with the second shift-in
for a previous READ instruction.
■ RACDR-1 is the first JTAG register access instruction that informs the intent to read
■ RACDR-2 is the second JTAG register access instruction during which read data is available on tdo
❑ RACDR-2 can be an independent Read/Write access instruction which is pipelined.
❑ It can also be a dummy transaction i.e exactly same as RACDR-1

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Figure 2-26 JTAG - Register Read access

tck

~~ ~~ ~~
Capture-DR

Insert IDLE cycles

Shift-DR between two JTAG
transfers addressed data is
shifted out on TDO
Update-DR

RACDR xx shift shift shift RACDR-1 new shift shift shift RACDR-
decode, Sync and addressed data is
New Write access select for read loaded in RACDR on
capture
JTIU_READ_DATA
(internal bus) xx Addressed read data

JTAG Transfer 1 JTAG Transfer 2

2.6.3.4 Register access status

RACDR’s STATUS bit indicates the Okay/Error status of the previous register access instruction. This bit is
also set if the new JTAG access is initiated before completing previous access with the controller. It is
advised to insert mode IDLE cycles between JTAG access if this error repeats. This is a Read-only bit hence
the value in this position on tdi is ignored. This value should be read as ‘0’ on tdo for all register read/write
accesses.

Note STATUS bit is unrelated to loopback test status

2.6.3.5 INTR bits

Loop back test sequence involves waiting for interrupts (BUF_RD_READY or ERR_INTERRPT) to
understand that controller completed the sequence. In the absence of DWC_mshc interrupt line being
available at SOC I/O level, these bits provide a means to poll for the same interrupts without actually
reading DWC_mshc registers.

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2.7 DMA vs Slave Mode of Data Transfer

2.7.1 Configuration Options
While certain applications demand high performance in terms of throughput from DWC_mshc, other
applications might require smaller area and power footprint while trading-off performance. DWC_mshc is a
highly configurable controller that offers wide variety of configuration options to suit applications with
different requirements.

2.7.2 Slave-Only Mode of Data Transfer

DWC_mshc is used to transfer data to and from storage devices, such as SD, eMMC. On the
system/application side, data can be transferred using either a high performance Master interface or Slave
interface as shown in Figure 2-27.

Figure 2-27 System side Data Transfer for DWC_mshc

AXI/AHB
Master

System Card Interface

Memory Logic

AHB
AHB master
Slave

DWC_mshc

When Master Interface is used, data is directly accessed from system memory by AXI/AHB. When slave
interface is used, data is accessed from the system memory by a separate AHB master and made available to
DWC_mshc using a data port register. This type of transfer is also called Non-DMA transfer or
Programmed Input Output (PIO) transfer. For more information on non-DMA/PIO transfer, see the
“Issuing CMD with Data Transfer (Not Using DMA/PIO)” in DesignWare Cores Mobile Storage Host
Controller User Guide.
A high throughput can be achieved using master interface for data transfer. If the application not need such
a high throughput, then the slave interface can be used for data transfer.
DWC_mshc offers a configuration option to operate only in the slave mode. In this case, DWC_mshc is
optimized for area and power by removing AXI/AHB master interface module, DMA engine, DMA-related
configuration registers, CQE engine, and any other logic that may be unnecessary. This can be done by de-
selecting the "Master Interface Present" checkbox in the Basic Configuration Parameters page. For
information on this parameter, refer to Parameter Descriptions chapter. For an understanding on how this
feature saves area and power, see “Area Savings While Using Optimized Clocking Mode” on page 622.

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2.8 DMA Engine

2.8.1 Overview of the DMA Engine
The DMA Engine unit handles data transfer between DWC_mshc and system memory. The key
features of this unit are as follows.
❑ Support SDMA/ADMA2/ADMA3 modes based on the configuration
❑ Fetch the descriptor and data, and schedule control and data packets (in UHS-II interface model).
The same DMA engine is used to interleave data transfer and descriptor fetch. This enables new
task descriptor fetches (for CMD44 and CMD45) while DMA is moving data during task
execution (for CMD46 and CMD47).
❑ The AXI transaction ID 0 is used for moving data and AXI transaction ID 1 is used to fetch task
descriptors.
❑ Pre-fetch data for back-to-back eMMC write commands
❑ Write back the received data packets to the system memory

2.8.2 Configuring DMA

DWC_mshc has a high performance master interface along with internal DMA to achieve the bandwidth of
high throughput application. By default, DWC_mshc offers the following types of internal DMAs:
■ SDMA
■ ADMA2
■ ADMA3
For information on how each DMA operates, see Appendix A.8, “Application Layer Data Flow”. Based on
the performance requirement on the Master interface, DWC_mshc can be programmed to operate in certain
DMA modes. However, DWC_mshc provides the DWC_MSHC_ADMA3_SUPPORT parameter that you
can deselect (as shown in Figure 2-28) to permanently remove ADMA3 while SDMA and ADMA2 exist in
DWC_mshc. By default, ADMA3 is always supported when a Master interface exists.

Figure 2-28 Deselecting ADMA3

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The ADMA3 capability is reflected on the CAPABILITIES2_R.ADMA3_SUPPORT register bit. This bit is
required if the SDMA or ADMA2 can provide the performance requirement or a use case does not need
ADMA3. Based on this register bit, DWC_mshc is optimized for area and power by removing support for
ADMA3. For information on how to disabling ADMA3 feature saves area and power, see “Area Savings
Without ADMA3 Mode” on page 622.

The software driver reads the CAPABILITIES2_R.ADMA3_SUPPORT register bit, to check

Note whether DWC_mshc supports ADMA3, before initiating an ADMA3 transfer as defined in the
“Issuing CMD with Data Transfer (ADMA3)” section in the DesignWare Cores Mobile Storage
Host Controller User Guide.

2.8.3 Selecting the DMA FIFO Depth

The DMA engine in DWC_mshc is implemented in the aclk domain and the RAM controller in the bclk
domain. DWC_mshc uses the DMA FIFO (that is set to two asynchronous FIFOs) to match the bclk and aclk
bandwidths. The depth of these FIFOs can affect the total bandwidth available on the AXI system bus and if
the bandwidth is insufficient, it can throttle the device/card data rate by using clock stopping (in
SD/eMMC mode) or by delaying FCRDY (in UHS-II mode).
Figure 2-29 shows the effect of different FIFO depths (4, 8 and 16) at four different aclk-bclk frequency
ratios. This data can be used as a guidance while configuring the DMA FIFO depth parameter
(DWC_MSHC_DMAQ_DEPTH). The data in Figure 2-29 considers a HS400 device capable of driving a
maximum data rate of 363.47 Mbps and the effective data rate for a given aclk-bclk combination is
normalized to the maximum possible data rate.

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Figure 2-29 FIFO Depth for Different ACLK-BCLK Frequency Ratios

100% 100% 100% 100% 100% 100% 100% 100%

99%

90%
87% 87%

80%
77%

70%

60%
56%

50%

40%

30%

20%

10%

0%
ACLK 300MHz - ACLK300- ACLK200- ACLK100-
BCLK 300MHz BCLK250 BCLK250 BCLK250

DMA FIFO Depth 16 DMA FIFO Depth 8 DMA FIFO Depth 4

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2.9 SRAM Controller

2.9.1 Overview of SRAM Controller
The SRAM controller interfaces the packet buffer of the host and the transaction controller units (SD and
UHS-II). The buffer depth can be configured between 256 and 32768 locations, where size of each location is
equal to the AXI data width (which depends on AXI/AHB data width as per the Master interface selection
between the AHB or AXI interface). Smaller buffer depth can be considered under the following conditions:
❑ In a low-area design
❑ Host has a high bandwidth with low latency
As write and read transfers to the cards do not occur simultaneously, a single shared buffer is used for read
and write operations to save area. During the data transfer command handshake, the read/write bit of the
command register is sampled and stored. This internal bit defines whether the DWC_mshc is in the read or
write mode.
The packet buffer uses a single clock single-port RAM synchronous to the controller base clock (bclk).

2.9.2 SPRAM Interface Timing

The SPRAM interface timings are shown in Figure 2-30 and Figure 2-31.

Figure 2-30 Timing Diagram for Writing to the RAM

clk

cs_n

wr_n

addr A1 A2 A3 A4

data_in D1 D2 D3 D4

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Figure 2-31 Timing Diagram for Reading from the RAM

clk

cs_n

wr_n

addr A1 A2 A3 A4

data_out D1 D2 D3

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2.10 Data Flow for Card Read in DWC_mshc

2.10.1 Packet Buffer Size Calculation
Packet buffer is a local storage used by DWC_mshc to store data packets while carrying out data transfer to
and from the card. An external SPRAM is used as a packet buffer. The width of the packet buffer is same as
the data width of the AXI/AHB interface (DWC_MSHC_MBIU_DW). The depth of packet buffer is decided
by the Packet Buffer Depth parameter (DWC_MSHC_PKT_BUFFER_DEPTH) except when enabling
Command Queuing Engine (CQE). As width of AXI interface is fixed for a particular system, it is important
to configure Packet buffer depth for better performance. Though a large buffer depth is preferred, an
optimal depth must always be chosen to minimize the area.
Figure 2-32 explains how data flows from the card interface (SD/SDIO/eMMC/UHS-II) to the AXI
interface through packet buffer for card read transfer. Received data from the card interface is written into
packet buffer. When one block of data (SD/SDIO/eMMC) or one burst of data (UHS-II) is received, DMA
starts transmitting that data to the system by reading it from packet buffer. For a card write transfer, data
flows in the reverse direction. DMA writes data into packet buffer that is subsequently read by the Card
Interface logic.

Figure 2-32 Data Flow for Card Read in DWC_mshc

DWC_mshc

Card
SRAM Interface
DMA Logic SD/eMMC/
Controller
AXI UHS-II

aclk
Packet Buffer bclk
(External SPRAM) Card
Clock

DMA and Card interface logic can work simultaneously as read and write to packet buffer can be
interleaved. For card read, DMA can send out previous block while Card interface logic is receiving current
block. Whereas for card write, DMA can write current block into packet buffer while Card interface logic is
sending out previous block. This type of parallel processing is possible when following conditions are met:
■ Packet buffer depth is chosen based on recommendation given in Table 2-21.
■ Frequency of bclk is greater than or equal to recommended bclk frequency. Refer the section on
controller base clock in “Speed and Clock Requirements” on page 27.
■ Frequency of aclk is greater than or equal to selected bclk frequency.

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2.11 Tuning in DWC_mshc

DWC_mshc is compatible with SD 4.2 and eMMMC 5.1 protocols and both these protocols have speed
modes in which the incoming data must be sampled on a clock with a programmable sampling. Therefore, a
method called tuning is required to identify the correct phase where the data can be robustly sampled.
Following are the tuning and re-tuning modes supported in DWC_mshc:
■ Tuning flow based on CMD21 (eMMC) or CMD19 (SD)
■ Mode 1 (software assisted) Re-tuning flow
■ Mode 3 (hardware managed) re-tuning (that is, Auto-Tuning)
■ Software Driven Tuning Flow
This section discusses the following topics:
■ “Overview of Tuning” on page 72
■ “Tuning Scenarios” on page 73
■ “Mode 1 Re-Tuning” on page 75
■ “Software Tuning” on page 78
■ “Auto-Tuning or Mode 3 Re-Tuning” on page 79
■ “Signals Related to Tuning” on page 84
■ “Signals Related to Tuning” on page 84
■ “Registers Related to Tuning” on page 85
■ “Programming Tuning” on page 85
■ “Implementation Guidelines While Using Auto-Tuning” on page 85
■ “PHY Timing and Placement Guidelines” on page 85
■ “Internal Timing Requirements” on page 86
■ “Technology-Specific Cells for Auto-Tuning” on page 92

2.11.1 Overview of Tuning

Tuning is the process of identifying the clock phase at which the incoming data can be robustly sampled. It
is used as a training sequence for sampling high frequency incoming data on multiple data lines. At high
frequencies, the skew between the lines can dominate the overall data valid period, there by reducing the
data valid window that can be as low as 0.475 UI. To sample such an input stream, the tuning engine in
DWC_mshc requires an external programmable DelayLine (DL) to generate the multiple phases.
DWC_mshc works with DelayLines that generate 8, 16, 32, 64, or 128 phases (configured using the
DWC_MSHC_DL_CW parameter). As shown in Figure 2-33, the output of DWC_mshc signals
tuning_cclk_sel and tuning_cclk_sel_update are driven by the internal tuning engine and must be used for
phase control of the DelayLine. These outputs are used by tuning engine to change the incoming phase of
cclk_rx clock so that it can find the phase at which incoming data on sd_dat_in port can be robustly
sampled.

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Figure 2-33 Tuning

DWC_mshc
tuning_cclk_sel_update
tuning_cclk_sel[7:0]

Tuning and Sampling

Interface
Delay Line gated cclk_tx
cclk_rx
[Sampling] clock or card_clk

fixed_clk

sample_clk_sel
sd_dat_in

cclk_tx

tuning_cclk_sel Old Code New Code

tuning_cclk_update

The high-speed SDR modes that need tuning are eMMC HS200 and SD SDR104. The tuning sequence for SD
or eMMC is a software-assisted sequence in which the hardware controls the DelayLine and calculates the
phase for robust sampling, and the software determines the necessity for tuning and starting the tuning
sequence. For information on the tuning programming sequences, see the Programming chapter in the
DesignWare Cores Mobile Storage Host Controller User Guide.

2.11.2 Tuning Scenarios

Tuning engines look for errors in the received data or response frame at every selected phase step. If errors
are found, then the phase is considered unfit for sampling and such a step is called a Fail step. However, if
errors are not found, then the step is considered fit for sampling and such a step is called a Pass step. You
must design the DelayLine with a resolution such that at least three successive Pass steps can be recognized
by the tuning engine. A combination of Pass step and Fail step leads to scenarios show in Figure 2-34, all of
which are supported by the tuning engine. Figure 2-34 uses a DelayLine with 16 phase steps to describe the
supported tuning scenarios that are discussed in subsequent sections.

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Figure 2-34 Pass Step and Fail Step Scenarios

cclk_rx

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Phase steps

FPF
Fail steps Pass steps Fail steps
Scenario

PF Scenario Pass steps Fail steps

FP Scenario Fail steps Pass steps

All Pass
Pass steps
Scenario

PFP
Scenario Pass steps Fail steps Pass steps

PFPF
Pass steps Fail steps Pass steps Fail steps
Scenario

2.11.2.1 Fail-Pass-Fail (FPF) Scenario

In the Fail-Pass-Fail scenario, a single burst of Pass steps is sandwiched between two bursts of Fail steps. In
the example shown in Figure 2-34, the phase steps 2–9 are determined as Pass steps by the tuning engine.
Among eight passing phase steps, phase step six is determined as the phase for robustly sampling the
incoming data. If the default step was set to 0, the tuning engine stops at phase step 10 as it has identified a
complete passing burst, that is a bust of Pass steps between Fail steps. This also avoids double locking,
where the DelayLine can generate more than 360 degrees phase shift.

2.11.2.2 Pass-Fail (PF) Scenario

In case of a Pass-Fail, the total length of the DelayLine and the skews are such that tuning engine notices
only a single burst of Fail steps at the end of Pass step burst. In the example shown in Figure 2-34, the phase
steps 0 to 7 are Pass steps and the tuning engine determines phase step 4 as the phase for robustly sampling
incoming data.

2.11.2.3 Fail-Pass (FP) Scenario

In case of a Fail-Pass, the total length of the DelayLine and the skews are such that the tuning engine notices
only a single burst of Fail steps at the beginning of the Pass-step burst. In the example shown in Figure 2-34,

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the phase steps 7 to 15 are Pass steps and the tuning engine determines phase step 11 as the phase for
robustly sampling incoming data.

2.11.2.4 All Pass Scenario

An All pass case occurs if the skew between data lines is less than one step of the DelayLine and due to
resolution loss, the tuning engine determines all steps as Pass steps. The phase step for robustly sampling
incoming data depends on the default tuning step. With default step as 0, sampling step is selected as step 8.

2.11.2.5 Pass-Fail-Pass (PFP) Scenario

In case of Pass-Fail-Pass, the tuning engine notices two passing bursts. This happens when the DelayLine
length and the step 0 phase is such that the tuning engine can sample data launched in CycleN in the initial
phase-steps and the data launched in CycleN+1 in the latter phase steps. This is shown in Figure 2-35.

Figure 2-35 Sampling of Data in PFP

In these cases, the Tuning engines assume that the Pass steps for DataN-1 in clock period N would also
repeat for DataN in clock period N+1. Considering this assumption, tuning engine adds the Pass steps from
both the bursts to calculate a robust sampling point. In the example shown in Figure 2-34, the tuning engine
selects phase step15 as the phase for robustly sampling incoming data.

2.11.2.6 Pass-Fail-Pass-Fail (PFPF) Scenario

In case of Pass-Fail-Pass-Fail, the tuning engine notices one partial Pass step burst for DataN-1 and a
complete Pass-step burst for DataN+1. The tuning engine prefers a complete Pass step over partial Pass-step
bursts and selects a phase within the complete Pass-step burst for robustly sampling incoming data. In the
example shown in Figure 2-34, phase step 10 is selected as the phase for robustly sampling incoming data.

2.11.3 Mode 1 Re-Tuning

DWC_mshc implements Mode 1 re-tuning as per the SD HCI specification and is available for use even in
the eMMC mode of operation. Mode 1 re-tuning is similar to the tuning sequence, and a distinction between
the two is made using HOST_CTRL2_R.SAMPLE_CLK_SEL register field value. The SD HCI specification
recommends that software must invoke re-tuning sequence for every 4 MB of data transferred or as per the
re-tuning timer maintained by the software.
During re-tuning, the tuning engine tests the validity of the sampling window, using the information
gathered in the initial tuning sequence. If the window is unaltered, re-tuning sequence is quick (total
CMD21/CMD19 iterations equal to number of Pass-steps +1). In case of any drifts, re-tuning may result in
more CMD21/CMD19 iterations (equal to total steps of DelayLine).
Following are the tuning schema available for mode 1 re-tuning:

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■ “Threshold Based Selection Tuning Schema” on page 76

❑ “Backward Compatible Tuning Schema” on page 76
■ “Largest Sampling Window Tuning Schema” on page 77
You can select the desired tuning mode in the coreConsultant GUI under Host Controller Capabilities.

2.11.3.1 Threshold Based Selection Tuning Schema

This mode allows the tuning engine to select the first complete sampling window that meets the threshold
criteria defined.
In this mode a complete sampling window is preferred over a partial sampling window. Tuning stops when
a complete sampling window meets the threshold criteria. Tuning also stops when all the taps are parsed as
shown in Figure 2-36.

Figure 2-36 Threshold Based Selection Tuning Schema

You can set the threshold criteria using AT_CTRL_R.SWIN_TH_VAL.

Related Parameters:
You can enable this mode by default (on reset) using the following parameters.
■ DWC_MSHC_TUNE_WINTH_EN = 1
■ DWC_MSHC_TUNE_WINTH_VAL = <as required for design>

Related Registers:
You can also enable this mode using the following registers:
■ AT_CTRL_R.SWIN_TH_EN = 1
■ AT_CTRL_R.SWIN_TH_VAL = <as required for design>

■ The recommended default threshold for SWIN_TH_VAL is 0.3UI. You should however
Note arrive at this threshold based on System on Chip and DelayLine design aspects that could
shrink the sampling window.
■ System designers can choose this schema in cases where the minimum threshold value is
known and time taken to complete tuning needs to be optimized.

2.11.3.1.1 Backward Compatible Tuning Schema

This mode allows the tuning engine to function as it was in 1.50a and earlier releases of the DWC_mshc.

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In this mode, a complete sampling window is preferred over a partial sampling window. Tuning stops
when either a complete sampling window is found or when all taps are parsed. There is no minimum
threshold on the width of sampling window as shown in Figure 2-37.

Figure 2-37 Spurious Pass Step Ignored

Related Parameters:
You can enable this mode by default (on reset) using the following parameters:
■ DWC_MSHC_TUNE_WINTH_EN = 1
■ DWC_MSHC_TUNE_WINTH_VAL = 0

Related Registers:
You can also enable this mode using the following registers:
■ AT_CTRL_R.SWIN_TH_EN = 1
■ AT_CTRL_R.SWIN_TH_VAL = 0

Note This is not recommended if the DelayLine used has a jitter spec > [2 * TapDelay].

2.11.3.2 Largest Sampling Window Tuning Schema

This mode allows the tuning algorithm to move through all the taps of delay line to identify the largest
sampling window available.
In this mode, tuning stops only when all the taps are parsed. The algorithm picks the largest sampling
window as shown in Figure 2-38.

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Figure 2-38 Largest Sampling Window Tuning Schema

If there are two sampling windows of same length, then the first one is selected. A delay line generating
more than 1.25UI delay can result in double locking.

Related Parameters:
You can enable this mode by default (on reset) using the following parameters:
■ DWC_MSHC_TUNE_WINTH_EN = 0
■ DWC_MSHC_TUNE_WINTH_VAL = don't care

Related Registers:
You can also enable this mode using the following registers:
■ AT_CTRL_R.SWIN_TH_EN = 0
■ AT_CTRL_R.SWIN_TH_VAL = don't care

System designers can choose this schema in cases where the minimum threshold value is not
Note known and time taken to complete tuning is not a concern.

2.11.4 Software Tuning

DWC_mshc implements a fully software-controlled tuning sequence called the software tuning. The
software can set the AT_CTRL_R.SW_TUNE_EN bit to take control of tuning_cclk_sel,
tuning_cclk_sel_update and sample_clk_sel signals which form the tuning and data sampling interface.
When AT_CTRL_R.SW_TUNE_EN is set to 1, the software can write into the
AT_STAT_R.CENTER_PH_CODE bit to change the value of tuning_cclk_sel. While using software tuning,
software must calculate the center phase and periodic re-tuning of the sampling clock. For information on
the programming sequence for software tuning, see DesignWare Cores Mobile Storage Host Controller User
Guide.

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Figure 2-39 Software Tuning Timing Diagram

hclk

AT_CTRL_R.SW_TUNE_EN

AT_STAT_R.CENTER_PH_CODE xxx 0x4

cclk_tx

tuning_cclk_sel xxx 0x4

tuning_cclk_sel_update

sample_clk_sel

2.11.5 Auto-Tuning or Mode 3 Re-Tuning

Auto-tuning is a hardware-managed re-tuning feature that complies with the SD HCI Mode3 re-tuning
procedure. Auto-tuning removes the need for the host software to re-tune the sampling clock for every
4 MB of data transfer (SD HCI). A tuning sampling clock is recommended in both SD and eMMC modes to
ensure ease in timing closure and for robust operation while operating at high SDR speeds, such as SDR104
and HS200.
Following are some functionalities of the auto-tuning feature:
■ Requires tuning based on CMD19 (SD) or CMD21 (eMMC) for initialization
❑ Once initialized, the auto-tuning engine can detect drifts and calculate corrections when data
transfers are in progress.
■ Does not depend on tuning commands of SD/eMMC for drift detection or corrections
❑ This is necessary as auto-tuning happens in the background during regular data/CMD transfers.
■ Detects drifts for all active data lines of the controller
■ Provides a software selectable correction interval
❑ Corrections can be applied either at block boundary or between data transfers.
■ Handles drifts as shown in Figure 2-40
❑ Drift monitoring window is hardware initialized. Software can program the AT_CTRL_R register
to alter the initialized values, if required.

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❑ If auto-tuning fails to correct a detected drift, the Tuning-error interrupt is set.

Figure 2-40 Supported Drift Types

card_rx Clock
Tuning Steps 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

| Eye Width = 8 |
Post Tuning
Pass Window

| Eye Width = 8 |
Right Drift
Pass Window

| Eye Width = 8 |
Left Drift
Pass Window

| Eye Width = 6 |
Shrink
Pass Window

| Eye Width = 7 |
Shrink Right
Pass Window

| Eye Width = 7 |
Shrink Left
Pass Window

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2.11.5.1 Block Diagram

Figure 2-41 shows the top level block diagram for auto-tuning.

Figure 2-41 Auto-Tuning Top Level Block Diagram

Controller
autotuning_cclk_sel_update
autotuning_cclk_sel

Auto-Tuning
Interface
Auto-Tuning
Engine drift_cclk_rx Delay Line gated_cclk_tx
[Drift Measurement]

Auto-Tuning Correction
Initialization Interface Interface
tuning_cclk_sel_update
tuning_cclk_sel
Data Sampling
Interface

Tuning Engine cclk_rx Delay Line

[Sampling]

fixed_clk

sample_clk_sel
sd_data_in[*]

2.11.5.2 Auto-Tuning Operation

Auto-tuning requires a dedicated Delayline (DL) that is an instance of the sampling DelayLine. This
instance of DL is called as the Drift Measurement (DM) DelayLine.
Figure 2-42 shows the auto-tuning flow diagram and following is a procedure for an auto-tuning operation:
1. Software must initiate tuning sequence based on CMD19 (for SD) or CMD21 (for eMMC) for
initializing the Auto-tuning engine.
2. After initialization, the auto-tuning engine is activated by default for all Data read transfers.
3. Auto-Tuning engine uses a DM DelayLine to generate drift_cclk_rx.
4. The drift_cclk_rx is generated using the same source as cclk_rx; however, its phase is controlled by
the autotune_cclk_sel[] outputs of the auto-tuning engine.
5. Auto-Tuning engine uses the data sampled on drift_cclk_rx to check for drifts on the data lines. A
drift is detected if following data errors occur:
❑ Data CRC errors

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❑ Start bit error

❑ End bit error
These drift checks are active only when READ transfers are in progress in HS200/SDR104 modes.
6. On drift detection, auto-tuning engine sweeps through DM DelayLine phases until it finds a
sampling window without drifts.
7. The new sampling window range allows the auto-tuning engine to calculate a correction for the
sampling phase.
8. The calculated correction is applied on the sampling DelayLine using tuning_cclk_sel outputs at the
software-selected correction interval.
Once initialized, the proposed solution is capable of observing, measuring and correcting drifts in the
receive datapath independent of software interventions.

The errors described in section “Auto-Tuning Operation” on page 81 do not reflect as error
Note interrupts, as these are detected by using the drift clock with left and right edge values.

Figure 2-42 DWC_mshc Auto-tuning Engine Flow Diagram

Mode 1 Tuning

Wait for
Auto-Tuning

Transfer Start

No Drift Yes
Detected?

Calculate
No End of Correction
Transfer?

Wait for Correction

Interval
Yes

Apply
Correction

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2.11.5.3 Application of Correction

Auto-tuning circuit can apply the correction on the sampling DelayLine in either of the following conditions
selected by the software:
■ Between two data transfers
■ Between two blocks

2.11.5.4 Interface Timing

SDR104 and HS200 speed modes allow a minimum of 8 idle cycles between 2 blocks (block-gap) where the
device/card tri-states its output and is not driving any data. DWC_mshc changes auto_tuning_cclk_sel and
auto_tuning_cclk_update outputs synchronous to cclk_tx in this block gap.

Figure 2-43 Auto-Tuning Interface Timing

sd_dat_in CRC13 CRC14 CRC15 end Z1 Z2 Z3 Z3 Z4 Z5 Z6 Z7 Z8 Start Data

drift_cclk_rx

cclk_tx

autotuning_cclk_sel

Old New

autotuning_cclk_sel_update

2.11.5.5 Tuning Error

Tuning error is generated by the AT engine when AT detects that the sampling window is less than three
steps. Tuning error can also occur if AT engine detects CRC error on the same phase as the sampling phase.
This error is reflected on the bit ERROR_INT_STAT_R[TUNING_ERR].

2.11.5.6 Command-Line Tuning

Considering that command-line traffic is less compared to data-line traffic (a main command starts the data
transfer and sub-commands would be rare) the auto-tuning engine works only on data lines to detect drift,
and to calculate drift correction. The correction applied is applicable to both data lines and command line.

Note The recommended physical design constraints must be followed to ensure that the drift
correction calculated by AT engine do not adversely affect the Command-response capture.

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2.11.5.7 Auto-Tuning Supported Modes

Auto-tuning is supported only in HS200 (eMMC mode) and SDR104 (SD mode) modes.

2.11.5.8 Re-tuning Timer for Auto-Tuning

According to the SD specification, the timer load value is a capability, that is a configuration value and not a
programmable value. This value must be maintained by the software and not by the hardware.
The software must maintain the re-tuning timer and must start this timer at the end of a data transfer and
reset it when a new data transfer starts. software must invoke the CMD-based tuning procedure when this
timer expires.

2.11.5.9 Glitch-Free Phase Switching

The tuning and auto-tuning interface provides the auto-tuning_cclk_sel_update and
tuning_cclk_sel_update signals to indicate that the phase select code is being changed. The PHY or
DelayLine can use these signals to update the phase at a timing where no glitches are generated at the
output of DelayLines. If the update cannot be managed, DWC_mshc enables the phase select code to be
changed only after stopping cclk_rx and drift_cclk_rx clocks, and after changed clocks are restarted. This
results in safe phase code switching.
Clocks are stopped by pulling down clk2card_on output that is generated on cclk_tx. The gated clock has an
unknown phase relationship with cclk_rx and drift_cclk_rx due to DelayLines. This being the case
programmable latency fields of AT_CTRL_R can be used to define this relationship as shown in Figure 2-44.

Figure 2-44 Glitch-Free Phase Switching

cclk_tx

clk2card_on ]
:19
[20
L_R
C TR
_
AT

Old code New code

]
:17
[18
L_R
C TR
_
AT
PostCode
Change_delay

gated_cclk_tx

The Glitch-free clock switching feature is disabled by default and can be enabled by programming the
AT_CTRL_R[16] bit to 1. However, this feature can reduce the performance by a maximum of 2% as a few
cycles of clocks are stopped between a block.

2.11.6 Signals Related to Tuning

For more information, refer to Signal Descriptions chapter.

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2.11.7 Registers Related to Tuning

Following are the registers related to tuning:
■ AT_CTRL_R
■ AT_STAT_R

2.11.8 Programming Tuning

See the Tuning Sequences section in the Programming DWC_mshc chapter of the DesignWare Cores Mobile
Storage Host Controller User Guide.

2.11.9 Implementation Guidelines While Using Auto-Tuning

The following sections discuss guidelines to be considered while implementing auto-tuning in DWC_mshc:
■ “PHY Timing and Placement Guidelines” on page 85
■ “Internal Timing Requirements” on page 86
■ “Technology-Specific Cells for Auto-Tuning” on page 92

2.11.10 PHY Timing and Placement Guidelines

Following are the implementation guidelines for PHY timing and placement:
■ The Drift Measurement DelayLine and Sampling DelayLine must be two instance of the same
DelayLine design, and must be placed close to each other such that PVT variations on the Sampling
DelayLine match with those on the Drift Measurement DelayLine. For more information, see
Figure 2-41.
■ cclk_rx and drift_cclk_rx must be balanced such that the skew when both are set to generate the same
phase (tuning_cclk_sel == autotuning_cclk_sel) is less than 0.4*StepDelay, where StepDelay is the
lower bound delay introduced by each stage of delayLine.
■ CMD line must be skew-balanced with data lines, this is necessary as tuning tunes both CMD+DATA
but Auto-tuning only monitors for drifts in DATA lines

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2.11.11 Internal Timing Requirements

2.11.11.1 Data Path Skew Balancing

When configured, Auto-tuning monitors the same data that is being sampled on cclk_rx by the sampling
logic. The SD/eMMC databus path that is sampled on cclk_rx (Sampling path in Figure 2-45) must be skew
balanced with the data path being sampled on drift_cclk_rx (Auto-tuning path in Figure 2-45) to ensure
accurate results while using auto-tuning. A maximum skew of 0.5 step of the DelayLine must be maintained
between the two paths.
Path balancing must be done for individual databus lines. Every data bus line has one endpoint in Auto-
tuning path that needs to be balanced with one endpoint in the sampling path as shown in Figure 2-45.

Figure 2-45 Skew Balancing of Data Path

Controller

GEN_FST2.sample_meta[0]

Auto-Tuning Path
drift_cclk_rx

U_DWC_mshc_bcm21_drift_detect_sync

gen_drift_detect_0_
U_DWC_mshc_tune_auto_dd
DWC_mshc_tune_auto_dm
U_DWC_mshc_tune_auto

U_DWC_mshc_tune

mem_a Combo
rray
cdat_in_pe_pipe_r
U_RAM

U_DWC_msh c_2clkfifo_pipe_data
Posedge Sampling Path
sd_dat_in
cclk_rx_ds_mux

cclk_rx

sd_dat_stb

datastrobe_en
U_DWC_mshc_2clkfifo_posedge_data

U_DWC_mshc_sd4_sample

U_DWC_mshc_sd4_sync
U_DWC_mshc_sd4

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The following tables map the paths to be balanced when SD_DATA_WIDTH is configured for 8 bits:
■ Table 2-9 for DataLine 0
■ Table 2-10 for DataLine 1
■ Table 2-11 for DataLine 2
■ Table 2-12 for DataLine 3
■ Table 2-13 for DataLine 4
■ Table 2-14 for DataLine 5
■ Table 2-15 for DataLine 6
■ Table 2-16 for DataLine 7

Table 2-9 Data Path for DataLine 0 When SD_DATA_WIDTH = 8

Auto-Tuning
Auto-Tuning Path Path Endpoint Sampling Path
DataLine Hierarchy Flop Name Sampling Path Hierarchy Endpoint Flop Name

0 U_DWC_mshc_tune.DW GEN_FST2.sa U_DWC_mshc_sd4.U_DWC cdat_in_pe_pipe_r_reg[0]

C_mshc_tune_auto.DWC mple_meta[0] _mshc_sd4_sync.U_DWC_m
_mshc_tune_auto_dm.U_ shc_sd4_sample
DWC_mshc_tune_auto_d
d.gen_drift_detect_0_.U_
DWC_mshc_bcm21_drift_
detect_sync

Table 2-10 Data Path for DataLine 1 When SD_DATA_WIDTH = 8

Auto-Tuning
Auto-Tuning Path Path Endpoint Sampling Path
DataLine Hierarchy Flop Name Sampling Path Hierarchy Endpoint Flop Name

1 U_DWC_mshc_tune.DW GEN_FST2.sa U_DWC_mshc_sd4.U_DWC cdat_in_pe_pipe_r_reg[1]

C_mshc_tune_auto.DWC mple_meta[0] _mshc_sd4_sync.U_DWC_m
_mshc_tune_auto_dm.U_ shc_sd4_sample
DWC_mshc_tune_auto_d
d.gen_drift_detect_1_.U_
DWC_mshc_bcm21_drift_
detect_sync

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Table 2-11 Data Path for DataLine 2 When SD_DATA_WIDTH = 8

Auto-Tuning
Auto-Tuning Path Path Endpoint Sampling Path
DataLine Hierarchy Flop Name Sampling Path Hierarchy Endpoint Flop Name

2 U_DWC_mshc_tune.DW GEN_FST2.sa U_DWC_mshc_sd4.U_DWC cdat_in_pe_pipe_r_reg[2]

C_mshc_tune_auto.DWC mple_meta[0] _mshc_sd4_sync.U_DWC_m
_mshc_tune_auto_dm.U_ shc_sd4_sample
DWC_mshc_tune_auto_d
d.gen_drift_detect_2_.U_
DWC_mshc_bcm21_drift_
detect_sync

Table 2-12 Data Path for DataLine 3 When SD_DATA_WIDTH = 8

Auto-Tuning
Auto-Tuning Path Path Endpoint Sampling Path
DataLine Hierarchy Flop Name Sampling Path Hierarchy Endpoint Flop Name

3 U_DWC_mshc_tune.DW GEN_FST2.sa U_DWC_mshc_sd4.U_DWC cdat_in_pe_pipe_r_reg[3]

C_mshc_tune_auto.DWC mple_meta[0] _mshc_sd4_sync.U_DWC_m
_mshc_tune_auto_dm.U_ shc_sd4_sample
DWC_mshc_tune_auto_d
d.gen_drift_detect_3_.U_
DWC_mshc_bcm21_drift_
detect_sync

Table 2-13 Data Path for DataLine 4 When SD_DATA_WIDTH = 8

Auto-Tuning
Auto-Tuning Path Path Endpoint Sampling Path
DataLine Hierarchy Flop Name Sampling Path Hierarchy Endpoint Flop Name

4 U_DWC_mshc_tune.DW GEN_FST2.sa U_DWC_mshc_sd4.U_DWC cdat_in_pe_pipe_r_reg[4]

C_mshc_tune_auto.DWC mple_meta[0] _mshc_sd4_sync.U_DWC_m
_mshc_tune_auto_dm.U_ shc_sd4_sample
DWC_mshc_tune_auto_d
d.gen_drift_detect_4_.U_
DWC_mshc_bcm21_drift_
detect_sync

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Table 2-14 Data Path for DataLine 5 When SD_DATA_WIDTH = 8

Auto-Tuning
Auto-Tuning Path Path Endpoint Sampling Path
DataLine Hierarchy Flop Name Sampling Path Hierarchy Endpoint Flop Name

5 U_DWC_mshc_tune.DW GEN_FST2.sa U_DWC_mshc_sd4.U_DWC cdat_in_pe_pipe_r_reg[5]

C_mshc_tune_auto.DWC mple_meta[0] _mshc_sd4_sync.U_DWC_m
_mshc_tune_auto_dm.U_ shc_sd4_sample
DWC_mshc_tune_auto_d
d.gen_drift_detect_5_.U_
DWC_mshc_bcm21_drift_
detect_sync

Table 2-15 Data Path for DataLine 6 When SD_DATA_WIDTH = 8

Auto-Tuning
Auto-Tuning Path Path Endpoint Sampling Path
DataLine Hierarchy Flop Name Sampling Path Hierarchy Endpoint Flop Name

6 U_DWC_mshc_tune.DW GEN_FST2.sa U_DWC_mshc_sd4.U_DWC cdat_in_pe_pipe_r_reg[6]

C_mshc_tune_auto.DWC mple_meta[0] _mshc_sd4_sync.U_DWC_m
_mshc_tune_auto_dm.U_ shc_sd4_sample
DWC_mshc_tune_auto_d
d.gen_drift_detect_6_.U_
DWC_mshc_bcm21_drift_
detect_sync

Table 2-16 Data Path for DataLine 7 When SD_DATA_WIDTH = 8

Auto-Tuning
Auto-Tuning Path Path Endpoint Sampling Path
DataLine Hierarchy Flop Name Sampling Path Hierarchy Endpoint Flop Name

7 U_DWC_mshc_tune.DW GEN_FST2.sa U_DWC_mshc_sd4.U_DWC cdat_in_pe_pipe_r_reg[7]

C_mshc_tune_auto.DWC mple_meta[0] _mshc_sd4_sync.U_DWC_m
_mshc_tune_auto_dm.U_ shc_sd4_sample
DWC_mshc_tune_auto_d
d.gen_drift_detect_7_.U_
DWC_mshc_bcm21_drift_
detect_sync

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The following tables map the paths to be balanced when SD_DATA_WIDTH is configured for 4 bits:
■ Table 2-17 for DataLine 0
■ Table 2-18 for DataLine 1
■ Table 2-19 for DataLine 2
■ Table 2-20 for DataLine 3

Table 2-17 Data Path for DataLine 0 When SD_DATA_WIDTH = 4

Auto-Tuning
Auto-Tuning Path Path Endpoint Sampling Path
DataLine Hierarchy Flop Name Sampling Path Hierarchy Endpoint Flop Name

0 U_DWC_mshc_tune.DW GEN_FST2.sa U_DWC_mshc_sd4.U_DWC cdat_in_pe_pipe_r_reg[0]

C_mshc_tune_auto.DWC mple_meta[0] _mshc_sd4_sync.U_DWC_m
_mshc_tune_auto_dm.U_ shc_sd4_sample
DWC_mshc_tune_auto_d
d.gen_drift_detect_0_.U_
DWC_mshc_bcm21_drift_
detect_sync

Table 2-18 Data Path for DataLine 1 When SD_DATA_WIDTH = 4

Auto-Tuning
Auto-Tuning Path Path Endpoint Sampling Path
DataLine Hierarchy Flop Name Sampling Path Hierarchy Endpoint Flop Name

1 U_DWC_mshc_tune.DW GEN_FST2.sa U_DWC_mshc_sd4.U_DWC cdat_in_pe_pipe_r_reg[1]

C_mshc_tune_auto.DWC mple_meta[0] _mshc_sd4_sync.U_DWC_m
_mshc_tune_auto_dm.U_ shc_sd4_sample
DWC_mshc_tune_auto_d
d.gen_drift_detect_1_.U_
DWC_mshc_bcm21_drift_
detect_sync

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Table 2-19 Data Path for DataLine 2 When SD_DATA_WIDTH = 4

Auto-Tuning
Auto-Tuning Path Path Endpoint Sampling Path
DataLine Hierarchy Flop Name Sampling Path Hierarchy Endpoint Flop Name

2 U_DWC_mshc_tune.DW GEN_FST2.sa U_DWC_mshc_sd4.U_DWC cdat_in_pe_pipe_r_reg[2]

C_mshc_tune_auto.DWC mple_meta[0] _mshc_sd4_sync.U_DWC_m
_mshc_tune_auto_dm.U_ shc_sd4_sample
DWC_mshc_tune_auto_d
d.gen_drift_detect_2_.U_
DWC_mshc_bcm21_drift_
detect_sync

Table 2-20 Data Path for DataLine 3 When SD_DATA_WIDTH = 4

Auto-Tuning
Auto-Tuning Path Path Endpoint Sampling Path
DataLine Hierarchy Flop Name Sampling Path Hierarchy Endpoint Flop Name

3 U_DWC_mshc_tune.DW GEN_FST2.sa U_DWC_mshc_sd4.U_DWC cdat_in_pe_pipe_r_reg[3]

C_mshc_tune_auto.DWC mple_meta[0] _mshc_sd4_sync.U_DWC_m
_mshc_tune_auto_dm.U_ shc_sd4_sample
DWC_mshc_tune_auto_d
d.gen_drift_detect_3_.U_
DWC_mshc_bcm21_drift_
detect_sync

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2.11.12 Technology-Specific Cells for Auto-Tuning

Auto-tuning does not use or mandate any technology-specific cells but you can replace the
DWC_mshc_tune_auto_dd module, if required

2.11.12.1 The DWC_mshc_tune_auto_dd Module

Th DWC_mshc_tune_auto_dd module is used to sample incoming data on sd_dat_in using drift_cclk_rx
clock. This module internally implements a 2-stage synchronizer/Delay that samples
sd_dat_in[SD_DAT_WIDTH-1:0] on drift_cclk_rx. By default, as drift_cclk_rx
(AT_CTRL_R.WIN_EDGE_SEL==0x0) samples sd_dat_in on the edges that are prone to drift, and hence,
these flip flops in DWC_mshc_tune_auto_dd are prone to metastability. You can replace these flip flops
with technology-specific flip flops that are metastable-hardened.
After tuning, sd_data_in can be sampled correctly using drift_cclk_rx (left/right phases) and cclk_rx (center
phase), and hence, sd_dat_in[] bus must meet the timing in both cclk_rx and drift_cclk_rx domains. The
synchronizer in the DWC_mshc_tune_auto_dd module avoids metastability propagation only if the drift
can cause data_ drift_cclk to be metastable.

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2.12 Memory
It is recommended that you select minimum size of the packet buffer as shown in Figure 2-21 that lists and
explains minimum packet buffer size for each card type.
Table 2-21 Minimum Packet Buffer Size

Card Type Minimum Packet Buffer Size (Bytes)

SD/SDIO/eMMCa 2 x Maximum Block Size

■ eMMC with CQE enabled and 2 x Maximum Block Size + 32 words
■ DWC_MSHC_EMMC_CQE_EXTRA_ROW
(Need additional packet buffer rows for
Command queuing) parameter setb

UHS-IIc 2 X Maximum N_FCU X Maximum Block Size

a For SD/SDIO/eMMC mode, it depends on maximum size of the data block (DWC_MSHC_MAX_BLK_SIZE)
b
Command queuing engine for eMMC mode uses 32 rows of packet buffer for its own storage in addition to the data. This
reduces effective storage available for the data. To improve the performance, depth packet buffer can be increased by 32.
You need to set the DWC_MSHC_EMMC_CQE_EXTRA_ROW (Need additional packet buffer rows for Command queuing)
parameter. Requirement of minimum packet buffer size increases to 32 in this case. Refer Example 2 for clarification.
c
For UHS-II mode, as data is processed in units of burst, it depends on maximum number of blocks in one burst (Desired value
of Maximum N_FCU) and maximum block size (DWC_MSHC_LINK_MAX_BLK_SIZE). Maximum N_FCU supported by
DWC_mshc is automatically calculated from packet buffer depth and maximum block size for UHS-II mode and is set to the
parameter DWC_MSHC_LINK_N_FCU (Maximum Number of Blocks per Flow Control Unit).

If selected configuration has both SD/eMMC and UHS-II, then minimum packet buffer size is
Note maximum of the two.

Based on this minimum packet buffer size, appropriate packet buffer depth must be calculated and
configured in DWC_mshc. Minimum packet buffer size calculation is explained in the following examples:
■ Example 1:
Card interface type: SD + UHS-II
Maximum Block size: 512 bytes
Maximum N_FCU: 4
AXI data width: 32 bits
Minimum Packet Buffer Depth = (2*4*512)/((32/8)) = 1024 Rows
You can select this minimum value or any higher value using the “Packet Buffer Depth” option in
coreConsultant. You will now need an SRAM of configuration [DWC_MSHC_MBIU_DW X
DWC_MSHC_PKT_BUFFER_DEPTH].
■ Example 2:
Card interface type: SD + eMMC

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Maximum Block size: 2048 bytes

AXI data width: 64 bits
Command queuing: Enabled
DWC_MSHC_EMMC_CQE_EXTRA_ROWS: Disabled
Minimum packet buffer depth is given by:
Minimum Packet Buffer data depth (PBDD_min) = (2*2048)/((64/8))=512 Rows
In this case since, DWC_MSHC_EMMC_CQE_EXTRA_ROWS is disabled, and you must select a value that
is higher than the Minimum Packet Buffer depth using the “Packet Buffer Depth” option in coreConsultant
(in this example, 1024). You will now need an SRAM of configuration [DWC_MSHC_MBIU_DW X
DWC_MSHC_PKT_BUFFER_DEPTH].
■ Example 3:
Card interface type: SD + eMMC
Maximum Block size: 2048 bytes
AXI data width: 64 bits
Command queuing: Enabled
DWC_MSHC_EMMC_CQE_EXTRA_ROWS: Enabled
Minimum packet buffer depth is given by:
Minimum Packet Buffer data depth (PBDD_min) = (2*2048)/((64/8)) = 512
Minimum Packet Buffer depth (PBDD_min+32) = 544 Rows
In this case, as DWC_MSHC_EMMC_CQE_EXTRA_ROWS is enabled, you must select a value that is equal
to or higher than the Minimum Packet Buffer data depth using the “Packet Buffer Depth” option in
coreConsultant and you will now need an SRAM of configuration [DWC_MSHC_MBIU_DW X
(DWC_MSHC_PKT_BUFFER_DEPTH + 32)]. Therefore, for this example,
DWC_MSHC_PKT_BUFFER_DEPTH must be set to 512 if you wish to use the minimum packet buffer
depth. As DWC_MSHC_EMMC_CQE_EXTRA_ROWS is enabled, coreConsultant sets ram_addr width to
10 bits such that 544 rows can be addressed.
While using DMA, the host memory data buffer size and start address must not exceed 128 MB. If it
exceeds, the data buffer must be split using two descriptors such that an AXI/AHB transfer attempting to
cross the limit (of 128 MB) is not generated.

2.12.1 Packet Buffer Full/Empty

In spite of selecting recommended minimum packet buffer depth and proper clock frequencies for aclk and
bclk, packet buffer may become full or empty.
When packet buffer becomes full in card read, clock to the card is stopped in SD/eMMC mode to prevent
card from sending next data block. In UHS-II mode, FCRDY is not sent. When packet buffer is empty, data
block is not sent in SD/eMMC mode and FCREQ is not sent in UHS-II mode. In both of these cases, card
interface logic is idle. To minimize these scenarios, higher packet buffer depth must be selected.

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2.13 Interrupts
In DWC_mshc, interrupts are generated based on various events.
There are two interrupt outputs provided by DWC_mshc:
■ intr
■ wakeup_intr
The interrupt signal must be used as interrupt for different events during active mode. During standby
mode, wakeup_intr must be used to identify any wakeup event, such as card removal or insertion, or an
SDIO card interrupt. The interrupts are of level type, that is, the interrupt remains asserted (high) until it is
cleared by the host or the software.
The Interrupt Status Registers indicate the events that caused the interrupt generation. Each event can be
prevented from asserting the interrupt on the interrupt signal by setting the corresponding mask bits.
A bit in interrupt status register is set only if the corresponding interrupt status enable is set and interrupt
event is observed. This bit set in interrupt status register asserts interrupt only if corresponding bit in
interrupt signal enable is set.

Host driver is responsible for enabling wakeup signals and disabling interrupt signals when the
Note host system enters its standby mode, and for disabling wakeup signals and enabling interrupt
signals when host system goes into active mode. The host driver must not enable both at
same time. Interrupt signals are enabled using interrupt signal enable and wakeup signals are
enabled using wakeup event enable.

For information about interrupt wakeup events, refer to NORMAL_INT_STAT_R, ERROR_INT_STAT_R,

UHS_II_ERR_INTR_STATUS_R and WUP_CTRL_R registers in the DesignWare Cores Mobile Storage Host
Controller (DWC_mshc) Databook.

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2.14 Error Detection

DWC_mshc is capable of detecting different types of error in SD, eMMC, and UHS-II transactions. Error is
detected in either command or data portion of the transaction. When an error is detected, the Error interrupt
in Normal interrupt status register (NORMAL_INT_STAT_R) is set.
Controller has two interrupt status registers, namely Error Interrupt Status register (ERROR_INT_STAT_R)
and UHS-II Error Interrupt Status register (UHS_II_ERR_INTR_STATUS_R). If error occurs in the SD and
eMMC mode, one of the bits is set in the Error Interrupt Status register. Error detected in UHS-II mode is
reflected in UHS-II Error Interrupt Status register. Abort command is used to recover from error detected
during data transfer. In addition to these two registers, there are two more error status registers, namely
Auto CMD Error Status register and ADMA Error Status registers. The Auto Command Errors are used by
SD/eMMC mode, and ADMA error status is used in all three modes.
The following sections list errors detected by DWC_mshc based on the mode. For more information about
ERROR_INT_STAT_R and UHS_II_ERR_INTR_STATUS_R registers, refer to Register Descriptions chapter.

2.14.1 SD/eMMC Mode

Table 2-22 lists error types and categories into which they can be grouped for SD/eMMC mode.
Table 2-22 Error Types and Categories for SD/eMMC Mode

Error Type Categories

Command Errors ■ Command Timeout Error

■ Command CRC Error
■ Command End Bit Error
■ Command Index Error
■ Command Conflict Error
■ Response Error

Auto Command Errors ■ Command not issued by Auto

CMD12 Error
■ Auto Command Timeout Error
■ Auto Command CRC Error
■ Auto Command End Bit Error
■ Auto Command Index Error
■ Auto Command Conflict Error
■ Auto CMD response Error

Data Errors ■ Data Timeout Error

■ Data CRC Error
■ Data End bit Error
■ ADMA Error
■ Tuning Error

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2.14.2 UHS-II Mode

Table 2-23 lists error types and categories into which they can be grouped for UHS-II mode.

Table 2-23 Error Types and Categories for UHS-II Mode

Error Type Categories

Command Errors ■ Timeout for CMD_RES

■ TID Error
■ Framing Error
■ CRC Error
■ RES Packet Error
■ EBSY Error
■ Header Error

Data Errors ■ Timeout for Deadlock

■ ADMA Error
■ Unrecoverable Error
■ TID Error
■ Framing Error
■ CRC Error
■ Retry Expired Error
■ Header Error
■ EBSY Error

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2.15 DFT Features for Synopsys SD/eMMC PHY Production Tests

The Pseudo Random number generator along with loopback mode is meant to be used for production
testing of Synopsys SD/eMMC PHY. When enabled, PRBS generates that data pattern which is looped back
to the controller. The loopback itself can be Internal to the PHY or external to the PHY.

2.15.1 Pseudo Random Pattern Generation (PRBS)

DWC_mshc PRBS feature allows you to generate a pseudo-random pattern for loopback testing of the PHY.
PRBS is implemented using a 16bit LSFR which uses the following polynomial.

The initial (seed) value of the LSFR can be programmed using PRBS_CNG register, after the seeded LSFR
generates a pseudo-random 16bit data pattern on every valid cycle.

2.15.2 Loopback Mode

DWC_mshc can be configured in loopback mode using PHYLPBK_CNFG register. This feature is meant to
work in conjunction with Synopsys eMMC/SD PHY for production tests (See, PHY Databook).

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Figure 2-46 Loopback Architecture

Controller
Loopback_mode SD/eMMC PHY
Controller data path

Data Tx module
sd_dat_out[]

PRBS CRC16

data error status

Data Rx Module

PHY internal loopback

sd_dat_in
Data to Packet buffer
CRC16

CMD INDEX, CMD Tx

ARGUMENT
sd_cmd_out
CRC7

CMD Rx
cmd error status
sd_cmd_in
CRC7

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2.15.2.1 Transmission
Figure 2-46 shows the loopback architecture of the controller. When in loopback, DWC_mshc data
transmission (Tx) module uses pattern generated from the PRBS unit as the data to be sent out. The data is
sent out in frames similar to how it is transmitted in functional mode. Each frame consists of a start bit
indicating beginning of the frame and ends with an 'End' bit. CRC16 for the block of data is appended and
transmitted along with the frame as shown in Figure 2-47:

Figure 2-47 Loopback Frame Format

START END
BIT PRBS DATA CRC16
BIT

The data packing format in this frame is same as used in the functional mode for SD/eMMC data
transmission. The size of PRBS data to be transmitted is determined by the BLOCKSIZE_R register and the
number of such frames to be sent are determined by the BLOCKCOUNT_R register.
Frame shown in Figure 2-48 is sent on the CMD line in loopback mode. The contents of CMD_R (INDEX)
and ARGUMENT_R register are used as the data payload and a CRC7 checksum is used. This frame is same
as the functional mode command frame, but here the ARGUMENT_R register can be used to send a fully
programmable 32bit pattern on the CMD line.

Figure 2-48 Loopback Mode CMD Frame Format

START CMD_R. ARGUMENT_R[31:0] END

BIT 1 CRC7
CMD_INDEX < User defined 32b pattern > BIT

2.15.2.2 Reception
The incoming CMD and DAT frames sampled by the controller and are checked for framing correctness and
CRC correctness. CRC16 for the data frames and CRC7 in case of CMD frames are validated. Any errors
identified are reported using ERROR_INT_STAT_R register.
DWC_mshc uses the same sampling logic as used in the functional mode. This allows you to use features
such as; Tuning even when working on loopback mode. The data sampled is stored in DWC_mshc packet
buffer. This data can be read using PIO/DMA for software debug during bringup.

2.15.2.3 Buffer Management

DWC_mshc stores the received loopback data in the packet buffer of size configured by the users. Reception
of incoming data stops if the packet buffer goes full. Hence It is expected that software uses PIO to read the
data out of buffer In cases where more than 1 block/frame of data is being used for loopback mode
(BLOCKCONT > 1). This ensures that the buffer does not go full and the programmed number of blocks are
transmitted and received in the loopback mode.

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2.16 Debug User Sideband Signals

When the parameter DWC_MSHC_DEBUG_SIDEBAND_EN is set to 1, the signals dbg_*_task_id and
dbg_*_pyld_desc gives the CQE task ID and the type of transfer on the AXI interface respectively. These
values can be useful in debugging CQE transactions.
During commands CMD44/45/46 the CQE Task ID value is reflected on either the dbg_aw_task_id or
dbg_ar_task_id signal depending on the direction of the transfer.
Also to determine if the current transfer is a data transfer or a descriptor fetch the signals
dbg_aw_pyld_desc or dbg_ar_pyld_desc is set depending on the direction of the transfer.

Note During the task descriptor fetch, the value on the dbg_*_task_id signals are invalid.

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3
Parameter Descriptions
This chapter details all the configuration parameters. You can use the coreConsultant GUI configuration
reports to determine the actual configured state of the controller. Some expressions might refer to TCL
functions or procedures (sometimes identified as <functionof>) that coreConsultant uses to make
calculations. The exact formula used by these TCL functions is not provided in this chapter. However, when
you configure the controller in coreConsultant, all TCL functions and parameters are evaluated completely;
and the resulting values are displayed where appropriate in the coreConsultant GUI reports.
The parameter descriptions in this chapter include the Enabled: attribute which indicates the values
required to be set on other parameters before you can change the value of this parameter.
These tables define all of the configuration options for this component.
■ Basic Configuration on page 104
■ AXI Settings on page 108
■ AHB Master Bus settings on page 109
■ GPIO Configuration on page 110
■ Low Power Configuration on page 111
■ Clocking modes on page 113
■ Host Controller Capabilities on page 114
■ Maximum Current Capabilities on page 121
■ Preset Values on page 123
■ Re-locatable Register Offsets on page 136
■ Host Controller Version on page 138
■ UHS-II Specific on page 139
■ eMMC Capabilities on page 147
■ Command Queueing settings on page 149
■ Subsystem configuration on page 152

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3.1 Basic Configuration Parameters

Table 3-1 Basic Configuration Parameters

Label Description

Card Interface Settings

Card Interface Type Selects the type of Card interface.

Values:
■ SD + UHS-II (0)
■ SD (1)
■ UHS-II (2)
■ SD + eMMC + UHS-II (3)
■ SD + eMMC (4)
■ eMMC (5)
Default Value: SD + UHS-II
Enabled: Always
Parameter Name: DWC_MSHC_CARD_INTERFACE_TYPE

UHS-II PHY-LINK Interface Indicates the data bit width for the UHS-II PHY-LINK interface.
Width This is applicable only for UHS-II.
Values:
■ 8 bits (0)
■ 16 bits (1)
Default Value: 16 bits
Enabled: DWC_MSHC_UHS2_SUPPORT==1
Parameter Name: DWC_MSHC_PHY_LINK_WIDTH

SD/eMMC Data Interface Indicates the data bus width for the SD/eMMC interface.
Width It is recommended to use a 4-bit data interface width for an SD application and an 8-
bit data interface width for an eMMC application. However, there is no restriction on
using any width for an SD/eMMC application from the controller.
Values:
■ 4 bits (0)
■ 8 bits (1)
Default Value: 4 bits
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_SD_DAT_WIDTH

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Table 3-1 Basic Configuration Parameters (Continued)

Label Description

SD/eMMC Low Speed SDR Indicates DWC_mshc is configured to support SD/eMMC low speed mode SDR
only support upto 100MHz without PHY.
When selected, Controller provides a programmable option to launch sd_dat_out*
and sd_cmd_out* with respect to negative edge of cclk_tx. It also implements the
programmable option to sample sd_dat_in and sd_cmd_in with respect to negative
edge of cclk_rx. Tuning of sampling clock is not supported
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: DWC_MSHC_CARD_INTERFACE_TYPE != 2
Parameter Name: DWC_MSHC_LS_NO_PHY_MODE

Application Interface Settings

Master Interface Present Indicates whether Master Interface is present in DWC_mshc.

Master interface is used by DMA for transferring data to and from system memory.
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: Always
Parameter Name: DWC_MSHC_MST_IF_PRESENT

Master Interface Type Indicates the type of Master interface.

The DWC_mshc uses this interface for SDMA and ADMA operations.
Values:
■ AXI (0)
■ AHB (1)
Default Value: AXI
Enabled: DWC_MSHC_MST_IF_PRESENT==1
Parameter Name: DWC_MSHC_MST_INTERFACE_TYPE

Master Interface Address Indicates the Master bus (AXI/AHB) Address width.
Width Values:
■ 32-bit (32)
■ 64-bit (64)
Default Value: 32-bit
Enabled: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Parameter Name: DWC_MSHC_MBIU_AW

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Table 3-1 Basic Configuration Parameters (Continued)

Label Description

Master Interface Data Width Indicates the Master bus (AXI/AHB) Data width.
No distinction is made between read and write channels.
Note: Data width of external memory must be same as the AXI/AHB master bus
data width.
Values:
■ 32-bit (32)
■ 64-bit (64)
Default Value: 32-bit
Enabled: DWC_MSHC_MST_IF_PRESENT==1
Parameter Name: DWC_MSHC_MBIU_DW

Slave Interface Type Selects the type of Slave interface.

Currently, there is no option to select the slave interface type. The application uses
this interface for Register access.
Values:
■ AHB (0)
Default Value: AHB
Enabled: 0
Parameter Name: DWC_MSHC_SLV_INTERFACE_TYPE

Response Type for Nonexistent Specifies the Host Controller to generate AHB slave error response for nonexistent
Register Access register word access.

Values:
■ OKAY Response (0)
■ ERROR Response (1)
Default Value: OKAY Response
Enabled: DWC_MSHC_CRYPTO_SUPPORT==0
Parameter Name: DWC_MSHC_SLV_RESPONSE_TYPE

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Table 3-1 Basic Configuration Parameters (Continued)

Label Description

DMA and Packet Buffer Settings

Packet Buffer Depth (External Sets the depth of the Packet Buffer.
Memory Size) Packet buffer is a local storage used by DWC_mshc to store data packets while
carrying out data transfer to and from the card. An external SPRAM is used as a
packet buffer. The depth of external SPRAM must be same as value of this
parameter.
The depth of the packet buffer decides the number of blocks that can be pre-fetched
during a card write or the number of blocks that can be stored before throttling the
card interface during card read.
The selected Master Interface data width decides the total Packet Buffer Size
Packet Buffer Size (in bytes) = Packet Buffer Depth x AXI Data Width (in bytes)
It is recommended to select the minimum size of the Packet Buffer as:
■ 2 x Maximum Block Size (for SD/eMMC)
■ 2 x Maximum N_FCU x Maximum Block Size (for UHS-II)

Note: When CQE is enabled with extra rows in the packet buffer, you must select a
higher depth than the minimum required. Refer the "Packet Buffer Size Calculation"
section in the DWC_mshc Databook for more details.
Values: 256, 512, 1024, 2048, 4096, 8192, 16384, 32768
Default Value: 512
Enabled: Always
Parameter Name: DWC_MSHC_PKT_BUFFER_DEPTH

Internal FIFO Depth (DMA <-> Sets the depth of DMA'S Async FIFOs that transport data To/From Packet Buffer
External Memory) (External Memory). The depth must be selected based on AXI Clock (aclk) and
Base clock (bclk) frequencies and the target throughput.
Values: 4, 8, 16
Default Value: 4
Enabled: DWC_MSHC_MST_IF_PRESENT==1
Parameter Name: DWC_MSHC_DMAQ_DEPTH

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3.2 AXI Settings Parameters

Table 3-2 AXI Settings Parameters

Label Description

AXI Settings

AXI ID Width Indicates the width of the AXI ID.

Values: 1, ..., 12
Default Value: 4
Enabled: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Parameter Name: DWC_MSHC_AXI_IDW

Maximum Outstanding Read Selects the Maximum Outstanding Read Requests on AXI.
Requests Values: 4, 8
Default Value: 4
Enabled: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Parameter Name: DWC_MSHC_AXI_MAX_RD_REQUESTS

Maximum Outstanding Write Selects the Maximum Outstanding Write Requests on AXI.
Requests Values: 4, 8
Default Value: 8
Enabled: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Parameter Name: DWC_MSHC_AXI_MAX_WR_REQUESTS

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3.3 AHB Master Bus settings Parameters

Table 3-3 AHB Master Bus settings Parameters

Label Description

Master Bus Burst types

Enable AHB INCR16. Selects the Reset value of MBIU_CTRL_R.BURST_INCR16_EN register field.
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==1)
Parameter Name: DWC_MSHC_MBIU_BURST16EN

Enable AHB INCR8. Selects the Reset value of MBIU_CTRL_R.BURST_INCR8_EN register field.
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==1)
Parameter Name: DWC_MSHC_MBIU_BURST8EN

Enable AHB INCR4. Selects the Reset value of MBIU_CTRL_R.BURST_INCR4_EN register field.
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==1)
Parameter Name: DWC_MSHC_MBIU_BURST4EN

Enable AHB Undefined Length Selects the Reset value of MBIU_CTRL_R.UNDEFL_INCR_EN register field.
INCR. Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==1)
Parameter Name: DWC_MSHC_MBIU_UNDEFLBURSTEN

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3.4 GPIO Configuration Parameters

Table 3-4 GPIO Configuration Parameters

Label Description

GPIO Settings

GPIO Support Indicates that DWC_mshc has extra General Purpose Input/Output (GPIO) ports.
When this option is selected, DWC_mshc has extra input and output ports. The
number of input and output ports are determined by parameter
DWC_MSHC_NUM_GP_IN and DWC_MSHC_NUM_GP_OUT respectively. Note
that these ports are transparent to DWC_mshc.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: Always
Parameter Name: DWC_MSHC_GPIO_ENABLE

Number of input ports Indicates the number of General Purpose Input ports.
Values: 1, ..., 32
Default Value: 1
Enabled: DWC_MSHC_GPIO_ENABLE == 1
Parameter Name: DWC_MSHC_NUM_GP_IN

Number of output ports Indicates the number of General Purpose Output ports.
Values: 1, ..., 32
Default Value: 1
Enabled: DWC_MSHC_GPIO_ENABLE == 1
Parameter Name: DWC_MSHC_NUM_GP_OUT

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3.5 Low Power Configuration Parameters

Table 3-5 Low Power Configuration Parameters

Label Description

Clock Gating

Internally gate UHS2 base Indicates that the base clock to the UHS-II module must be gated internally when
clock the UHS-II interface is not used.
It is controlled using UHS-II interface enable bit in Host Control2 register. This is
applicable if the configuration supports both SD/eMMC and UHS-II interface types.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: (DWC_MSHC_CARD_INTERFACE_TYPE == 0) ||
(DWC_MSHC_CARD_INTERFACE_TYPE == 3)
Parameter Name: DWC_MSHC_INTERNAL_CLK_GATE

Internally gate Master Bus Inserts a clock gate to switch off the MBIU clocks when the module is idle.
Interface clock when inactive Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: DWC_MSHC_MST_IF_PRESENT == 1
Parameter Name: DWC_MSHC_MBIU_CLK_GATE

Internally gate DMA engine Inserts a clock gate to switch off the DMA clocks when the module is idle.
clock when inactive Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: DWC_MSHC_MST_IF_PRESENT == 1
Parameter Name: DWC_MSHC_DMA_CLK_GATE

Internally gate Command Inserts a clock gate to switch off the CQE clocks when the module is idle.
Queuing engine clock when Values:
inactive ■ false (0)
■ true (1)
Default Value: false
Enabled: DWC_MSHC_EMMC_CQE_EN == 1
Parameter Name: DWC_MSHC_CQE_CLK_GATE

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Table 3-5 Low Power Configuration Parameters (Continued)

Label Description

Internally gate Task scheduler Inserts clock gate to switch off the Task Scheduler's clock when the module is idle.
clock when inactive Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: DWC_MSHC_EMMC_CQE_EN == 1
Parameter Name: DWC_MSHC_TS_CLK_GATE

Internally gate ASYNC FIFO Inserts clock gate to switch of the asynchronous FIFO clocks when the FIFO is
clocks when inactive empty.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: Always
Parameter Name: DWC_MSHC_ASYNC_CLK_GATE

Type of Clock gating Selects between Latch based clock gate and Flop based clock gate
mechanism Values:
■ LATCH BASED (0)
■ FLOP BASED (1)
Default Value: FLOP BASED
Enabled: DWC_MSHC_ANY_CLK_GATE==1
Parameter Name: DWC_MSHC_CLKGATE_TYPE

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3.6 Clocking modes Parameters

Table 3-6 Clocking modes Parameters

Label Description

Grouping of clocks

Enable grouping of clocks to Enables grouping of clocks to merge. By default, all input clocks to DWC_mshc are
merge asynchronous to each other.
If this option is enabled, you must connect grouped clocks to a common clock
source external to the controller.
Note: Refer the "Clock I/O Interface" section in DWC_mshc User Guide for more
information.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: Always
Parameter Name: DWC_MSHC_CLKS_GROUP_EN

Select clocks to merge Selects a clock group to which same clock is connected.
Different options are provided among master clock (aclk/m_hclk), base clock (bclk)
and slave clock (hclk). The design is optimized based on selection of this clock
group. The design is optimized based on selection of this clock group.
Values:
■ Master, Slave and Base Clock (0)
■ Master and Base Clock (1)
■ Master and Slave Clock (2)
■ Base and Slave Clock (3)
Default Value: (DWC_MSHC_MST_IF_PRESENT == 1) ? 0 : 3
Enabled: (DWC_MSHC_CLKS_GROUP_EN==1) &&
(DWC_MSHC_MST_IF_PRESENT==1)
Parameter Name: DWC_MSHC_CLKS_GROUP_SEL

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3.7 Host Controller Capabilities Parameters

Table 3-7 Host Controller Capabilities Parameters

Label Description

DMA Support

SDMA Indicates that DWC_mshc supports SDMA.

Values:
■ false (0)
■ true (1)
Default Value: DWC_MSHC_MST_IF_PRESENT==1
Enabled: 0
Parameter Name: DWC_MSHC_SDMA_SUPPORT

ADMA2 Indicates that DWC_mshc supports ADMA2.

Values:
■ false (0)
■ true (1)
Default Value: DWC_MSHC_MST_IF_PRESENT==1
Enabled: 0
Parameter Name: DWC_MSHC_ADMA2_SUPPORT

ADMA3 Indicates that DWC_mshc supports ADMA3.

Values:
■ false (0)
■ true (1)
Default Value: DWC_MSHC_MST_IF_PRESENT==1
Enabled: DWC_MSHC_MST_IF_PRESENT==1
Parameter Name: DWC_MSHC_ADMA3_SUPPORT

SD/eMMC Tuning

Tuning Modes Selects the re-tuning method and limits the maximum data length.
This is applicable in SD UHS-I and eMMC modes.
Values:
■ Mode1 (0)
■ Mode3 (1)
■ Tuning Disabled (2)
Default Value: DWC_MSHC_LS_NO_PHY_MODE== 1 ? 2 : 0
Enabled: (DWC_MSHC_SD_EMMC_SUPPORT==1) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Parameter Name: DWC_MSHC_RETUNE_MODE

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Table 3-7 Host Controller Capabilities Parameters (Continued)

Label Description

Number of Re-Tuning Timer Indicates the initial value of the Re-Tuning Timer for Mode 1 to 3.
This is applicable only for eMMC and UHS-I modes.
Values:
■ Re-Tuning Timer Disabled (0)
■ 1 Second (1)
■ 2 Seconds (2)
■ 4 Seconds (3)
■ 8 Seconds (4)
■ 16 Seconds (5)
■ 32 Seconds (6)
■ 64 Seconds (7)
■ 128 Seconds (8)
■ 256 Seconds (9)
■ 512 Seconds (10)
■ 1024 Seconds (11)
■ Get Information from Other Source (15)
Default Value: Re-Tuning Timer Disabled
Enabled: (DWC_MSHC_SD_EMMC_SUPPORT==1) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Parameter Name: DWC_MSHC_RETUNE_TIMER

Tuning Required for SDR50 Indicates that DWC_mshc requires tuning to operate in SDR50.
This is applicable only for the UHS-I and eMMC modes.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: (DWC_MSHC_SD_EMMC_SUPPORT==1) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Parameter Name: DWC_MSHC_TUNE_SDR50_EN

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Table 3-7 Host Controller Capabilities Parameters (Continued)

Label Description

Number of Clock Phases Indicates the number of individual clock phases available for selection during tuning.
Available for Tuning When using a DelayLine, it indicates the number of steps supported. This is
applicable for UHS-I and eMMC modes.
Values:
■ 8 (3)
■ 16 (4)
■ 32 (5)
■ 64 (6)
■ 128 (7)
Default Value: 8
Enabled: (DWC_MSHC_SD_EMMC_SUPPORT==1) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Parameter Name: DWC_MSHC_DL_CW

Default tuning mode This sets the default, on Reset value for AT_CTRL_R.SWIN_TH_EN register field
When '1' this setting allows tuning algorithm to select the very the first sampling
window which meets the criteria set by SWIN_TH_VAL When '0' this setting
ensures tuning algorithm sweeps all the taps and settles at the largest sampling
window
Values:
■ Largest Sampling window mode (0)
■ Threshold based mode (1)
Default Value: Threshold based mode
Enabled: (DWC_MSHC_SD_EMMC_SUPPORT==1) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Parameter Name: DWC_MSHC_TUNE_WINTH_EN

Default Threshold value default value of AT_CTRL_R.SWIN_TH_VAL register, value is valid only if
AT_CTRL_R.SWIN_TH_EN is '1'
Values: 0, ..., (2**DWC_MSHC_DL_CW)-1
Default Value: ((2**DWC_MSHC_DL_CW)>>2)-1
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1 &&
DWC_MSHC_TUNE_WINTH_EN==1 && (DWC_MSHC_LS_NO_PHY_MODE==0)
Parameter Name: DWC_MSHC_TUNE_WINTH_VAL

Default Clock Phase Value Indicates the reset value of the tuning_cclk_sel output signal.
The tuning_cclk_sel output signal also gets initialized to this default value on tuning
reset. Tuning starts from this default value. This is applicable for UHS-I and eMMC
modes.
Values: 0, ..., (2**DWC_MSHC_DL_CW)-1
Default Value: 6
Enabled: (DWC_MSHC_SD_EMMC_SUPPORT==1) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Parameter Name: DWC_MSHC_DEF_DL_CODE

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Table 3-7 Host Controller Capabilities Parameters (Continued)

Label Description

Card Clock and Data timeout clock

Clock Multiplier Value Indicates the Clock Multiplier value of the Programmable Clock Generator.
■ 0: Clock Multiplier is Not Supported
■ 1: Clock Multiplier M = 2
■ 2: Clock Multiplier M = 3
■ .............
■ 255: Clock Multiplier M = 256
Values: 0, ..., 255
Default Value: 0
Enabled: Always
Parameter Name: DWC_MSHC_CLK_MULTIPLIER

Base Clock Frequency for Indicates the Maximum Base Clock Frequency for the card clock.
SDCLK/RCLK The Maximum Clock Frequency for an SD card is SDCLK and for an UHS-II card, it
is RCLK.
■ 0: Get information using a different method
■ 1: 1 MHz
■ 2: 2 MHz
■ .........
■ 255: 255 MHz
Values: 0, ..., 255
Default Value: 1
Enabled: Always
Parameter Name: DWC_MSHC_BASE_CLK_FREQ_SD

Timer Clock Frequency Unit Indicates the Timer Clock Frequency Unit.
Values:
■ KHz (0)
■ MHz (1)
Default Value: MHz
Enabled: Always
Parameter Name: DWC_MSHC_TIMER_CLK_FREQ_UNIT

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Table 3-7 Host Controller Capabilities Parameters (Continued)

Label Description

Timer Clock Frequency to Indicates the Timer Clock Frequency to detect Data Timeout Error.
detect Data Timeout Error The unit for this frequency is decided by the
DWC_MSHC_TIMER_CLK_FREQ_UNIT parameter.
■ 0: Get information using a different method
■ 1: 1 KHz/MHz
■ 2: 2 KHz/MHz
■ ............
■ 63: 63 KHz/MHz
Values: 0, ..., 63
Default Value: 1
Enabled: Always
Parameter Name: DWC_MSHC_TIMER_CLK_FREQ

SD/eMMC Power Supply and Driver Type Support

1.8V VDD1 Power Supply Indicates that DWC_mshc supports 1.8V VDD1 Power Supply.
Support Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: Always
Parameter Name: DWC_MSHC_VOLT18_VDD1_SUPPORT

SD 3.0V/Embedded 1.2V Indicates that DWC_mshc supports SD 3.0V/Embededded 1.2V VDD1 Power
VDD1 Power Supply Support Supply.
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: Always
Parameter Name: DWC_MSHC_VOLT30_VDD1_SUPPORT

3.3V VDD1 Power Supply Indicates that DWC_mshc supports 3.3V VDD1 Power Supply.
Support Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: Always
Parameter Name: DWC_MSHC_VOLT33_VDD1_SUPPORT

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Table 3-7 Host Controller Capabilities Parameters (Continued)

Label Description

Driver Type A Support Indicates that DWC_mshc supports Driver Type A for 1.8V Signaling.

Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_DRV_TYPE_A_SUPPORT

Driver Type C Support Indicates that DWC_mshc supports Driver Type C for 1.8V Signaling.
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_DRV_TYPE_C_SUPPORT

Driver Type D Support Indicates that DWC_mshc supports Driver Type D for 1.8V Signaling.
Values:
■ false (0)
■ true (1)
Default Value: true
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_DRV_TYPE_D_SUPPORT

Slot Type Indicates the Slot Types supported by DWC_mshc.

Values:
■ Removable Card Slot (0)
Default Value: Removable Card Slot
Enabled: Always
Parameter Name: DWC_MSHC_SLOT_TYPE

Miscellaneous

Maximum Block Size Indicates that DWC_mshc supported Maximum Block Size.
Values:
■ 512 Bytes (0)
■ 1024 Bytes (1)
■ 2048 Bytes (2)
Default Value: [<functionof> DWC_MSHC_MBIU_DW
DWC_MSHC_PKT_BUFFER_DEPTH]
Enabled: Always
Parameter Name: DWC_MSHC_MAX_BLK_SIZE

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Table 3-7 Host Controller Capabilities Parameters (Continued)

Label Description

Asynchronous Interrupt Indicates that DWC_mshc supports Asynchronous Interrupt.

Support This is applicable only for the SDIO mode.
Values:
■ false (0)
■ true (1)
Default Value: DWC_MSHC_SD_EMMC_SUPPORT==1
Enabled: 0
Parameter Name: DWC_MSHC_ASYNCINT_SUPPORT

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3.8 Maximum Current Capabilities Parameters

Table 3-8 Maximum Current Capabilities Parameters

Label Description

Maximum Current Settings

Maximum Current for 1.8V Indicates the Maximum Current for 1.8V VDD2.
VDD2 This is applicable only for UHS-II mode. The value indicates current in 4mA steps.
■ 0: Get information using a different method
■ 1: 4mA
■ 2: 8mA
■ .......
■ 255: 1020mA
Values: 0, ..., 255
Default Value: 0
Enabled: DWC_MSHC_VOLT18_VDD2_SUPPORT == 1
Parameter Name: DWC_MSHC_MAXCUR_VOLT18_VDD2

Maximum Current for 1.8V Indicates the Maximum Current for 1.8V VDD1.
VDD1 The value indicates current in 4mA steps.
■ 0: Get information using a different method
■ 1: 4mA
■ 2: 8mA
■ .......
■ 255: 1020mA
Values: 0, ..., 255
Default Value: 0
Enabled: DWC_MSHC_VOLT18_VDD1_SUPPORT == 1
Parameter Name: DWC_MSHC_MAXCUR_VOLT18_VDD1

Maximum Current for 3.0V Indicates the Maximum Current for 3.0V VDD1.
VDD1 The value indicates current in 4mA steps.
■ 0: Get information using a different method
■ 1: 4mA
■ 2: 8mA
■ ......
■ 255: 1020mA
Values: 0, ..., 255
Default Value: 0
Enabled: DWC_MSHC_VOLT30_VDD1_SUPPORT == 1
Parameter Name: DWC_MSHC_MAXCUR_VOLT30_VDD1

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Table 3-8 Maximum Current Capabilities Parameters (Continued)

Label Description

Maximum Current for 3.3V Indicates the Maximum Current for 3.3V VDD1.
VDD1 The value indicates current in 4mA steps.
■ 0: Get information using a different method
■ 1: 4mA
■ 2: 8mA
■ .......
■ 255: 1020mA
Values: 0, ..., 255
Default Value: 0
Enabled: DWC_MSHC_VOLT33_VDD1_SUPPORT == 1
Parameter Name: DWC_MSHC_MAXCUR_VOLT33_VDD1

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3.9 Preset Values Parameters

Table 3-9 Preset Values Parameters

Label Description

Preset Value for Initialization

Driver Strength for Default Specifies the Driver Strength for Default Speed.
Speed Values:
■ Not Applicable (0)
Default Value: Not Applicable
Enabled: 0
Parameter Name: DWC_MSHC_DRV_SEL_DFLTSPD

Clock Generator Select for Specifies the Clock Generator to be selected for Initialization.
Initialization ■ 1: External Programmable Clock Generator
■ 0: External Clock Divider
Values:
■ 10-bit Divided Clock Mode (0)
■ Programmable Clock Mode (1)
Default Value: 10-bit Divided Clock Mode
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_CLKGEN_SEL_INIT

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Table 3-9 Preset Values Parameters (Continued)

Label Description

Frequency of SDCLK for Indicates the Frequency of SDCLK for Initialization.

Initialization The Value indicates the Clock Divider Value for an external Clock Generator.

Following are values for the 10-bit divided clock mode:

■ 0: Base Clock
■ 1: Base Clock / 2
■ 2: Base Clock / 4
■ N: Base Clock / 2N
■ 1023: Base Clock / 2046

Following are values for the programmable clock mode:

■ 0: Base Clock * M
■ 1: Base Clock * M / 2
■ 2: Base Clock * M / 3
■ N-1: Base Clock * M / N
■ 1023: Base Clock * M / 1024
Where, M = Configured Clock Multiplier Value from the Host Controller Capability
Selection.
Values: 0, ..., 1023
Default Value: 0
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_FREQ_SEL_INIT

Preset Value for Default Speed

Clock Generator Select for Specifies the Clock Generator to be selected for Default Speed.
Default Speed ■ 1: External Programmable Clock Generator
■ 0: External Clock Divider
Values:
■ 10-bit Divided Clock Mode (0)
■ Programmable Clock Mode (1)
Default Value: 10-bit Divided Clock Mode
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_CLKGEN_SEL_DFLTSPD

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Table 3-9 Preset Values Parameters (Continued)

Label Description

Frequency of SDCLK for Indicates the Frequency of SDCLK for Default Speed.
Default Speed The Value indicates the Clock Divider Value for an external Clock Generator.

Following are values for the 10-bit divided clock mode:

■ 0: Base Clock
■ 1: Base Clock / 2
■ 2: Base Clock / 4
■ N: Base Clock / 2N
1023: Base Clock / 2046

Following are values for programmable clock mode:

■ 0: Base Clock * M
■ 1: Base Clock * M / 2
■ 2: Base Clock * M / 3
■ N-1: Base Clock * M / N
■ 1023: Base Clock * M / 1024
Where, M = Configured Clock Multiplier Value from the Host Controller Capability
Selection.
Values: 0, ..., 1023
Default Value: 0
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_FREQ_SEL_DFLTSPD

Preset Value for High Speed

Clock Generator Select for Specifies the Clock Generator to be selected for High Speed.
High Speed ■ 1: External Programmable Clock Generator
■ 0: External Clock Divider
Values:
■ 10-bit Divided Clock Mode (0)
■ Programmable Clock Mode (1)
Default Value: 10-bit Divided Clock Mode
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_CLKGEN_SEL_HSPD

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Table 3-9 Preset Values Parameters (Continued)

Label Description

Frequency of SDCLK for High Indicates the Frequency of SDCLK for High Speed.
Speed The value indicates the Clock Divider Value for an external Clock Generator.

10-bit Divided Clock Mode

■ 0: Base Clock
■ 1: Base Clock / 2
■ 2: Base Clock / 4
■ N: Base Clock / 2N
■ 1023: Base Clock / 2046

Programmable Clock Mode

■ 0: Base Clock * M
■ 1: Base Clock * M / 2
■ 2: Base Clock * M / 3
■ N-1: Base Clock * M / N
■ 1023: Base Clock * M / 1024
Where, M = Configured Clock Multiplier Value from the Host Controller Capability
Selection.
Values: 0, ..., 1023
Default Value: 0
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_FREQ_SEL_HSPD

Preset Value for SDR12

Driver Strength for SDR12 Specifies the Driver Strength for SDR12 Speed.
Speed Values:
■ Driver Type B (0)
■ Driver Type A (1)
■ Driver Type C (2)
■ Driver Type D (3)
Default Value: Driver Type B
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_DRV_SEL_SDR12

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Table 3-9 Preset Values Parameters (Continued)

Label Description

Clock Generator Select for Specifies the Clock Generator to be selected for SDR12 Speed.
SDR12 Speed ■ 1: External Programmable Clock Generator
■ 0: External Clock Divider
Values:
■ 10-bit Divided Clock Mode (0)
■ Programmable Clock Mode (1)
Default Value: 10-bit Divided Clock Mode
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_CLKGEN_SEL_SDR12

Frequency of SDCLK for Indicates the Frequency of SDCLK for SDR12 Speed.
SDR12 Speed The Value indicates the Clock Divider Value for an external Clock Generator.

10-bit Divided Clock Mode

■ 0: Base Clock
■ 1: Base Clock / 2
■ 2: Base Clock / 4
■ N: Base Clock / 2N
■ 1023: Base Clock / 2046

Programmable Clock Mode

■ 0: Base Clock * M
■ 1: Base Clock * M / 2
■ 2: Base Clock * M / 3
■ N-1: Base Clock * M / N
■ 1023: Base Clock * M / 1024
Where, M = Configured Clock Multiplier Value from the Host Controller Capability
Selection.
Values: 0, ..., 1023
Default Value: 0
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_FREQ_SEL_SDR12

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Table 3-9 Preset Values Parameters (Continued)

Label Description

Preset Value for SDR25

Driver Strength for SDR25 Specifies the Driver Strength for SDR25 Speed.
Speed Values:
■ Driver Type B (0)
■ Driver Type A (1)
■ Driver Type C (2)
■ Driver Type D (3)
Default Value: Driver Type B
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_DRV_SEL_SDR25

Clock Generator Select for Specifies the Clock Generator to be selected for SDR25 Speed.
SDR25 Speed ■ 1: External Programmable Clock Generator
■ 0: External Clock Divider
Values:
■ 10-bit Divided Clock Mode (0)
■ Programmable Clock Mode (1)
Default Value: 10-bit Divided Clock Mode
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_CLKGEN_SEL_SDR25

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Table 3-9 Preset Values Parameters (Continued)

Label Description

Frequency of SDCLK for Indicates the Frequency of SDCLK for SDR25 Speed.
SDR25 Speed The Value indicates the Clock Divider Value for an external.//Clock Generator.

10-bit Divided Clock Mode

■ 0: Base Clock
■ 1: Base Clock / 2
■ 2: Base Clock / 4
■ N: Base Clock / 2N
■ 1023: Base Clock / 2046

Programmable Clock Mode

■ 0: Base Clock * M
■ 1: Base Clock * M / 2
■ 2: Base Clock * M / 3
■ N-1: Base Clock * M / N
■ 1023: Base Clock * M / 1024
Where M = Configured Clock Multiplier Value from the Host Controller Capability
Selection
Values: 0, ..., 1023
Default Value: 0
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_FREQ_SEL_SDR25

Preset Value for SDR50

Driver Strength for SDR50 Specifies the Driver Strength for SDR50 Speed.
Speed This is applicable only for UHS-I mode.
Values:
■ Driver Type B (0)
■ Driver Type A (1)
■ Driver Type C (2)
■ Driver Type D (3)
Default Value: Driver Type B
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_DRV_SEL_SDR50

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Table 3-9 Preset Values Parameters (Continued)

Label Description

Clock Generator Select for Specifies the Clock Generator to be selected for SDR50 Speed.
SDR50 Speed ■ 1: External Programmable Clock Generator
■ 0: External Clock Divider
Values:
■ 10-bit Divided Clock Mode (0)
■ Programmable Clock Mode (1)
Default Value: 10-bit Divided Clock Mode
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_CLKGEN_SEL_SDR50

Frequency of SDCLK for Indicates the Frequency of SDCLK for SDR50 Speed.
SDR50 Speed The Value indicates the Clock Divider Value for an external Clock Generator.

10-bit Divided Clock Mode

■ 0: Base Clock
■ 1: Base Clock / 2
■ 2: Base Clock / 4
■ N: Base Clock / 2N
■ 1023: Base Clock / 2046

Programmable Clock Mode

■ 0: Base Clock * M
■ 1: Base Clock * M / 2
■ 2: Base Clock * M / 3
■ N-1: Base Clock * M / N
■ 1023: Base Clock * M / 1024
Where, M = Configured Clock Multiplier Value from the Host Controller Capability
Selection.
Values: 0, ..., 1023
Default Value: 0
Enabled: DWC_MSHC_SD_EMMC_SUPPORT==1
Parameter Name: DWC_MSHC_FREQ_SEL_SDR50

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Table 3-9 Preset Values Parameters (Continued)

Label Description

Preset Value for SDR104

Driver Strength for SDR104 Specifies the Driver Strength for SDR104 Speed.
Speed This is applicable only for UHS-I mode.
Values:
■ Driver Type B (0)
■ Driver Type A (1)
■ Driver Type C (2)
■ Driver Type D (3)
Default Value: Driver Type B
Enabled: (DWC_MSHC_SD_EMMC_SUPPORT==1) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Parameter Name: DWC_MSHC_DRV_SEL_SDR104

Clock Generator Select for Specifies the Clock Generator to be selected for SDR104 Speed.
SDR104 Speed ■ 1: External Programmable Clock Generator
■ 0: External Clock Divider
Values:
■ 10-bit Divided Clock Mode (0)
■ Programmable Clock Mode (1)
Default Value: 10-bit Divided Clock Mode
Enabled: (DWC_MSHC_SD_EMMC_SUPPORT==1) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Parameter Name: DWC_MSHC_CLKGEN_SEL_SDR104

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Table 3-9 Preset Values Parameters (Continued)

Label Description

Frequency of SDCLK for Indicates the Frequency of SDCLK for SDR104 Speed.
SDR104 Speed The Value indicates the Clock Divider Value for an external Clock Generator.

10-bit Divided Clock Mode

■ 0: Base Clock
■ 1: Base Clock / 2
■ 2: Base Clock / 4
■ N: Base Clock / 2N
■ 1023: Base Clock / 2046

Programmable Clock Mode

■ 0: Base Clock * M
■ 1: Base Clock * M / 2
■ 2: Base Clock * M / 3
■ N-1: Base Clock * M / N
■ 1023: Base Clock * M / 1024
Where, M = Configured Clock Multiplier Value from the Host Controller Capability
Selection.
Values: 0, ..., 1023
Default Value: 0
Enabled: (DWC_MSHC_SD_EMMC_SUPPORT==1) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Parameter Name: DWC_MSHC_FREQ_SEL_SDR104

Preset Value for DDR50

Driver Strength for DDR50 Specifies the Driver Strength for DDR50 Speed.
Speed This is applicable only for UHS-I mode.
Values:
■ Driver Type B (0)
■ Driver Type A (1)
■ Driver Type C (2)
■ Driver Type D (3)
Default Value: Driver Type B
Enabled: (DWC_MSHC_SD_EMMC_SUPPORT==1) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Parameter Name: DWC_MSHC_DRV_SEL_DDR50

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Table 3-9 Preset Values Parameters (Continued)

Label Description

Clock Generator Select for Specifies the Clock Generator to be selected for DDR50 Speed.
DDR50 Speed ■ 1: External Programmable Clock Generator
■ 0: External Clock Divider
Values:
■ 10-bit Divided Clock Mode (0)
■ Programmable Clock Mode (1)
Default Value: 10-bit Divided Clock Mode
Enabled: (DWC_MSHC_SD_EMMC_SUPPORT==1) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Parameter Name: DWC_MSHC_CLKGEN_SEL_DDR50

Frequency of SDCLK for Indicates the Frequency of SDCLK for DDR50 Speed.
DDR50 Speed The Value indicates the Clock Divider Value for an external Clock Generator.

10-bit Divided Clock Mode

■ 0: Base Clock
■ 1: Base Clock / 2
■ 2: Base Clock / 4
■ N: Base Clock / 2N
■ 1023: Base Clock / 2046

Programmable Clock Mode

■ 0: Base Clock * M
■ 1: Base Clock * M / 2
■ 2: Base Clock * M / 3
■ N-1: Base Clock * M / N
■ 1023: Base Clock * M / 1024
Where, M = Configured Clock Multiplier Value from the Host Controller Capability
Selection.
Values: 0, ..., 1023
Default Value: 0
Enabled: (DWC_MSHC_SD_EMMC_SUPPORT==1) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Parameter Name: DWC_MSHC_FREQ_SEL_DDR50

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Table 3-9 Preset Values Parameters (Continued)

Label Description

Preset Value for UHS-II/HS400

Driver Strength for HS400 Specifies the Driver Strength for HS400.
mode Values:
■ Driver Type B (0)
■ Driver Type A (1)
■ Driver Type C (2)
■ Driver Type D (3)
Default Value: Driver Type B
Enabled: (DWC_MSHC_SD_EMMC_SUPPORT==1) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Parameter Name: DWC_MSHC_DRV_SEL_HS400

Clock Generator Select for Specifies the Clock Generator to be selected for UHS-II Speed.
UHS-II Speed ■ 1: External Programmable Clock Generator
■ 0: External Clock Divider
Values:
■ 10-bit Divided Clock Mode (0)
■ Programmable Clock Mode (1)
Default Value: 10-bit Divided Clock Mode
Enabled: DWC_MSHC_UHS2_SUPPORT==1
Parameter Name: DWC_MSHC_CLKGEN_SEL_UHS2

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Table 3-9 Preset Values Parameters (Continued)

Label Description

Frequency of RCLK for UHS-II Indicates the Frequency of RCLK for UHS-II Speed.
Speed The Value indicates the Clock Divider Value for an external Clock Generator.

10-bit Divided Clock Mode

■ 0: Base Clock
■ 1: Base Clock / 2
■ 2: Base Clock / 4
■ N: Base Clock / 2N
■ 1023: Base Clock / 2046

Programmable Clock Mode

■ 0: Base Clock * M
■ 1: Base Clock * M / 2
■ 2: Base Clock * M / 3
■ N-1: Base Clock * M / N
■ 1023: Base Clock * M / 1024
Where, M = Configured Clock Multiplier Value from the Host Controller Capability
Selection.
Values: 0, ..., 1023
Default Value: 0
Enabled: DWC_MSHC_UHS2_SUPPORT==1
Parameter Name: DWC_MSHC_FREQ_SEL_UHS2

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3.10 Re-locatable Register Offsets Parameters

Table 3-10 Re-locatable Register Offsets Parameters

Label Description

(0x0E1-0x0E0) Pointer for UHS-II Settings

Select the Offset Address of Indicates the word aligned Offset Address of the UHS-II Settings Register.
the UHS-II Settings Register Values: 0x100, ..., 0xffc
Default Value: (DWC_MSHC_UHS2_SUPPORT > 0)? 328 : 3912
Enabled: DWC_MSHC_UHS2_SUPPORT==1
Parameter Name: DWC_MSHC_PTR_UHS2_SETTING

(0x0E3-0x0E2) Pointer for UHS-II Host Capabilities

Select the Offset Address of Indicates the word aligned Offset Address of the UHS-II Host Capability Register.
the UHS-II Host Capability Values: 0x100, ..., 0xffc
Register Default Value: (DWC_MSHC_UHS2_SUPPORT > 0)? 344 : 3928
Enabled: DWC_MSHC_UHS2_SUPPORT==1
Parameter Name: DWC_MSHC_PTR_UHS2_CAPABILITY

(0x0E5-0x0E4) Pointer for UHS-II Test

Select the Offset Address of Indicates the word aligned Offset Address of the UHS-II Test Register.
the UHS-II Test Register Values: 0x100, ..., 0xffc
Default Value: (DWC_MSHC_UHS2_SUPPORT > 0)? 360 : 3944
Enabled: DWC_MSHC_UHS2_SUPPORT==1
Parameter Name: DWC_MSHC_PTR_UHS2_TEST

(0x0E7-0x0E6) Pointer for Embedded Control

Select the Offset Address of Indicates the word aligned Offset Address of the Embedded Control Register.
the Embedded Control Values: 0x100, ..., 0xffc
Register Default Value: (DWC_MSHC_UHS2_SUPPORT > 0)? 364 : 3948
Enabled: Always
Parameter Name: DWC_MSHC_PTR_EMBDCTL

(0x0E9-0x0E8) Pointer for Vendor 1 Specific Area

Select the Offset Address of Indicates the Offset Address of the Vendor Specific Area 1.
the Vendor Specific Register Values: 0x100, ..., 0xefc
Default Value: 0x500
Enabled: Always
Parameter Name: DWC_MSHC_PTR_VENDOR1

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Table 3-10 Re-locatable Register Offsets Parameters (Continued)

Label Description

(0x0EB-0x0EA) Pointer for Vendor 2 Specific Area

Select the Offset Address of Indicates the Offset Address of the Vendor Specific Area 2.
the Vendor Specific Register The is used by eMMC HCI Registers. The address must be aligned to 128 bytes.
Values: 256, ..., ((DWC_MSHC_CRYPTO_SUPPORT > 0)?
((DWC_MSHC_CRYPTO_CFG > 0)? 8192 : 4096) : 3584)
Default Value: (DWC_MSHC_CRYPTO_SUPPORT > 0)?
((DWC_MSHC_CRYPTO_CFG > 0)? 8192 : 4096) : 384
Enabled: DWC_MSHC_CRYPTO_SUPPORT==0
Parameter Name: DWC_MSHC_PTR_VENDOR2

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3.11 Host Controller Version Parameters

Table 3-11 Host Controller Version Parameters

Label Description

Version Settings

Vendor Version Number Indicates the Vendor Version Number.

Values: 0x0, ..., 0xff
Default Value: 0x0
Enabled: Always
Parameter Name: DWC_MSHC_VENDOR_VER

Specification Version Number Indicates Specification Version Number.

Values: 0x0, ..., 0xff
Default Value: 0x5
Enabled: 0
Parameter Name: DWC_MSHC_SD_SPEC_VER

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3.12 UHS-II Specific Parameters

Table 3-12 UHS-II Specific Parameters

Label Description

General Capabilities register

Bus Topology Indicates the Supported Bus Topology.

This parameter is transparent to DWC_mshc. It is used by the application software
to know the supported bus topology for UHS-II.
Values:
■ P2P Connection (0)
■ Ring Connection (1)
■ HUB Connection (2)
■ HUB is Connected in Ring (3)
Default Value: P2P Connection
Enabled: Always
Parameter Name: DWC_MSHC_UHS2_BUS_TOPOLOGY

Number of Devices Supported Indicates the Number of Devices Supported.

This parameter is transparent to DWC_mshc. It is used by the application software
to know the number of devices for UHS-II.
Values:
■ Not Used (0)
■ 1 Device (1)
■ 2 Devices (2)
■ 3 Devices (3)
■ 4 Devices (4)
■ 5 Devices (5)
■ 6 Devices (6)
■ 7 Devices (7)
■ 8 Devices (8)
■ 9 Devices (9)
■ 10 Devices (10)
■ 11 Devices (11)
■ 12 Devices (12)
■ 13 Devices (13)
■ 14 Devices (14)
■ 15 Devices (15)
Default Value: 1 Device
Enabled: DWC_MSHC_UHS2_BUS_TOPOLOGY > 0
Parameter Name: DWC_MSHC_UHS2_NUM_DEVICES

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Table 3-12 UHS-II Specific Parameters (Continued)

Label Description

Removable/Embedded Type Indicates the Supported Card Type Removable/Embedded.

Values:
■ Removable Card (P2P) (0)
■ Embedded Devices (1)
■ Embedded Devices + Removable Card (2)
Default Value: Removable Card (P2P)
Enabled: DWC_MSHC_UHS2_BUS_TOPOLOGY > 0
Parameter Name: DWC_MSHC_UHS2_EMBEDDED_TYPE

Lane 2L-HD Support Specifies Two Lanes Half Duplex Support.

Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: Always
Parameter Name: DWC_MSHC_UHS2_LANE_2L_HD

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Table 3-12 UHS-II Specific Parameters (Continued)

Label Description

Group Allocation Power (GAP) Indicates the Maximum capability of the host power supply for a group configured by
a Host System.
This field is used to set the argument of DEVICE_INIT CCMD by the application
software.
Values:
■ Not Used (0)
■ 360 mW (1)
■ 720 mW (2)
■ 1080 mW (3)
■ 1440 mW (4)
■ 1800 mW (5)
■ 2160 mW (6)
■ 2520 mW (7)
■ 2880 mW (8)
■ 3240 mW (9)
■ 3600 mW (10)
■ 3960 mW (11)
■ 4320 mW (12)
■ 4680 mW (13)
■ 5040 mW (14)
■ 5400 mW (15)
Default Value: Not Used
Enabled: Always
Parameter Name: DWC_MSHC_UHS2_GAP

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Table 3-12 UHS-II Specific Parameters (Continued)

Label Description

Device Allocation Power (DAP) Indicates the Maximum capability of the host power supply for a device configured
by a Host System.
This field is used to set the argument of DEVICE_INIT CCMD by the application
software.
Values:
■ 360mW (0)
■ 360 mW (1)
■ 720 mW (2)
■ 1080 mW (3)
■ 1440 mW (4)
■ 1800 mW (5)
■ 2160 mW (6)
■ 2520 mW (7)
■ 2880 mW (8)
■ 3240 mW (9)
■ 3600 mW (10)
■ 3960 mW (11)
■ 4320 mW (12)
■ 4680 mW (13)
■ 5040 mW (14)
■ 5400 mW (15)
Default Value: 360mW
Enabled: Always
Parameter Name: DWC_MSHC_UHS2_DAP

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Table 3-12 UHS-II Specific Parameters (Continued)

Label Description

PHY Capabilities register

Minimum N_LSS_DIR Indicates the Minimum N_LSS_DIR required by the Host Controller.
Required Values:
■ 8 x 16 LSS (0)
■ 8 x 1 LSS (1)
■ 8 x 2 LSS (2)
■ 8 x 3 LSS (3)
■ 8 x 4 LSS (4)
■ 8 x 5 LSS (5)
■ 8 x 6 LSS (6)
■ 8 x 7 LSS (7)
■ 8 x 8 LSS (8)
■ 8 x 9 LSS (9)
■ 8 x 10 LSS (10)
■ 8 x 11 LSS (11)
■ 8 x 12 LSS (12)
■ 8 x 13 LSS (13)
■ 8 x 14 LSS (14)
■ 8 x 15 LSS (15)
Default Value: 8 x 16 LSS
Enabled: Always
Parameter Name: DWC_MSHC_PHY_N_LSS_DIR

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Table 3-12 UHS-II Specific Parameters (Continued)

Label Description

Minimum N_LSS_SYN Indicates the Minimum N_LSS_SYN required by the Host Controller.
Required Values:
■ 4 x 16 LSS (0)
■ 4 x 1 LSS (1)
■ 4 x 2 LSS (2)
■ 4 x 3 LSS (3)
■ 4 x 4 LSS (4)
■ 4 x 5 LSS (5)
■ 4 x 6 LSS (6)
■ 4 x 7 LSS (7)
■ 4 x 8 LSS (8)
■ 4 x 9 LSS (9)
■ 4 x 10 LSS (10)
■ 4 x 11 LSS (11)
■ 4 x 12 LSS (12)
■ 4 x 13 LSS (13)
■ 4 x 14 LSS (14)
■ 4 x 15 LSS (15)
Default Value: 4 x 16 LSS
Enabled: Always
Parameter Name: DWC_MSHC_PHY_N_LSS_SYN

Supported Speed Range Indicates the Supported Speed Range by the Host Controller.
Values:
■ Range A (0)
■ Range A and Range B (1)
Default Value: Range A
Enabled: Always
Parameter Name: DWC_MSHC_PHY_SPD_RANGE

PHY Revision Number Indicates PHY Revision Number.

Values: 0x0, ..., 0x3f
Default Value: 0x0
Enabled: 0
Parameter Name: DWC_MSHC_PHY_REV

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Table 3-12 UHS-II Specific Parameters (Continued)

Label Description

LINK/TRAN Capabilities register

Minimum Number of Data Gap Indicates the Minimum number of data gap (DIDL) Supported.
(DIDL) Supported ■ 4: 4 LSS
■ 5: 5 LSS
■ 6: 6 LSS
■ ...........
■ 255: 255 LSS
Values: 4, ..., 255
Default Value: 4
Enabled: Always
Parameter Name: DWC_MSHC_LINK_N_DATA_GAP

Maximum Block Size Indicates the Maximum Block Size Supported.

Supported ■ 512: 512 Bytes
■ 1024: 1024 Bytes
■ 2048: 2048 Bytes
Values:
■ 512 Bytes (512)
■ 1024 Bytes (1024)
■ 2048 Bytes (2048)
Default Value: [<functionof> DWC_MSHC_MBIU_DW
DWC_MSHC_PKT_BUFFER_DEPTH]
Enabled: Always
Parameter Name: DWC_MSHC_LINK_MAX_BLK_SIZE

Host Device Type Indicates Host Device Type.

Values:
■ Host Controller (0)
■ Not Used (1)
Default Value: Host Controller
Enabled: 0
Parameter Name: DWC_MSHC_LINK_DEVICE_TYPE

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Table 3-12 UHS-II Specific Parameters (Continued)

Label Description

Maximum Number of Blocks Indicates Maximum number of blocks in a flow control unit Supported.
per Flow Control Unit ■ 0: 256 Blocks
■ 1: 1 Block
■ 2: 2 Blocks
■ .............
■ 255: 255 Blocks
The value of this parameter is automatically calculated based on the packet buffer
depth, the AXI data width, and the maximum block size using following formula:
DWC_MSHC_LINK_N_FCU = (DWC_MSHC_PKT_BUFFER_DEPTH /
(2*(DWC_MSHC_LINK_MAX_BLK_SIZE / (DWC_MSHC_MBIU_DW/8))))
Values: 0, ..., 255
Default Value: SNPS_RSVDPARAM_6 >= 1 ? SNPS_RSVDPARAM_6 : 1
Enabled: 0
Parameter Name: DWC_MSHC_LINK_N_FCU

LINK Revision Number Indicates LINK Revision Number.

Values: 0x0, ..., 0x3f
Default Value: 0x0
Enabled: 0
Parameter Name: DWC_MSHC_LINK_REV

Miscellaneous Settings

Minimum T_DMT_ENTRY in Indicates the Minimum time for entering into dormant state (T_DMT_ENTRY) in
bclk (equivalent to 750 RCLK) terms of base clock period. The equivalent of 750 RCLK (minimum T_DMT_ENTRY
as defined by specification) in terms of supported maximum base clock frequency
shall be provided. It should be derived based on maximum supported base clock
and minimum RCLK frequencies.
Values: 0x0, ..., 0x3fff
Default Value: 0x2224
Enabled: Always
Parameter Name: DWC_MSHC_T_DMT_ENTRY

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3.13 eMMC Capabilities Parameters

Table 3-13 eMMC Capabilities Parameters

Label Description

eMMC Features

Boot Support Indicates that DWC_mshc supports booting from an eMMC device.
DWC_mshc supports both Mandatory and Alternate Boot modes.
Values:
■ false (0)
■ true (1)
Default Value: DWC_MSHC_EMMC_SUPPORT==1
Enabled: 0
Parameter Name: DWC_MSHC_EMMC_BOOT_EN

Data Strobe Support Indicates that DWC_mshc supports strobe to sample the data on data line
sd_dat_in.
When this option is selected, DWC_mshc has extra input (sd_dat_stb), which is
used as data strobe to sample the data. The data is sampled using sd_dat_stb only
when HS400 mode is selected. This data strobe is used to sample CRC Status in
case of Card Write and Data in case of Card Read. This option is enabled when
Data Interface Width is selected as 8 bits.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: (DWC_MSHC_EMMC_SUPPORT==1) &&
(DWC_MSHC_SD_DAT_WIDTH == 1) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Parameter Name: DWC_MSHC_EMMC_DATASTROBE_EN

Enhanced Strobe Support Indicates that DWC_mshc supports enhanced strobe.

The controller uses the data strobe (sd_dat_stb) to sample the response on
sd_cmd_in when the ENH_STROBE_ENABLE field in EMMC_CTRL_R register is
set to 1 while operating in HS400 mode.
Values:
■ false (0)
■ true (1)
Default Value: DWC_MSHC_EMMC_DATASTROBE_EN == 1
Enabled: 0
Parameter Name: DWC_MSHC_EMMC_CMDSTROBE_EN

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Table 3-13 eMMC Capabilities Parameters (Continued)

Label Description

Negedge Data transmission in Indicates DWC_mshc is configured to support Negedge transmission of data in
HS400 mode HS400 mode to help meet timing for both HS200 and HS400 device i/p timings.

Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: (DWC_MSHC_EMMC_SUPPORT==1) &&
(DWC_MSHC_LS_NO_PHY_MODE==0) &&
(DWC_MSHC_EMMC_DATASTROBE_EN==1)
Parameter Name: DWC_MSHC_NEG_DATA_HS400_MODE

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3.14 Command Queueing settings Parameters

Table 3-14 Command Queueing settings Parameters

Label Description

Command Queueing Engine Features

Command Queuing Support Indicates DWC_mshc supports Command Queueing. This is applicable only for
SD/eMMC. It is not applicable for UHS-II.
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: DWC-MSHC-SRC or DWC-MSHC-CRYPTO license is required to enable
this parameter when Card Interface type is SD/eMMC
Parameter Name: DWC_MSHC_EMMC_CQE_EN

Controller Command Queue Indicates the command queueing depth as supported by the device. Refer the
Depth Command Queue Depth specification of the eMMC device. The controller uses this
configuration to optimize the area of task scheduler.
■ 0: Maximum of 1 task can be queued. (Depth:1)
■ 1: Maximum of 2 tasks can be queued. (Depth:2)
■ 2: Maximum of 3 tasks can be queued. (Depth:3)
■ ......
■ 31: Maximum of 32 tasks can be queued. (Depth:32)
Values: 0, ..., 31
Default Value: 31
Enabled: 0
Parameter Name: DWC_MSHC_CMDQD

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Table 3-14 Command Queueing settings Parameters (Continued)

Label Description

Need Additional Packet Buffer Indicates that additional packet buffer rows will be used when Command Queuing is
Rows For CMD Queuing enabled.
The Command Queuing Engine requires a maximum of 32 rows of memory for local
storage in the packet buffer.
Consider that the packet buffer depth selected is 512 rows:
■ When de-selected, the configured DWC_MSHC_PKT_BUFFER_DEPTH is
shared between the data and local storage (not optimal). In this case, the total
number of packet buffer rows is equal to 512.
■ When selected, this option indicates that Packet Buffer can provide additional
rows (recommended). In this case, the total number of packet buffer rows is
equal to 544.
Values:
■ false (0)
■ true (1)
Default Value: DWC_MSHC_EMMC_CQE_EN == 1
Enabled: DWC_MSHC_EMMC_CQE_EN == 1
Parameter Name: DWC_MSHC_EMMC_CQE_EXTRA_ROWS

CQE Timer Clock Frequency Indicates the timer clock frequency multiplier value of the command queuing engine.
Multiplier The configured value reflects in the CQCAP.ITCFMUL of the HCI.
■ 0: 1 KHz
■ 1: 10 KHz
■ 2: 100 KHz
■ 3: 1 MHz
■ 4: 10 Mhz
Values: 0, ..., 4
Default Value: 3
Enabled: DWC_MSHC_EMMC_CQE_EN == 1
Parameter Name: DWC_MSHC_CQE_TIMER_CLK_FMUL

CQE Timer Clock Frequency Indicates the timer clock frequency value of the command queuing engine. The
configured value reflects in the CQCAP.ITCFVAL of the HCI.
■ 0: Not allowed
■ 1: Multiply by 1
■ 2: Multiply by 2
■ ......
■ 1023: Multiply by 1023
Values: 0, ..., 1023
Default Value: 200
Enabled: DWC_MSHC_EMMC_CQE_EN == 1
Parameter Name: DWC_MSHC_CQE_TIMER_CLK_FVAL

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Table 3-14 Command Queueing settings Parameters (Continued)

Label Description

Sideband signal support for Indicates the support of sideband signals in Master interface.
AXI Master Interface Type
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: (DWC_MSHC_MST_INTERFACE_TYPE==0) &&
(DWC_MSHC_EMMC_CQE_EN==1)
Parameter Name: DWC_MSHC_DEBUG_SIDEBAND_EN

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3.15 Subsystem configuration Parameters

Table 3-15 Subsystem configuration Parameters

Label Description

PHY type selection

SD/eMMC PHY Type Selects the SD/eMMC PHY to be used with this configuration inside top wrapper.
External Phy - SD/eMMC PHY will not be instantiated inside wrapper SNPS
SD/eMMC PHY - Synopsys DesignWare SD/eMMC PHY is instantiated inside the
wrapper.
Values:
■ External PHY (0)
■ SNPS SD/eMMC PHY (1)
Default Value: External PHY
Enabled: (DWC_MSHC_SD_EMMC_SUPPORT == 1) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Parameter Name: DWC_MSHC_SDEMMC_PHY_TYPE

UHS2 PHY Type Selects UHS2 PHY used for this configuration. External Phy - UHS2 PHY will not be
instantiated inside wrapper Partner-Vendor PHY - Partner Vendor's PHY and SNPS
SD/eMMC PHY are instantiated inside the wrapper.
Values:
■ External PHY (0)
■ Partner-Vendor PHY (1)
Default Value: External PHY
Enabled: DWC_MSHC_UHS2_SUPPORT==1 &&
DWC_MSHC_SDEMMC_PHY_TYPE==1
Parameter Name: DWC_MSHC_UHS2_PHY_TYPE

SD/eMMC PHY voltage Synopsys DesignWare SD/eMMC PHY is available in two voltage support variants.
support Use this option to pick the right variant that would be used in the subsystem
wrapper.
Values:
■ 3.3v and 1.8v (0)
■ 1.8v and 1.2v (1)
■ 1.8v (2)
Default Value: 3.3v and 1.8v
Enabled: DWC_MSHC_SDEMMC_PHY_TYPE==1
Parameter Name: DWC_MSHC_SDEMMC_PHY_VOLT

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Table 3-15 Subsystem configuration Parameters (Continued)

Label Description

Implement PGPINS for When selected Subsystem implements VDD/VSS/VDDIO PGPINS

SubSystem wrapper Values:
■ false (0)
■ true (1)
Default Value: DWC_MSHC_SDEMMC_PHY_TYPE==1
Enabled: DWC_MSHC_SDEMMC_PHY_TYPE==1
Parameter Name: DWC_MSHC_SDEMMC_PHY_PGPINS

Register settings for PHY

Synopsys SD/eMMC PHY When selected Controller implements Synopsys SD/eMMC PHY specific control
registers and status registers
Values:
■ false (0)
■ true (1)
Default Value: DWC_MSHC_SDEMMC_PHY_TYPE==1
Enabled: DWC_MSHC_SDEMMC_PHY_TYPE==1
Parameter Name: DWC_MSHC_SDEMMC_PHY_REGS

Implement Loopback and When selected Controller implements PRBS and Loopback features for PHY DFT
PRBS features Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: DWC_MSHC_SDEMMC_PHY_TYPE==1
Parameter Name: DWC_MSHC_SDEMMC_PHY_DFT

Implement JTAG Interface When selected, Controller implements JTAG I/F that allows test mode access to
MSHC registers. This is in addition to existing AHB I/F which is to be used for
accessing MSHC registers in functional mode
Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: DWC_MSHC_SDEMMC_PHY_TYPE==1
Parameter Name: DWC_MSHC_JTAGIF_EN

Base offset address for PHY Indicates the Base offset address of PHY registers address block
registers
Values: 0x100, ..., 0xefc
Default Value: 0x300
Enabled: 0
Parameter Name: DWC_MSHC_PTR_PHY_REGS

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Table 3-15 Subsystem configuration Parameters (Continued)

Label Description

SD/eMMC PHY active during Selects whether the PHY needs to be active during test mode
test scan mode Values:
■ false (0)
■ true (1)
Default Value: false
Enabled: DWC_MSHC_SDEMMC_PHY_TYPE==1
Parameter Name: DWC_MSHC_SDEMMC_PHY_TEST_ACTIVE

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4
Signal Descriptions
This chapter details all possible I/O signals in the controller. For configurable IP titles, your actual
configuration might not contain all of these signals.
Inputs are on the left of the signal diagrams; outputs are on the right.
Attention: For configurable IP titles, do not use this document to determine the exact I/O footprint of the
controller. It is for reference purposes only.
When you configure the controller in coreConsultant, you must access the I/O signals for your actual
configuration at workspace/report/IO.html or workspace/report/IO.xml after you have completed the
report creation activity. That report comes from the exact same source as this chapter but removes all the
I/O signals that are not in your actual configuration. This does not apply to non-configurable IP titles. In
addition, all parameter expressions are evaluated to actual values. Therefore, the widths might change
depending on your actual configuration.
Some expressions might refer to TCL functions or procedures (sometimes identified as <functionof>) that
coreConsultant uses to make calculations. The exact formula used by these TCL functions is not provided in
this chapter. However, when you configure the controller in coreConsultant, all TCL functions and
parameters are evaluated completely; and the resulting values are displayed where appropriate in the
coreConsultant GUI reports.
In addition to describing the function of each signal, the signal descriptions in this chapter include the
following information:
Active State: Indicates whether the signal is active high or active low. When a signal is not intended to be
used in a particular application, then this signal needs to be tied or driven to the inactive state (opposite of
the active state).
Registered: Indicates whether or not the signal is registered directly inside the IP boundary without
intervening logic (excluding simple buffers). A value of No does not imply that the signal is not
synchronous, only that there is some combinatorial logic between the signal's origin or destination register
and the boundary of the controller. A value of N/A indicates that this information is not provided for this IP
title.
Synchronous to: Indicates which clocks in the IP sample this input (drive for an output) when considering
all possible configurations. A particular configuration might not have all of the clocks listed. This clock
might not be the same as the clock that your application logic should use to clock (sample/drive) this pin.
For more details, consult the clock section in the databook.
Exists: Names of configuration parameters that populate this signal in your configuration.

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Validated by: Assertion or de-assertion of signals that validates the signal being described.
The I/O signals are grouped as follows:
■ AXI Interface on page 157
■ AHB Master Interface on page 168
■ AHB Slave Interface on page 171
■ RAM Interface on page 175
■ SD/eMMC Card Interface on page 177
■ Auto-Tuning Interface on page 180
■ UHS-II Card Interface on page 182
■ Card Clock Control on page 188
■ Card Bus Power Control Interface on page 192
■ Misc Signals Interface on page 194
■ SD/eMMC PHY Interface on page 200
■ Debug Sideband Interface on page 213
■ JTAG Interface on page 215

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4.1 AXI Interface Signals

aclk - - awaddr
aresetn - - awlen
awready - - awid
wready - - awburst
bid - - awvalid
bresp - - awqos
bvalid - - awsize
arready - - awlock
rid - - awcache
rresp - - awprot
rdata - - wid
rvalid - - wdata
rlast - - wstrb
- wlast
- wvalid
- bready
- araddr
- arlen
- arid
- arburst
- arvalid
- arqos
- arsize
- arlock
- arcache
- arprot
- rready

Table 4-1 AXI Interface Signals

Port Name I/O Description

aclk I AXI master clock

AXI Master interface and DMA runs at this clock.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: None
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-1 AXI Interface Signals (Continued)

Port Name I/O Description

aresetn I AXI Master interface reset

Your application should reset the AXI bridge master when it is
asserting reset to the core.
Asynchronous assertion and de-assertion synchronous to aclk
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: Asynchronous
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: Low

awaddr[(DWC_MSHC_MBIU_AW-1):0] O AXI Master Write Address

Specifies the address of the first transfer in a write burst transaction.
Associated control signals are used to determine addresses of
remaining transfers in the burst.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

awlen[(DWC_MSHC_BLW-1):0] O AXI Master Write Burst Length

Specifies the exact number of transfers in the burst and determines
the number of data transfers associated with the address.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

awid[(DWC_MSHC_AXI_IDW-1):0] O AXI Master Write Address ID

Indicates ID tag of write address signals.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-1 AXI Interface Signals (Continued)

Port Name I/O Description

awburst[1:0] O AXI Master Write Burst Type

Determines the type of burst used.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

awvalid O AXI Master Write Address/control valid indicator

Indicates whether valid write address and control information is
available. Address and control information remain stable until
awready signal is high.
■ 0: Address and control information not available
■ 1: Address and control information is available
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

awready I AXI Master Write Ready

Indicates that the slave is ready to accept address and associated
control signals.
■ 0: Slave not ready
■ 1: Slave ready
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

awqos[(DWC_QOS_DW-1):0] O QoS of the AXI Write data channel

Exists: (DWC_MSHC_QOS_EN==1)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-1 AXI Interface Signals (Continued)

Port Name I/O Description

awsize[2:0] O AXI Master Write burst size

Indicates size of each transfer in a burst. This is hardwired to 4 and 8
for 32-bit and 64-bit AXI master data width, respectively.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

awlock[1:0] O AXI Master Write Locked Transfer

This output signal is for completeness. Lock function is not supported
in DWC_mshc. It is hardwired to zero.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

awcache[3:0] O AXI Master Write Cache Control

This output signal is for completeness. It is hardwired to zero.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

awprot[2:0] O AXI Master Write Channel Protection Control

Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&

(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-1 AXI Interface Signals (Continued)

Port Name I/O Description

wid[(DWC_MSHC_AXI_IDW-1):0] O AXI Master Write ID

AXI master write identification ID. This signal is ID tag of write
transfer.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

wdata[(DWC_MSHC_MBIU_DW-1):0] O AXI Master Write Data

Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

wstrb[(DWC_MSHC_STRW-1):0] O AXI Master Write Strobes

Indicates which byte lanes to update in memory. There is one write
strobe for every eight bits of write data bus. wstrb[n] is associated
with wdata[8*n+7 : 8*n]
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

wlast O AXI Master Write Data Last of the current burst

Indicates last transfer in write burst.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-1 AXI Interface Signals (Continued)

Port Name I/O Description

wvalid O AXI Master Write Data Valid

Indicates that valid write data and stobes are available. Write data
and strobes remain stable until wready signal is high.
■ 0: Write data and stobes are not available
■ 1: Write data and stobes are available
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

wready I AXI Master Write Data accept

Indicates that the slave is ready to accept write data.
■ 0: Slave not ready
■ 1: Slave ready
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

bid[(DWC_MSHC_AXI_IDW-1):0] I AXI Master Write Response ID

The identification tag of the write response. The BID value must
match the AWID value of write transaction to which slave is
responding.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

bresp[1:0] I AXI Master Write Response

Indicates status of the write transaction.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-1 AXI Interface Signals (Continued)

Port Name I/O Description

bvalid I AXI Master Write Response Valid

Indicates valid write response is available.
■ 0: Write response is not available
■ 1: Write response is available
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

bready O AXI Master Write Response Accept

Indicates that the master can accept response information
■ 0: Master is not ready
■ 1: Master ready
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

araddr[(DWC_MSHC_MBIU_AW-1):0] O AXI Master Read Address

Specifies the address of the first transfer in a read burst transaction.
Associated control signals are used to determine addresses of
remaining transfers in the burst.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

arlen[(DWC_MSHC_BLW-1):0] O AXI Master Read Burst Length

Specifies the exact number of transfers in the burst and determines
the number of data transfers associated with the address.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-1 AXI Interface Signals (Continued)

Port Name I/O Description

arid[(DWC_MSHC_AXI_IDW-1):0] O AXI Master Read ID

Indicates ID tag of read address signals.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

arburst[1:0] O AXI Master Read Burst Type

Determines the type of burst used.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

arvalid O AXI Master Read Address/control valid indicator

Indicates valid read address and control information is available.
Address and control information remain stable until arready signal is
high.
■ 0: Address and control information not available
■ 1: Address and control information is available
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

arready I AXI Master Read Ready

Indicates that the slave is ready to accept address and associated
control signals.
■ 0: Slave not ready
■ 1: Slave ready
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-1 AXI Interface Signals (Continued)

Port Name I/O Description

arqos[(DWC_QOS_DW-1):0] O AXI Master Read QoS

Exists: (DWC_MSHC_QOS_EN==1)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

arsize[2:0] O AXI Master Read burst size

Indicates size of each transfer in a burst. This is hardwired to either 4
and 8 for 32 bit and 64 bit AXI master data width respectively.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

arlock[1:0] O AXI Master Read Locked Transfer

This output signal is for completeness. Lock function is not supported
in DWC_mshc. It is hardwired to zero.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

arcache[3:0] O AXI Master Read Cache Control

This output signal is for completeness. It is hardwired to zero.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

arprot[2:0] O AXI Master Read Channel Protection Control

Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-1 AXI Interface Signals (Continued)

Port Name I/O Description

rid[(DWC_MSHC_AXI_IDW-1):0] I AXI Read Response/Data ID

AXI master read identification ID. This signal is required by the AXI
bridge to identify a response for particular master request.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

rresp[1:0] I AXI Read Response

Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

rdata[(DWC_MSHC_MBIU_DW-1):0] I AXI Read Data

Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

rvalid I AXI Read Valid

Indicates valid read data is available. Read data remain stable until
rready signal is high.
■ 0: Read data not available
■ 1: Read data available
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-1 AXI Interface Signals (Continued)

Port Name I/O Description

rlast I AXI Read Last Data of the current burst

Indicates last transfer in read burst.
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

rready O AXI Data accept

Indicates that the Master is ready to accept write data.
■ 0: Master not ready
■ 1: Master ready
Exists: (DWC_MSHC_MST_IF_PRESENT==1) &&
(DWC_MSHC_MST_INTERFACE_TYPE==0)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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4.2 AHB Master Interface Signals

m_hclk - - m_haddr
m_hresetn - - m_hburst
m_hgrant - - m_hbusreq
m_hrdata - - m_hprot
m_hready - - m_hsize
m_hresp - - m_htrans
- m_hwdata
- m_hwrite

Table 4-2 AHB Master Interface Signals

Port Name I/O Description

m_hclk I AHB master clock.

Exists: (DWC_MSHC_MST_INTERFACE_TYPE==1)
Synchronous To: None
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: High; all signals sampled rising edge of clock

m_hresetn I AHB master reset.

Asynchronous assertion, synchronous de-assertion. The reset must
be synchronously de-asserted after rising edge of m_hclk.
DWC_mshc_x2h does not contain logic to perform this
synchronization, so it must be provided externally.
Exists: (DWC_MSHC_MST_INTERFACE_TYPE==1)
Synchronous To: Asynchronous
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: Low

m_hgrant I AHB bus grant. Asserted by arbiter to indicate that requesting master
has won ownership of bus.
Exists: (DWC_MSHC_MST_INTERFACE_TYPE==1) &&
(MSHC_MAHB_LITE==0)
Synchronous To: m_hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-2 AHB Master Interface Signals (Continued)

Port Name I/O Description

m_hrdata[(DWC_MSHC_MBIU_DW- I Transfer read data. Used to transfer data from bus slaves to bus
1):0] master during read operations.
Exists: (DWC_MSHC_MST_INTERFACE_TYPE==1)
Synchronous To: m_hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

m_hready I Ready response from selected slave. Indicates current transfer is

complete.
Exists: (DWC_MSHC_MST_INTERFACE_TYPE==1)
Synchronous To: m_hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

m_hresp[1:0] I Transfer response. Indicates response type from slave.

Exists: (DWC_MSHC_MST_INTERFACE_TYPE==1)
Synchronous To: m_hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

m_haddr[(DWC_MSHC_MBIU_AW-1):0] O AHB address bus.

Exists: (DWC_MSHC_MST_INTERFACE_TYPE==1)
Synchronous To: m_hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

m_hburst[2:0] O Transfer type. Indicates if transfer constitutes part of a burst.

Exists: (DWC_MSHC_MST_INTERFACE_TYPE==1)
Synchronous To: m_hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

m_hbusreq O Bus request signal. Asserted by master to request access to bus. In

AHB-Lite mode, this output is a constant, driven high.
Exists: (DWC_MSHC_MST_INTERFACE_TYPE==1) &&
(MSHC_MAHB_LITE==0)
Synchronous To: m_hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-2 AHB Master Interface Signals (Continued)

Port Name I/O Description

m_hprot[3:0] O Protection control.

Exists: (DWC_MSHC_MST_INTERFACE_TYPE==1)
Synchronous To: m_hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

m_hsize[2:0] O Transfer size. Indicates size of transfer.

Exists: (DWC_MSHC_MST_INTERFACE_TYPE==1)
Synchronous To: m_hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

m_htrans[1:0] O Transfer control. Indicates type of transfer being performed.

Exists: (DWC_MSHC_MST_INTERFACE_TYPE==1)
Synchronous To: m_hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

m_hwdata[(DWC_MSHC_MBIU_DW- O Transfer write data.

1):0] Exists: (DWC_MSHC_MST_INTERFACE_TYPE==1)
Synchronous To: m_hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

m_hwrite O Transfer write control. When HIGH, indicates write transfer. When
LOW, indicates read transfer.
Exists: (DWC_MSHC_MST_INTERFACE_TYPE==1)
Synchronous To: m_hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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4.3 AHB Slave Interface Signals

hclk - - hrdata
hresetn - - hresp
hsel - - hready_resp
haddr -
hsize -
htrans -
hwrite -
hready -
hwdata -

Table 4-3 AHB Slave Interface Signals

Port Name I/O Description

hclk I AHB Clock

Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: High

hresetn I AHB Asynchronous Reset

Asynchronous assertion and de-assertion synchronous to hclk
Exists: Always
Synchronous To: Asynchronous
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: Low

hsel I AHB Peripheral Select

Asserted when current transfer on the AHB bus is for the DWC_mshc
slave.
Exists: Always
Synchronous To: hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

haddr[(MSHC_S_ADDR_WIDTH-1):0] I AHB Address Bus.

Exists: Always
Synchronous To: hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-3 AHB Slave Interface Signals (Continued)

Port Name I/O Description

hsize[2:0] I AHB Transfer Size

Following sizes are supported by DWC_mshc:
■ 000 - 8 bits
■ 001 - 16 bits
■ 010 - 32 bits
Exists: Always
Synchronous To: hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

htrans[1:0] I AHB Transfer Type

■ 00 - IDLE
■ 01 - BUSY
■ 10 - NONSEQUENTIAL
■ 11 - SEQUENTIAL
Note: Transfer of type Busy and SEQUENTIAL is not supported by
DWC_mshc.
Exists: Always
Synchronous To: hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

hwrite I AHB Transfer Write Control

Asserted during write transfer and de-asserted during read transfer.
Exists: Always
Synchronous To: hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

hready I AHB Ready Response from selected slave

Indicates that the previous transfer is complete. This signal is passed
to all master and slaves.
Exists: Always
Synchronous To: hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-3 AHB Slave Interface Signals (Continued)

Port Name I/O Description

hwdata[(MSHC_S_DATA_WIDTH-1):0] I AHB Transfer Write Data.

Exists: Always
Synchronous To: hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

hrdata[(MSHC_S_DATA_WIDTH-1):0] O AHB Transfer Read Data.

Exists: Always
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-3 AHB Slave Interface Signals (Continued)

Port Name I/O Description

hresp[1:0] O AHB Transfer Response from DWC_mshc

Transfer response provides information about current transfer.
DWC_mshc supports three types of responses OKAY, ERROR and
RETRY.

■ OKAY:

- When transfer is completed successfully OKAY response is

returned.
- By default, when AHB master tries to access any register
beyond register map of DWC_mshc, OKAY response is
returned.
■ ERROR:

- Write to Command Queuing DoorBell register after requesting

HALT is ignored and ERROR response is returned.
- When cC parameter "DWC_MSHC_SLV_RESPONSE_TYPE"
is set,AHB slave error response is generated for nonexistent
register word access.

■ RETRY:

- Generated during ADMA3 command descriptor fetch and

there is a AHB slave write access at offset at 0x00-0x0F in
SD/eMMC mode or 0x80-0x9F in UHS-II mode
Write to register beyond register map is ignored and zero is returned
for read.
Exists: Always
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

hready_resp O AHB Transfer Ready Response from DWC_mshc When asserted,

indicates that the current transfer is complete.
Exists: Always
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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4.4 RAM Interface Signals

ram_data_in - - ram_cs_n
- ram_rw_n
- ram_addr
- ram_data_out

Table 4-4 RAM Interface Signals

Port Name I/O Description

ram_cs_n O SP RAM Chip Select

■ 0 - SPRAM is selected
■ 1 - SPRAM is not selected
Exists: Always
Synchronous To: bclk
Registered: DWC_MSHC_RAC_INT_PIPE_STAGE>=1 ? Yes : No
Power Domain: SINGLE_DOMAIN
Active State: Low

ram_rw_n O SP RAM Read/Write Control

■ 0 - Write enable
■ 1 - Read enable
Exists: Always
Synchronous To: bclk
Registered: DWC_MSHC_RAC_INT_PIPE_STAGE>=1 ? Yes : No
Power Domain: SINGLE_DOMAIN
Active State: Low

ram_addr[(DWC_MSHC_BADDRW-1):0] O SP RAM Address

Exists: Always
Synchronous To: bclk
Registered: DWC_MSHC_RAC_INT_PIPE_STAGE>=1 ? Yes : No
Power Domain: SINGLE_DOMAIN
Active State: High

ram_data_in[(DWC_MSHC_MBIU_DW- I SP RAM Data Input

1):0] Exists: Always
Synchronous To: bclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-4 RAM Interface Signals (Continued)

Port Name I/O Description

ram_data_out[(DWC_MSHC_MBIU_DW O SP RAM Data Output

-1):0] Exists: Always
Synchronous To: bclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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4.5 SD/eMMC Card Interface Signals

cclk_tx - - sd_cmd_out
cclk_rx - - sd_cmd_out_en
cresetn_tx - - sd_dat_out
cresetn_rx - - sd_dat_out_en
sd_cmd_in - - sd_rst_n
sd_dat_in - - sd_rst_n_oe
sd_dat_stb - - sd_datxfer_width

Table 4-5 SD/eMMC Card Interface Signals

Port Name I/O Description

cclk_tx I SD/eMMC Card transmit clock

Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: None
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: High

cclk_rx I SD/eMMC Card receive clock

Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: None
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: High

cresetn_tx I SD/eMMC Card Interface Reset for cclk_tx clock domain

Asynchronous assertion and de-assertion synchronous to cclk_tx
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: Asynchronous
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: Low

cresetn_rx I SD/eMMC Card Interface Reset for cclk_rx clock domain

Asynchronous assertion and de-assertion synchronous to cclk_rx
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: Asynchronous
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: Low

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Table 4-5 SD/eMMC Card Interface Signals (Continued)

Port Name I/O Description

sd_cmd_in I SD/eMMC Card Command Input

Sampled by cclk_rx.
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: cclk_rx
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

sd_cmd_out O SD/eMMC Card Command Output

Driven out by cclk_tx.
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: cclk_tx
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

sd_cmd_out_en O SD/eMMC Card Command Output Enable

Driven out by cclk_tx.
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: cclk_tx
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

sd_dat_in[(SD_DAT_WIDTH-1):0] I SD/eMMC Card Data input

Sampled by cclk_rx. All data line must be pulled high, even if they are
not used.
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: cclk_rx
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

sd_dat_out[(SD_DAT_WIDTH-1):0] O SD/eMMC Card Data Output

Driven out by cclk_tx.
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: cclk_tx
Registered: DWC_MSHC_DDR50_SUPPORT==1 ? No : Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-5 SD/eMMC Card Interface Signals (Continued)

Port Name I/O Description

sd_dat_out_en[(SD_DAT_WIDTH-1):0] O SD/eMMC Card Data Output Enable

Driven out by cclk_tx.One output enable control bit for each
sd_dat_out bit.
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: cclk_tx
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

sd_dat_stb I eMMC data strobe signal.

Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==3 ||
DWC_MSHC_CARD_INTERFACE_TYPE==4 ||
DWC_MSHC_CARD_INTERFACE_TYPE==5) &&
(DWC_MSHC_EMMC_DATASTROBE_EN==1)
Synchronous To: Asynchronous
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

sd_rst_n O eMMC device reset signal.

Exists: (DWC_MSHC_CARD_INTERFACE_TYPE > 2)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: Low

sd_rst_n_oe O Output enable control for eMMC device reset signal PAD.
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE > 2)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: Low

sd_datxfer_width[1:0] O Active SD/eMMC data bus width

This two-bit output reflects the current active data width on
SD/eMMC data bus.
■ 00 : 1-bit data width
■ 01 : 4-bit data width
■ 1X : 8-bit data width
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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4.6 Auto-Tuning Interface Signals

drift_cclk_rx - - autotuning_cclk_sel
cresetn_drx - - autotuning_cclk_sel_update

Table 4-6 Auto-Tuning Interface Signals

Port Name I/O Description

drift_cclk_rx I SD/eMMC Card receive clock used for Auto-tuning.

Exists: (DWC_MSHC_RETUNE_MODE==1) &&
(DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: None
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: High

cresetn_drx I SD/eMMC Card Interface Reset for drift_cclk_rx clock domain.

Exists: (DWC_MSHC_RETUNE_MODE==1) &&
(DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: Asynchronous
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: Low

autotuning_cclk_sel[(DWC_MSHC_DL_ O Selects the Left/Right Edge phase of sampling clock for Auto-tuning.
CW-1):0] This signal must be used as:
■ A "Mux-select" to the clock muxtiplixer that selects different
phases of drift_cclk_rx, or
■ A delay control code to the delay line that changes drift_cclk_rx
phase.
The value is decided by the auto-tuning engine.
Exists: (DWC_MSHC_RETUNE_MODE==1) &&
(DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: cclk_tx
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-6 Auto-Tuning Interface Signals (Continued)

Port Name I/O Description

autotuning_cclk_sel_update O Stroble pulse that indicates change in Auto-tuning_cclk_sel value.

This signal can be used for synchronization purpose or as a delay
control code update signal.
Exists: (DWC_MSHC_RETUNE_MODE==1) &&
(DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: cclk_tx
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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4.7 UHS-II Card Interface Signals

pclk - - uhs2_mode
presetn - - uhs2_ct
uhs2_rdm - - uhs2_tdm
uhs2_rd - - uhs2_td
uhs2_rdtm - - uhs2_tdrm
uhs2_rdt - - uhs2_tdr
uhs2_st -

Table 4-7 UHS-II Card Interface Signals

Port Name I/O Description

pclk I UHS-II Link/PHY interface clock

Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: None
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: High

presetn I UHS-II interface reset

Asynchronous assertion and de-assertion synchronous to pclk
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: Asynchronous
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: Low

uhs2_mode O UHS-II PHY power mode

■ 0 - Dormant state
■ 1 - Non dormant state
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: pclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-7 UHS-II Card Interface Signals (Continued)

Port Name I/O Description

uhs2_rdm[(MSHC_UHS2_PHY_LINK_W I UHS-II Receive Data Coding mode

IDTH_BYTES-1):0] High represents uhs2_rd carries K-Symbol and low represents
uhs2_rd carries D-Symbol for each byte received on uhs2_rd. When
UHS-II PHY-LINK interface width is configured to 16, uhs2_rd signal
is of 16 bits and uhs2_rdm signal is of 2 bits. In this case,
uhs2_rdm[0] corresponds to uhs2_rd[7:0] and uhs2_rdm[1]
corresponds to uhs2_rd[15:8].
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: pclk
Registered: DWC_MSHC_PHY_LINK_WIDTH==0 ? Yes : No
Power Domain: SINGLE_DOMAIN
Active State: High

uhs2_rd[(((DWC_MSHC_PHY_LINK_WI I UHS-II Receive Data of Receive Lane D1.

DTH==0)?8:16)-1):0] Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: pclk
Registered: DWC_MSHC_PHY_LINK_WIDTH==0 ? Yes : No
Power Domain: SINGLE_DOMAIN
Active State: High

uhs2_rdtm[(MSHC_UHS2_PHY_LINK_ I UHS-II Receive Coding Mode of Transmit Lane

WIDTH_BYTES-1):0] High represents uhs2_rdt carries K-Symbol and low represents
uhs2_rdt carries D-Symbol for each byte received on uhs2_rdt. When
UHS-II PHY-LINK interface width is configured to 16, uhs2_rdt signal
is of 16 bits and uhs2_rdtm signal is of 2 bits. In this case,
uhs2_rdtm[0] corresponds to uhs2_rdt[7:0] and uhs2_rdtm[1]
corresponds to uhs2_rdt[15:8].
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: pclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-7 UHS-II Card Interface Signals (Continued)

Port Name I/O Description

uhs2_rdt[(((DWC_MSHC_PHY_LINK_W I UHS-II Receive Data of Transmit Lane D0.

IDTH==0)?8:16)-1):0] Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: pclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

uhs2_st[7:0] I UHS-II PHY Status

The meaning for each bit field is explained as follows:
[0] Amplitude Detector Output
[1] PLL lock (high active)
[2] PHY command acknowledge (high active)
[3] PHY Receive Error Status
■ [5:4] uhs2_rd status
- 00: EIDL
- 01: OFF
- 10: STB
- 11: VLD
■ [7:6] uhs2_rdt status
- 00: EIDL
- 01: OFF
- 10: STB
- 11: VLD

Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: pclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-7 UHS-II Card Interface Signals (Continued)

Port Name I/O Description

uhs2_ct[7:0] O UHS-II PHY Control

The meaning for each bit field is explained as follows:
[3:0]
■ (uhs2_mode=0) PHY initialization parameter
- [1:0] PHY Major Revision
- [3:2] Transmission speed range
The values for the transmission speed range are as follows:
00: Range A
01: Range B
Others: Reserved
■ (uhs2_mode=1) PHY command
- 0000: No command
- 0101: Enter to (2L-) HDIN mode
- 0110: Enter to (2L-) HDOUT mode
- 0111: Exit from (2L-) HD mode
- Others: Reserved
[5:4] uhs2_td status
■ 00: EIDL
■ 01: OFF
■ 10: STB
■ 11: VLD
[7:6] uhs2_tdr status
■ 00: EIDL
■ 01: OFF
■ 10: STB
■ 11: VLD
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: pclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-7 UHS-II Card Interface Signals (Continued)

Port Name I/O Description

uhs2_tdm[(MSHC_UHS2_PHY_LINK_W O UHS-II Transmit Coding Mode

IDTH_BYTES-1):0] High represents uhs2_td carries K-Symbol and low represents
uhs2_td carries D-Symbol for each byte transmitted on uhs2_td.
When UHS-II PHY-LINK interface width is configured to 16, uhs2_td
signal is of 16 bits and uhs2_tdm signal is of 2 bits. In this case,
uhs2_tdm[0] corresponds to uhs2_td[7:0] and uhs2_tdm[1]
corresponds to uhs2_td[15:8].
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: pclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

uhs2_td[(((DWC_MSHC_PHY_LINK_WI O UHS-II Transmit Data of Transmit Lane D0.

DTH==0)?8:16)-1):0] Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: pclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

uhs2_tdrm[(MSHC_UHS2_PHY_LINK_ O UHS-II Transmit Coding Mode of Receive Lane

WIDTH_BYTES-1):0] High represents uhs2_tdr carries K-Symbol and low represents
uhs2_tdr carries D-Symbol for each byte transmitted on uhs2_tdr.
When UHS-II PHY-LINK interface width is configured to 16, uhs2_tdr
signal is of 16 bits and uhs2_tdrm signal is of 2 bits. In this case,
uhs2_tdrm[0] corresponds to uhs2_tdr[7:0] and uhs2_tdrm[1]
corresponds to uhs2_tdr[15:8].
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: pclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-7 UHS-II Card Interface Signals (Continued)

Port Name I/O Description

uhs2_tdr[(((DWC_MSHC_PHY_LINK_W O UHS-II Transmit Data of Receive Lane D1.

IDTH==0)?8:16)-1):0] Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: pclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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4.8 Card Clock Control Signals

card_clk_stable - - clk2card_on
int_bclk_stable - - tuning_cclk_sel
int_aclk_stable - - tuning_cclk_sel_update
int_tmclk_stable - - sample_cclk_sel
- card_clk_gen_sel
- card_clk_freq_sel
- uhs2_spd_range
- card_clk_en
- intclk_en

Table 4-8 Card Clock Control Signals

Port Name I/O Description

clk2card_on O Control to switch on clock supplied to the card.

In SD/eMMC mode, this signal is used to enable the SDCLK and in
UHS-II mode, this signal is used to enable RCLK.
Exists: Always
Synchronous To: DWC_MSHC_CARD_INTERFACE_TYPE==2 ?
"hclk" : "cclk_tx"
Registered: DWC_MSHC_CARD_INTERFACE_TYPE==2 ? Yes :
No
Power Domain: SINGLE_DOMAIN
Active State: High

tuning_cclk_sel[(DWC_MSHC_DL_CW- O Selects the appropriate tuned (phase shifted) clock to receive the
1):0] data.
This signal should be used as:
■ A "Mux-select" to the clock muxtiplexer that selects different
phases of cclk_rx, or
■ A delay control code to the delay line that changes cclk_rx phase.
The value is decided after execution of tuning sequence and it is
used to select the phase of cclk_rx clock.
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!=2) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Synchronous To: cclk_tx
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-8 Card Clock Control Signals (Continued)

Port Name I/O Description

tuning_cclk_sel_update O Stroble pulse that indicates change in tuning_cclk_sel value.

This signal can be used for Synchronization purpose or as a delay
control code update signal.
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!=2) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Synchronous To: cclk_tx
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

sample_cclk_sel O Select sampling clock to receive CMD and DAT for UHS-I Tuned
clock (phase shifted) or fixed clock
■ 1 - Tuned clock is used to sample the data
■ 0 - Fixed clock is used to sample the data
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!=2) &&
(DWC_MSHC_LS_NO_PHY_MODE==0)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

card_clk_gen_sel O Select clock generator mode

■ 1 - Programmable clock mode
■ 0 - Divided clock mode
Exists: Always
Synchronous To: hclk
Registered: Ye
Power Domain: SINGLE_DOMAIN
Active State: High

card_clk_freq_sel[9:0] O Select frequency of SDCLK/RCLK

This is used to select the frequency of card clock, that is
SDCLK/RCLK. The value depends on the required frequency for
desired card clock and clock generator mode. Refer Section 5.2.3
"Connecting Clock I/O interface" in DWC_mshc User Guide.
Exists: Always
Synchronous To: hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-8 Card Clock Control Signals (Continued)

Port Name I/O Description

uhs2_spd_range[1:0] O Speed range programmed in host controller for UHS-II

The PLL multiplier for bit clock (for UHS-II PHY) and pclk generation
is selected by this field. Change of this value is not effective
immediately and is applied from exiting Dormant state. This is
applicable only for UHS-II.
■ 00 - Range A
■ 01 - Range B
■ Others - Reserved
Refer Section "Connecting Clock I/O interface" in DWC_mshc User
Guide.
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: bclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

card_clk_en O This signal is used to enable dedicated card clock PLL (if used in
Host system design)
Exists: Always
Synchronous To: hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

card_clk_stable I When asserted it indicates that the card clock is stable

This signal represents stability of SDCLK/PCLK generated by host
system clock source (PLL).
Exists: Always
Synchronous To: Asynchronous
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

intclk_en O Internal clock enable

This is enable for internal clock (aclk, bclk) of host controller. When
this is low, aclk and bclk can be stopped.
Exists: Always
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-8 Card Clock Control Signals (Continued)

Port Name I/O Description

int_bclk_stable I Internal bclk stable

Indicate stability of internal clock - bclk. This input shall be tied to 1, if
bclk is not gated as per intclk_en control.
Exists: Always
Synchronous To: Asynchronous
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

int_aclk_stable I Internal aclk stable

Indicates stability of internal clock - aclk. This input shall be tied to 1,
if aclk is not gated as per intclk_en control.
Exists: Always
Synchronous To: Asynchronous
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

int_tmclk_stable I Internal tmclk stable

Indicate stability of internal clock - tmclk. This input shall be tied to 1,
if tmclk is not gated as per intclk_en control.
Exists: Always
Synchronous To: Asynchronous
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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4.9 Card Bus Power Control Interface Signals

host_reg_vol_stable - - sd_vdd1_sel
- sd_vdd2_sel
- sd_vdd1_on
- sd_vdd2_on

Table 4-9 Card Bus Power Control Interface Signals

Port Name I/O Description

sd_vdd1_sel[2:0] O Select VDD1 voltage level for SD card

■ 111b - 3.3V
■ 110b - 3.0V
■ 101b - 1.8V
■ 100b-000b - Reserved
Exists: Always
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

sd_vdd2_sel[2:0] O Select VDD2 voltage level for UHS-II card

■ 101b - 1.8V
■ 000b - VDD2 not supported
■ others - Reserved
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-9 Card Bus Power Control Interface Signals (Continued)

Port Name I/O Description

sd_vdd1_on O Switch on VDD1/VDD bus power for SD/eMMC card

Exists: Always
Synchronous To: hclk
Registered: (DWC_MSHC_CARD_INTERFACE_TYPE == 0 ||
DWC_MSHC_CARD_INTERFACE_TYPE == 1 ||
DWC_MSHC_CARD_INTERFACE_TYPE == 3 ||
DWC_MSHC_CARD_INTERFACE_TYPE == 4 ||
DWC_MSHC_CARD_INTERFACE_TYPE == 5) ? No : Yes
Power Domain: SINGLE_DOMAIN
Active State: High

sd_vdd2_on O Switch on VDD2 bus power (UHS-II only)

Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

host_reg_vol_stable I Check whether host regulator voltage is stable

Exists: Always
Synchronous To: Asynchronous
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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4.10 Misc Signals Interface

bclk - - intr
bresetn - - wakeup_intr
tmclk - - uhs2_if_en
tresetn - - uhs1_drv_sth
cqetmclk - - uhs1_swvolt_en
cqetresetn - - gp_out
card_detect_n - - led_control
card_write_prot -
gp_in -
test_scan_mode -

Table 4-10 Misc Signals Interface

Port Name I/O Description

bclk I Core base clock

Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: High

bresetn I Core base clock reset

Asynchronous assertion and de-assertion synchronous to bclk
Exists: Always
Synchronous To: Asynchronous
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: Low

tmclk I Timer clock

Exists: Always
Synchronous To: None
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: High

tresetn I Timer reset

Asynchronous assertion and de-assertion synchronous to tmclk
Exists: Always
Synchronous To: Asynchronous
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: Low

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Table 4-10 Misc Signals Interface (Continued)

Port Name I/O Description

cqetmclk I CQE Timer clock

Exists: (DWC_MSHC_EMMC_CQE_EN==1)
Synchronous To: None
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: High

cqetresetn I CQE Timer reset

Asynchronous assertion and de-assertion synchronous to cqetmclk
Exists: (DWC_MSHC_EMMC_CQE_EN==1)
Synchronous To: Asynchronous
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: Low

card_detect_n I Card Detect Signal

When this is 0, it represents card is connected.
When this signal goes from 0 to 1 card insertion interrupt is
generated if enabled.
Note: This signal should be connected to ground if an eMMC device
is connected to DWC_mshc. As eMMC device is non-removable,
card detection is not required.
Exists: Always
Synchronous To: Asynchronous
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: Low

card_write_prot I SD Card Write Protect Signal. When this is 0, it represents card is

write protected.
Note: This signal is only applicable for SD card and has to be driven
directly from write protect physical switch of SD card socket; however
for eMMC device, this is don't care and should be tied HIGH to
comply with SDHCI since eMMC device does not have write protect
physical switch similar to SD card.
Exists: Always
Synchronous To: Asynchronous
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-10 Misc Signals Interface (Continued)

Port Name I/O Description

intr O Host controller interrupt

Exists: Always
Synchronous To: hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

wakeup_intr O Interrupt for wakeup

Exists: Always
Synchronous To: hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

uhs2_if_en O UHS-II interface select output

■ 1 - UHS-II Interface Enabled
■ 0 - SD/eMMC Interface Enabled
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE==0 ||
DWC_MSHC_CARD_INTERFACE_TYPE==2 ||
DWC_MSHC_CARD_INTERFACE_TYPE==3)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

uhs1_drv_sth[1:0] O UHS-I driver strength select

Host controller output driver in 1.8V signaling is selected by this
output. In 3.3V signaling, this output is not effective.
■ 00 - Driver Type B (Default)
■ 01 - Driver Type A
■ 10 - Driver Type C
■ 11 - Driver Type D

Note: This output can also be used in eMMC mode. eMMC defines
five type of driver strengths namely Type0, Type1, Type2, Type3 and
Type4. Any of the four driver strengths can be mapped to this output.
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-10 Misc Signals Interface (Continued)

Port Name I/O Description

uhs1_swvolt_en O Change signal voltage from 3.3V to 1.8V for UHS-I

This signal controls the external voltage regulator for I/O cell. When
high, the switching voltage changes from 3.3V to 1.8V.
■ 1 - 1.8V Signaling
■ 0 - 3.3V Signaling

Note: This output can also be used in eMMC mode while switching
from 3.0V to 1.8V.
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!=2)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

gp_in[(DWC_MSHC_NUM_GP_IN-1):0] I General Purpose input port

Exists: (DWC_MSHC_GPIO_ENABLE==1)
Synchronous To: hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

gp_out[(DWC_MSHC_NUM_GP_OUT- O General Purpose output port

1):0] Exists: (DWC_MSHC_GPIO_ENABLE==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

test_scan_mode I Control signal for DFT mode

This signal is the scan mode bypass pin used for DFT purposes. This
signal should be tied low during normal operation.
Exists: (DWC_MSHC_POSEDGE_SCAN_CLK==1) ||
(DWC_MSHC_ANY_CLK_GATE==1) ||
(DWC_MSHC_EMMC_DATASTROBE_EN==1) ||
(DWC_MSHC_SDEMMC_PHY_REGS==1) ||
(DWC_MSHC_LS_NO_PHY_MODE==1 &&
DWC_MSHC_EMMC_DATASTROBE_EN==0)
Synchronous To: hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-10 Misc Signals Interface (Continued)

Port Name I/O Description

led_control O Warn user not to remove card while it is being accessed

Exists: Always
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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4.11 SD/eMMC PHY Interface Signals

phy_powergood - - phy_resetb
pdtst_y - - phy_pad_sp
dll_locked - - phy_pad_sn
dll_lock_error - - cpd_rxsel
dll_dbg_mstlockcode - - cpd_pu
dll_dbg_slvlockcode - - cpd_pd
- cpd_txpren
- cpd_txprep
- dpd_rxsel
- dpd_pu
- dpd_pd
- dpd_txpren
- dpd_txprep
- ckpd_rxsel
- ckpd_pu
- ckpd_pd
- ckpd_txpren
- ckpd_txprep
- spd_rxsel
- spd_pu
- spd_pd
- spd_txpren
- spd_txprep
- rpd_rxsel
- rpd_pu
- rpd_pd
- rpd_txpren
- rpd_txprep
- pdtst_mode
- pdtst_oe
- pdtst_a
- phy_dl_step
- phy_dlout_en
- phy_tune_dly
- cckdl_extdlyen
- cckdl_config
- cckdl_bypassen
- cckdl_dc_update
- cckdl_dc
- smpdl_extdlyen
- smpdl_config
- smpdl_override
- smpdl_bypassen
- atdl_extdlyen
- atdl_config
- atdl_bypassen
- dllslv_update_dly
- dll_waitcycle
- dll_jumpstep
- dllmst_extdlyen
- dllmst_config
- dllmst_bypassen
- dllslv_extdlyen
- dllslv_config
- dllslv_bypassen
- dllslv_swdc_update
- dll_offset
- dll_en

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- dll_offseten
- dllmst_test_dc
- dll_lbt_loadval
- dll_update_windw
- hs400_lpbk_en

Table 4-11 SD/eMMC PHY Interface Signals

Port Name I/O Description

phy_resetb O SD/eMMC PHY reset

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: Low

phy_pad_sp[3:0] O Output buffer PMOS strength control for SD/eMMC PHY PADs
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

phy_pad_sn[3:0] O Output buffer NMOS strength control for SD/eMMC PHY PADs
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

phy_powergood I SD/eMMC PHY powergood status

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: Asynchronous
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

cpd_rxsel[2:0] O SD/eMMC PHY Command Pad's receiver select control

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-11 SD/eMMC PHY Interface Signals (Continued)

Port Name I/O Description

cpd_pu O SD/eMMC PHY Command Pad's pullup enable control

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

cpd_pd O SD/eMMC PHY Command Pad's pull down control

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

cpd_txpren[3:0] O SD/eMMC PHY Command Pad's TX Slew control NMOS

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

cpd_txprep[3:0] O SD/eMMC PHY Command Pad's TX Slew control PMOS

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dpd_rxsel[2:0] O SD/eMMC PHY Data Pad's receiver select control. Common for all
PADs used for data
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dpd_pu O SD/eMMC PHY Data Pad's pullup enable control.Common for all
PADs used for data
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-11 SD/eMMC PHY Interface Signals (Continued)

Port Name I/O Description

dpd_pd O SD/eMMC PHY Data Pad's pull down control.Common for all PADs
used for data
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dpd_txpren[3:0] O SD/eMMC PHY Data Pad's TX Slew control NMOS.Common for all
PADs used for data
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dpd_txprep[3:0] O SD/eMMC PHY Data Pad's TX Slew control PMOS. Common for all
PADs used for data
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

ckpd_rxsel[2:0] O SD/eMMC PHY Device clock Pad's receiver select control

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

ckpd_pu O SD/eMMC PHY Device clock Pad's pullup enable control

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

ckpd_pd O SD/eMMC PHY Device clock Pad's pull down control

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-11 SD/eMMC PHY Interface Signals (Continued)

Port Name I/O Description

ckpd_txpren[3:0] O SD/eMMC PHY Device clock Pad's TX Slew control NMOS

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

ckpd_txprep[3:0] O SD/eMMC PHY Device clock Pad's TX Slew control PMOS

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

spd_rxsel[2:0] O SD/eMMC PHY Device Strobe Pad's receiver select control

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

spd_pu O SD/eMMC PHY Device Strobe Pad's pullup enable control

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

spd_pd O SD/eMMC PHY Device Strobe Pad's pull down control

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

spd_txpren[3:0] O SD/eMMC PHY Device Strobe Pad's TX Slew control NMOS

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-11 SD/eMMC PHY Interface Signals (Continued)

Port Name I/O Description

spd_txprep[3:0] O SD/eMMC PHY Device Strobe Pad's TX Slew control PMOS

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

rpd_rxsel[2:0] O SD/eMMC PHY GPIO Pad's receiver select control. Common for all
PADs used for all GPIOs
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

rpd_pu O SD/eMMC PHY GPIO Pad's pullup enable control.Common for all
PADs used for all GPIOs
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

rpd_pd O SD/eMMC PHY GPIO Pad's pull down control.Common for all PADs
used for all GPIOs
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

rpd_txpren[3:0] O SD/eMMC PHY GPIO Pad's TX Slew control NMOS.Common for all
PADs used for all GPIOs
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-11 SD/eMMC PHY Interface Signals (Continued)

Port Name I/O Description

rpd_txprep[3:0] O SD/eMMC PHY GPIO Pad's TX Slew control PMOS. Common for all
PADs used for all GPIOs
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

pdtst_mode O Connect to PAD's test_mode control.This is common for all PADs of

SD/eMMC PHY
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

pdtst_oe[(MSHC_SDEMMCPHY_NUMP O SD/eMMC PHY PAD test mode output enable

ADS-1):0] Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

pdtst_a[(MSHC_SDEMMCPHY_NUMPA O SD/eMMC PHY PAD test mode PAD Input. Connects to test mode ia
DS-1):0] of PAD
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

pdtst_y[(MSHC_SDEMMCPHY_NUMPA I SD/eMMC PHY PAD test mode pad output. Conncts to test mode oy
DS-1):0] of PAD
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: Asynchronous
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

phy_dl_step O SD/eMMC PHY delay line step size control

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-11 SD/eMMC PHY Interface Signals (Continued)

Port Name I/O Description

phy_dlout_en O SD/eMMC PHY delay line output debug path enable

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

phy_tune_dly[1:0] O SD/eMMC PHY pulse stretch delay control

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

cckdl_extdlyen O SD/eMMC PHY Fixed Delay Enable. This signal enables additional
fixed delay equivalent of 128 stages for card clock delayline.
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

cckdl_config[1:0] O SD/eMMC PHY's card clock delay Line input source control
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

cckdl_bypassen O SD/eMMC PHY's card clock delay Line bypass control.

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

cckdl_dc_update O SD/eMMC PHY's card clock delay Line output disable control. When
'1' it shuts off output of delay line and prepared it for code update.
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-11 SD/eMMC PHY Interface Signals (Continued)

Port Name I/O Description

cckdl_dc[6:0] O SD/eMMC PHY's card clock delay line's delay code

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

smpdl_extdlyen O SD/eMMC PHY Fixed Delay Enable. This signal enables additional
fixed delay equivalent of 128 stages for sampling clock delayline.
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

smpdl_config[1:0] O SD/eMMC PHY's sampling clock delay Line input source control
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

smpdl_override O SD/eMMC PHY's sampling clock delay Line config SW override

signal.
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

smpdl_bypassen O SD/eMMC PHY's sampling clock delay Line bypass control.

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

atdl_extdlyen O SD/eMMC PHY Fixed Delay Enable. This signal enables additional
fixed delay equivalent of 128 stages for autotuning clock delayline.
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-11 SD/eMMC PHY Interface Signals (Continued)

Port Name I/O Description

atdl_config[1:0] O SD/eMMC PHY's Autotuning clock delay Line input source control
Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

atdl_bypassen O SD/eMMC PHY's Autotuning clock delay Line bypass control.

Exists: (DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dllslv_update_dly[1:0] O controls the duration DLL slave delayline's output are cut-off during
code update
Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dll_waitcycle[2:0] O specifies the number of clock cycles DLL logic has to wait before
sensing lead/lag output from phase detector
Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dll_jumpstep[6:0] O controls initial jump cycle length of the DLL.

Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-11 SD/eMMC PHY Interface Signals (Continued)

Port Name I/O Description

dllmst_extdlyen O SD/eMMC PHY DLL Master Fixed Delay Enable. This signal enables
additional fixed delay equivalent of 128 stages
Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dllmst_config[1:0] O SD/eMMC PHY's DLL Master delay Line input source control
Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dllmst_bypassen O SD/eMMC PHY's DLL Master delay Line bypass control.

Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dllslv_extdlyen O SD/eMMC PHY DLL Slave Fixed Delay Enable. This signal enables
additional fixed delay equivalent of 128 stages
Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dllslv_config[1:0] O SD/eMMC PHY's DLL Slave delay Line input source control
Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-11 SD/eMMC PHY Interface Signals (Continued)

Port Name I/O Description

dllslv_bypassen O SD/eMMC PHY's DLL Slave delay Line bypass control.

Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dllslv_swdc_update O SD/eMMC PHY's DLL Slave's SW controlled delay code update

signal.
Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dll_offset[6:0] O Sets the value of DLL's offset input

Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dll_en O DLL enable control

Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: cclk_tx
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dll_offseten O qualifes dll_offset output when '1'

Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: cclk_tx
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-11 SD/eMMC PHY Interface Signals (Continued)

Port Name I/O Description

dllmst_test_dc[6:0] O Sets the value of DLL's master test code input when dll is disabled
Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: cclk_tx
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dll_lbt_loadval[15:0] O Sets the value of DLL's olbt_loadval input. Controls the lbt timer's
timeout value at which DLL runs a revalidation cycle.
Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: hclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dll_update_windw O DLL update window status, DLL updates slave code when this signal
is 1.
Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: cclk_tx
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

dll_locked I DLL's lock status

Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: cclk_tx
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dll_lock_error I DLL's lock error status

Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: cclk_tx
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-11 SD/eMMC PHY Interface Signals (Continued)

Port Name I/O Description

dll_dbg_mstlockcode[6:0] I DLL's Master Delay line lock code for debug purpose
Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: cclk_tx
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

dll_dbg_slvlockcode[6:0] I DLL's Slave Delay line lock code for debug purpose
Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1)
Synchronous To: cclk_tx
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

hs400_lpbk_en O This signal indicates if the loopback is enabled in HS400 mode

Exists: (DWC_MSHC_EMMC_DATASTROBE_EN==1) &&
(DWC_MSHC_SDEMMC_PHY_REGS==1) &&
(DWC_MSHC_SDEMMC_PHY_DFT==1)
Synchronous To: cclk_tx
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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4.12 Debug Sideband Interface Signals

- dbg_aw_task_id
- dbg_aw_pyld_descr
- dbg_w_task_id
- dbg_w_pyld_descr
- dbg_ar_task_id
- dbg_ar_pyld_descr

Table 4-12 Debug Sideband Interface Signals

Port Name I/O Description

dbg_aw_task_id[(DWC_SIDEBAND_TA O Sideband TaskID debug signals Write address channel Signal

SKID_W-1):0] reflects the task id of the current write transaction in CQE mode.
Driven based on the task ID programmed for the current transfer.
When CQE Mode is not programmed i.e. CQCFG[CQ_EN] is 0, this
will be driven to 0 always.
Exists: (DWC_MSHC_DEBUG_SIDEBAND_EN==1)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dbg_aw_pyld_descr O Sideband Desc payload debug signals Write address channel 1:

Payload Write :: Data that is got from emmc card 0: All other cases
Exists: (DWC_MSHC_DEBUG_SIDEBAND_EN==1)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dbg_w_task_id[(DWC_SIDEBAND_TAS O Sideband TaskID debug signals Write data channel Signal reflects
KID_W-1):0] the task id of the current write transaction in CQE mode. Driven
based on the task ID programmed for the current transfer. When
CQE Mode is not programmed i.e. CQCFG[CQ_EN] is 0, this will be
driven to 0 always.
Exists: (DWC_MSHC_DEBUG_SIDEBAND_EN==1)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-12 Debug Sideband Interface Signals (Continued)

Port Name I/O Description

dbg_w_pyld_descr O Sideband Desc payload debug signals Write data channel 1: Payload
Write :: Data that is got from emmc card 0: All other cases
Exists: (DWC_MSHC_DEBUG_SIDEBAND_EN==1)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dbg_ar_task_id[(DWC_SIDEBAND_TAS O Sideband TaskID debug signals Read address channel Signal

KID_W-1):0] reflects the task id of the current read transaction in CQE mode.
Driven based on the task ID programmed for the current transfer.
When CQE Mode is not programmed i.e. CQCFG[CQ_EN] is 0, this
will be driven to 0 always.
Exists: (DWC_MSHC_DEBUG_SIDEBAND_EN==1)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

dbg_ar_pyld_descr O Sideband Desc payload debug signals Read address channel 1:

Payload Read :: Data that will be stored to emmc card 0: Descriptor
Read :: Data that will be used by emmc controller
Exists: (DWC_MSHC_DEBUG_SIDEBAND_EN==1)
Synchronous To: aclk
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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4.13 JTAG Interface Signals

jtagif_sel - - tdo
tck - - tdo_en
trstn -
tms -
tdi -

Table 4-13 JTAG Interface Signals

Port Name I/O Description

jtagif_sel I Input to select the active register access interface

■ 0 - AHB I/F can access MSHC registers
■ 1 - JTAG I/F access to MSHC registers are enabled
Note: System designer must ensure that this input is driven to 0 in
functional mode.
Exists: (DWC_MSHC_JTAGIF_EN==1)
Synchronous To: Asynchronous
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

tck I JTAG Interfce clock.

Exists: (DWC_MSHC_JTAGIF_EN==1)
Synchronous To: None
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: High; all signals sampled rising edge of clock

trstn I JTAG Interface Reset

Asynchronous assertion and de-assertion synchronous to tck
Exists: (DWC_MSHC_JTAGIF_EN==1)
Synchronous To: Asynchronous
Registered: N/A
Power Domain: SINGLE_DOMAIN
Active State: Low

tms I JTAG Interface Test Mode select

Note: Aligned to negative edge of tck
Exists: (DWC_MSHC_JTAGIF_EN==1)
Synchronous To: tck
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

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Table 4-13 JTAG Interface Signals (Continued)

Port Name I/O Description

tdi I JTAG Interface Test Data In

Note: Aligned to negative edge of tck
Exists: (DWC_MSHC_JTAGIF_EN==1)
Synchronous To: tck
Registered: No
Power Domain: SINGLE_DOMAIN
Active State: High

tdo O JTAG Interface Test Data Out

Note: Aligned to negative edge of tck
Exists: (DWC_MSHC_JTAGIF_EN==1)
Synchronous To: tck
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

tdo_en O JTAG Interface Test Data Out Enable

Note: Aligned to negative edge of tck
Exists: (DWC_MSHC_JTAGIF_EN==1)
Synchronous To: tck
Registered: Yes
Power Domain: SINGLE_DOMAIN
Active State: High

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5
Register Descriptions
This chapter details all possible registers in the IP. They are arranged hierarchically into maps and blocks
(banks).Your actual configuration might not contain all of these registers.
Attention: For configurable IP titles, do not use this document to determine the exact attributes of your
register map. It is for reference purposes only.
When you configure the controller in coreConsultant, you must access the register attributes for your actual
configuration at workspace/report/ComponentRegisters.html or
workspace/report/ComponentRegisters.xml after you have completed the report creation activity. That
report comes from the exact same source as this chapter but removes all the registers that are not in your
actual configuration. This does not apply to non-configurable IP titles. In addition, all parameter
expressions are evaluated to actual values. Therefore, the Offset and Memory Access values might change
depending on your actual configuration.
Some expressions might refer to TCL functions or procedures (sometimes identified as <functionof>) that
coreConsultant uses to make calculations. The exact formula used by these TCL functions is not provided in
this chapter. However, when you configure the controller in coreConsultant, all TCL functions and
parameters are evaluated completely; and the resulting values are displayed where appropriate in the
coreConsultant GUI reports.
Exists Expressions
These expressions indicate the combination of configuration parameters required for a register, field, or
block to exist in the memory map. The expression is only valid in the local context and does not indicate the
conditions for existence of the parent. For example, the expression for a bit field in a register assumes that
the register exists and does not include the conditions for existence of the register.
Offset
The term Offset is synonymous with Address.
Memory Access Attributes
The Memory Access attribute is defined as <ReadBehavior>/<WriteBehavior> which are defined in the
following table.

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Table 5-1 Possible Read and Write Behaviors

Read (or Write) Behavior Description

RC A read clears this register field.

RS A read sets this register field.

RM A read modifies the contents of this register field.

Wo You can only write once to this register field.

W1C A write of 1 clears this register field.

W1S A write of 1 sets this register field.

W1T A write of 1 toggles this register field.

W0C A write of 0 clears this register field.

W0S A write of 0 sets this register field.

W0T A write of 0 toggles this register field.

WC Any write clears this register field.

WS Any write sets this register field.

WM Any write toggles this register field.

no Read Behavior attribute You cannot read this register. It is Write-Only.

no Write Behavior attribute You cannot write to this register. It is Read-Only.

Table 5-2 Memory Access Examples

Memory Access Description

R Read-only register field.

W Write-only register field.

R/W Read/write register field.

R/W1C You can read this register field. Writing 1 clears it.

RC/W1C Reading this register field clears it. Writing 1 clears it.

R/Wo You can read this register field. You can only write to it once.

Special Optional Attributes

Some register fields might use the following optional attributes.

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Table 5-3 Optional Attributes

Attribute Description

Volatile As defined by the IP-XACT specification. If true, indicates in the

case of a write followed by read, or in the case of two consecutive
reads, there is no guarantee as to what is returned by the read on
the second transaction or that this return value is consistent with the
write or read of the first transaction. The element implies there is
some additional mechanism by which this field can acquire new
values other than by reads/writes/resets and other access methods
known to IP-XACT. For example, when the core updates the register
field contents.

Testable As defined by the IP-XACT specification. Possible values are

unconstrained, untestable, readOnly, writeAsRead, restore.
Untestable means that this field is untestable by a simple automated
register test. For example, the read-write access of the register is
controlled by a pin or another register. readOnly means that you
should not write to this register; only read from it. This might apply
for a register that modifies the contents of another register.

Reset Mask As defined by the IP-XACT specification. Indicates that this register
field has an unknown reset value. For example, the reset value is set
by another register or an input pin; or the register is implemented
using RAM.

* Varies Indicates that the memory access (or reset) attribute (read, write
behavior) is not fixed. For example, the read-write access of the
register is controlled by a pin or another register. Or when the
access depends on some configuration parameter; in this case the
post-configuration report in coreConsultant gives the actual access
value.

Component Banks/Blocks
The following table shows the address blocks for each memory map. Follow the link for an address block to
see a table of its registers.

Table 5-4 Address Banks/Blocks for Memory Map: DWC_mshc_map

Address Block Description

DWC_mshc_block on page 221 This register block defines the standard SD Host
Controller register set
Exists: Always

DWC_mshc_UHS_II_setting_block on page 425 This register block has UHS-II related setting registers
Exists: (DWC_MSHC_UHS2_SUPPORT==1)

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Table 5-4 Address Banks/Blocks for Memory Map: DWC_mshc_map (Continued)

Address Block Description

DWC_mshc_UHS_II_capability_block on page 434 This register block defines UHS-II related capability
registers
Exists: (DWC_MSHC_UHS2_SUPPORT==1)

DWC_mshc_UHS_II_test_block on page 445 This register block defines UHS-II test related registers
Exists: (DWC_MSHC_UHS2_SUPPORT==1)

DWC_mshc_embedded_control_block on page 451 This register block defines embedded control registers
Exists: Always

DWC_mshc_vendor2_block on page 456 This register block defines Vendor-2 related registers
Exists: DWC_MSHC_SD_EMMC_SUPPORT==1

DWC_mshc_phy_block on page 498 This register block has PHY related registers
Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1)

DWC_mshc_vendor1_block on page 540 This register block defines Vendor-1 related registers
Exists: Always

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5.1 DWC_mshc_map/DWC_mshc_block Registers

This register block defines the standard SD Host Controller register set. Follow the link for the register to see
a detailed description of the register.

Table 5-5 Registers for Address Block: DWC_mshc_map/DWC_mshc_block

Register Offset Description

SDMASA_R on page 225 0x0 SDMA System Address register

BLOCKSIZE_R on page 227 0x4 Block Size register

BLOCKCOUNT_R on page 229 0x6 16-bit Block Count register

ARGUMENT_R on page 230 0x8 Argument register

XFER_MODE_R on page 231 0xc Transfer Mode register

CMD_R on page 236 0xe Command register

RESP01_R on page 240 0x10 Response Register 0/1

RESP23_R on page 241 0x14 Response Register 2/3

RESP45_R on page 242 0x18 Response Register 4/5

RESP67_R on page 243 0x1c Response Register 6/7

BUF_DATA_R on page 244 0x20 Buffer Data Port Register

PSTATE_REG on page 245 0x24 Present State Register

HOST_CTRL1_R on page 253 0x28 Host Control 1 Register

PWR_CTRL_R on page 256 0x29 Power Control Register

BGAP_CTRL_R on page 260 0x2a Block Gap Control Register

WUP_CTRL_R on page 262 0x2b Wakeup Control Register

CLK_CTRL_R on page 264 0x2c Clock Control Register

TOUT_CTRL_R on page 268 0x2e Timeout Control Register

SW_RST_R on page 270 0x2f Software Reset Register

NORMAL_INT_STAT_R on page 273 0x30 Normal Interrupt Status Register

ERROR_INT_STAT_R on page 278 0x32 Error Interrupt Status Register

NORMAL_INT_STAT_EN_R on page 285 0x34 Normal Interrupt Status Enable Register

ERROR_INT_STAT_EN_R on page 289 0x36 Error Interrupt Status Enable Register

NORMAL_INT_SIGNAL_EN_R on 0x38 Normal Interrupt Signal Enable Register

page 293

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Table 5-5 Registers for Address Block: DWC_mshc_map/DWC_mshc_block (Continued)

Register Offset Description

ERROR_INT_SIGNAL_EN_R on 0x3a Error Interrupt Signal Enable Register

page 297

AUTO_CMD_STAT_R on page 301 0x3c Auto CMD Status Register

HOST_CTRL2_R on page 305 0x3e Host Control 2 Register

CAPABILITIES1_R on page 311 0x40 Capabilities 1 Register - 0 to 31

CAPABILITIES2_R on page 318 0x44 Capabilities Register - 32 to 63

CURR_CAPABILITIES1_R on page 323 0x48 Maximum Current Capabilities Register - 0 to 31

CURR_CAPABILITIES2_R on page 325 0x4c Maximum Current Capabilities Register - 32 to 63

FORCE_AUTO_CMD_STAT_R on 0x50 Force Event Register for Auto CMD Error Status register
page 327

FORCE_ERROR_INT_STAT_R on 0x52 Force Event Register for Error Interrupt Status

page 330

ADMA_ERR_STAT_R on page 334 0x54 ADMA Error Status Register

ADMA_SA_LOW_R on page 336 0x58 ADMA System Address Register - Low

ADMA_SA_HIGH_R on page 337 0x5c ADMA System Address Register - High

PRESET_INIT_R on page 338 0x60 Preset Value for Initialization

PRESET_DS_R on page 340 0x62 Preset Value for Default Speed

PRESET_HS_R on page 342 0x64 Preset Value for High Speed

PRESET_SDR12_R on page 344 0x66 Preset Value for SDR12

PRESET_SDR25_R on page 346 0x68 Preset Value for SDR25

PRESET_SDR50_R on page 348 0x6a Preset Value for SDR50

PRESET_SDR104_R on page 350 0x6c Preset Value for SDR104

PRESET_DDR50_R on page 352 0x6e Preset Value for DDR50

PRESET_UHS2_R on page 354 0x74 Preset Value for UHS-II

ADMA_ID_LOW_R on page 356 0x78 ADMA3 Integrated Descriptor Address Register - Low

ADMA_ID_HIGH_R on page 357 0x7c ADMA3 Integrated Descriptor Address Register - High

UHS_II_BLOCK_SIZE_R on page 358 0x80 UHS-II Block Size Register

UHS_II_BLOCK_COUNT_R on page 361 0x84 UHS-II Block Count Register

UHS_II_COMMAND_PKT_0_3_R on 0x88 UHS-II Command Packet Register (Byte 0, 1, 2 and 3)

page 363

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Table 5-5 Registers for Address Block: DWC_mshc_map/DWC_mshc_block (Continued)

Register Offset Description

UHS_II_COMMAND_PKT_4_7_R on 0x8c UHS-II Command Packet Register (Byte 4, 5, 6 and 7)

page 364

UHS_II_COMMAND_PKT_8_11_R on 0x90 UHS-II Command Packet Register (Byte 8, 9, 10 and 11)

page 365

UHS_II_COMMAND_PKT_12_15_R on 0x94 UHS-II Command Packet Register (Byte 12, 13, 14 and 15)
page 366

UHS_II_COMMAND_PKT_16_19_R on 0x98 UHS-II Command Packet Register (Byte 16, 17, 18 and 19)
page 367

UHS_II_XFER_MODE_R on page 368 0x9c UHS-II Transfer Mode Register

UHS_II_CMD_R on page 374 0x9e UHS-II Command Register

UHS_II_RESP_0_3_R on page 377 0xa0 UHS-II Response Register (Byte 0, 1, 2 and 3)

UHS_II_RESP_4_7_R on page 378 0xa4 UHS-II Response Register (Byte 4, 5, 6 and 7)

UHS_II_RESP_8_11_R on page 379 0xa8 UHS-II Response Register (Byte 8, 9, 10 and 11)

UHS_II_RESP_12_15_R on page 380 0xac UHS-II Response Register (Byte 12, 13, 14 and 15)

UHS_II_RESP_16_19_R on page 381 0xb0 UHS-II Response Register (Byte 16, 17, 18 and 19)

UHS_II_MSG_SEL_R on page 382 0xb4 UHS-II MSG Select Register

UHS_II_MSG_R on page 383 0xb8 UHS-II MSG Register

UHS_II_DEV_INTR_STATUS_R on 0xbc UHS-II Device Interrupt Status Register

page 384

UHS_II_DEV_SEL_R on page 389 0xbe UHS-II Device Select Register

UHS_II_DEV_INR_CODE_R on page 391 0xbf UHS-II Device Interrupt Code Register

UHS_II_SOFT_RESET_R on page 392 0xc0 UHS-II Software Reset Register

UHS_II_TIMER_CNTRL_R on page 395 0xc2 UHS-II Timer Control Register

UHS_II_ERR_INTR_STATUS_R on 0xc4 UHS-II Error Interrupt Status Register

page 398

UHS_II_ERR_INTR_STATUS_EN_R on 0xc8 UHS-II Error Interrupt Status Enable Register

page 405

UHS_II_ERR_INTR_SIGNAL_EN_R on 0xcc UHS-II Error Interrupt Signal Enable Register

page 410

P_UHS_II_SETTINGS_R on page 415 0xe0 Pointer for UHS-II Settings

P_UHS_II_HOST_CAPAB on page 416 0xe2 Pointer for UHS-II Host Capabilities

P_UHS_II_TEST on page 417 0xe4 Pointer for UHS-II Test

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Table 5-5 Registers for Address Block: DWC_mshc_map/DWC_mshc_block (Continued)

Register Offset Description

P_EMBEDDED_CNTRL on page 418 0xe6 Pointer for Embedded Control

P_VENDOR_SPECIFIC_AREA on 0xe8 Pointer for Vendor Specific Area 1

page 419

P_VENDOR2_SPECIFIC_AREA on 0xea Pointer for Vendor Specific Area 2

page 420

SLOT_INTR_STATUS_R on page 421 0xfc Slot Interrupt Status Register

HOST_CNTRL_VERS_R on page 423 0xfe Host Controller Version

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5.1.1 SDMASA_R
■ Name: SDMA System Address register
■ Description: This register is used to configure a 32-bit Block Count or an SDMA System Address
based on the Host Version 4 Enable bit in the Host Control 2 register. This register is applicable for
both SD and eMMC modes.
■ Size: 32 bits
■ Offset: 0x0
■ Exists: (DWC_MSHC_SD_EMMC_SUPPORT==1)

BLOCKCNT_SDMASA 31:0

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Table 5-6 Fields for Register: SDMASA_R

Memory
Bits Name Access Description

31:0 BLOCKCNT_SDMASA R/W 32-bit Block Count (SDMA System Address)

■ SDMA System Address (Host Version 4 Enable = 0): This
register contains the system memory address for an
SDMA transfer in the 32-bit addressing mode. When the
Host Controller stops an SDMA transfer, this register
points to the system address of the next contiguous data
position. It can be accessed only if no transaction is
executing. Reading this register during data transfers may
return an invalid value.
■ 32-bit Block Count (Host Version 4 Enable = 1): From the
Host Controller Version 4.10 specification, this register is
redefined as 32-bit Block Count. The Host Controller
decrements the block count of this register for every block
transfer and the data transfer stops when the count
reaches zero. This register must be accessed when no
transaction is executing. Reading this register during data
transfers may return invalid value.
Following are the values for BLOCKCNT_SDMASA:
■ 0xFFFF_FFFF: 4G - 1 Block
■ ...
■ 0x0000_0002: 2 Blocks
■ 0x0000_0001: 1 Block
■ 0x0000_0000: Stop Count
Note:
■ For Host Version 4 Enable = 0, the Host driver does not
program the system address in this register while
operating in ADMA mode. The system address must be
programmed in the ADMA System Address register.
■ For Host Version 4 Enable = 0, the Host driver programs
a non-zero 32-bit block count value in this register when
Auto CMD23 is enabled for non-DMA and ADMA modes.
Auto CMD23 cannot be used with SDMA.
■ This register must be programmed with a non-zero value
for data transfer if the 32-bit Block count register is used
instead of the 16-bit Block count register.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.2 BLOCKSIZE_R
■ Name: Block Size register
■ Description: This register is used to configure an SDMA buffer boundary and the number of bytes in
a data block. This register is applicable for both SD and eMMC modes.
■ Size: 16 bits
■ Offset: 0x4
■ Exists: (DWC_MSHC_SD_EMMC_SUPPORT==1)

14:12
11:0
RSVD_BLOCKSIZE15 15
SDMA_BUF_BDARY
XFER_BLOCK_SIZE

Table 5-7 Fields for Register: BLOCKSIZE_R

Memory
Bits Name Access Description

15 RSVD_BLOCKSIZE15 R This bit of the BLOCKSIZE_R register is reserved. It always

returns 0.
Value After Reset: 0x0
Exists: Always

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Table 5-7 Fields for Register: BLOCKSIZE_R (Continued)

Memory
Bits Name Access Description

14:12 SDMA_BUF_BDARY R/W SDMA Buffer Boundary

These bits specify the size of contiguous buffer in system
memory. The SDMA transfer waits at every boundary
specified by these fields and the Host Controller generates
the DMA interrupt to request the Host Driver to update the
SDMA System Address register.
Values:
■ 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary
■ 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary
■ 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary
■ 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary
■ 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary
■ 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary
■ 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary
■ 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary
Value After Reset: 0x0
Exists: Always

11:0 XFER_BLOCK_SIZE R/W Transfer Block Size

These bits specify the block size of data transfers. In case of
memory, it is set to 512 bytes. It can be accessed only if no
transaction is executing. Read operations during transfers
may return an invalid value, and write operations are
ignored. Following are the values for XFER_BLOCK_SIZE:
■ 0x1: 1 byte
■ 0x2: 2 bytes
■ 0x3: 3 bytes
■ ......
■ 0x1FF: 511 byte
■ 0x200: 512 bytes
■ ......
■ 0x800: 2048 bytes
Note: This register must be programmed with a non-zero
value for data transfer.
Value After Reset: 0x0
Exists: Always

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5.1.3 BLOCKCOUNT_R
■ Name: 16-bit Block Count register
■ Description: This register is used to configure the number of data blocks. This register is applicable
for both SD and eMMC modes.
■ Size: 16 bits
■ Offset: 0x6
■ Exists: (DWC_MSHC_SD_EMMC_SUPPORT==1)

BLOCK_CNT 15:0

Table 5-8 Fields for Register: BLOCKCOUNT_R

Memory
Bits Name Access Description

15:0 BLOCK_CNT R/W 16-bit Block Count

■ If the Host Version 4 Enable bit is set 0 or the 16-bit Block
Count register is set to non-zero, the 16-bit Block Count
register is selected.
■ If the Host Version 4 Enable bit is set 1 and the 16-bit
Block Count register is set to zero, the 32-bit Block Count
register is selected.
Following are the values for BLOCK_CNT:
■ 0x0: Stop Count
■ 0x1: 1 Block
■ 0x2: 2 Blocks
■ ... - ...
■ 0xFFFF: 65535 Blocks
Note: For Host Version 4 Enable = 0, this register must be
set to 0000h before programming the 32-bit block count
register when Auto CMD23 is enabled for non-DMA and
ADMA modes.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.4 ARGUMENT_R
■ Name: Argument register
■ Description: This register is used to configure the SD/eMMC command argument.
■ Size: 32 bits
■ Offset: 0x8
■ Exists: (DWC_MSHC_SD_EMMC_SUPPORT==1)

ARGUMENT 31:0

Table 5-9 Fields for Register: ARGUMENT_R

Memory
Bits Name Access Description

31:0 ARGUMENT R/W Command Argument

These bits specify the SD/eMMC command argument that is
specified in bits 39-8 of the Command format.
Value After Reset: 0x0
Exists: Always

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5.1.5 XFER_MODE_R
■ Name: Transfer Mode register
■ Description: This register is used to control the operation of data transfers for an SD/eMMC mode.
The Host driver sets this register before issuing a command that transfers data.
■ Size: 16 bits
■ Offset: 0xc
■ Exists: (DWC_MSHC_SD_EMMC_SUPPORT==1)

15:9

3:2
8
RESP_ERR_CHK_ENABLE 7
6
5
4

1
0
BLOCK_COUNT_ENABLE
AUTO_CMD_ENABLE
RESP_INT_DISABLE

DATA_XFER_DIR
MULTI_BLK_SEL

DMA_ENABLE
RESP_TYPE
RSVD

Table 5-10 Fields for Register: XFER_MODE_R

Memory
Bits Name Access Description

15:9 RSVD R These bits of the XFER_MODE_R register are reserved.

They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-10 Fields for Register: XFER_MODE_R (Continued)

Memory
Bits Name Access Description

8 RESP_INT_DISABLE R/W Response Interrupt Disable

The Host Controller supports response check function to
avoid overhead of response error check by the Host driver.
Response types of only R1 and R5 can be checked by the
Controller.
If Host Driver checks the response error, set this bit to 0 and
wait for Command Complete Interrupt and then check the
response register.
If the Host Controller checks the response error, set this bit
to 1 and set the Response Error Check Enable bit to 1. The
Command Complete Interrupt is disabled by this bit
regardless of the Command Complete Signal Enable.
Note: During tuning (when the Execute Tuning bit in the Host
Control2 register is set), the Command Complete Interrupt is
not generated irrespective of the Response Interrupt Disable
setting.
Values:
■ 0x0 (ENABLED): Response Interrupt is enabled
■ 0x1 (DISABLED): Response Interrupt is disabled
Value After Reset: 0x0
Exists: Always

7 RESP_ERR_CHK_ENABLE R/W Response Error Check Enable

The Host Controller supports response check function to
avoid overhead of response error check by Host driver.
Response types of only R1 and R5 can be checked by the
Controller. If the Host Controller checks the response error,
set this bit to 1 and set Response Interrupt Disable to 1. If an
error is detected, the Response Error interrupt is generated
in the Error Interrupt Status register.
Note:
■ Response error check must not be enabled for any
response type other than R1 and R5.
■ Response check must not be enabled for the tuning
command.

Values:
■ 0x0 (DISABLED): Response Error Check is disabled
■ 0x1 (ENABLED): Response Error Check is enabled
Value After Reset: 0x0
Exists: Always

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Table 5-10 Fields for Register: XFER_MODE_R (Continued)

Memory
Bits Name Access Description

6 RESP_TYPE R/W Response Type R1/R5

This bit selects either R1 or R5 as a response type when the
Response Error Check is selected.
Error statuses checked in R1:
■ OUT_OF_RANGE
■ ADDRESS_ERROR
■ BLOCK_LEN_ERROR
■ WP_VIOLATION
■ CARD_IS_LOCKED
■ COM_CRC_ERROR
■ CARD_ECC_FAILED
■ CC_ERROR
■ ERROR
Response Flags checked in R5:
■ COM_CRC_ERROR
■ ERROR
■ FUNCTION_NUMBER
■ OUT_OF_RANGE

Values:
■ 0x0 (RESP_R1): R1 (Memory)
■ 0x1 (RESP_R5): R5 (SDIO)
Value After Reset: 0x0
Exists: Always

5 MULTI_BLK_SEL R/W Multi/Single Block Select

This bit is set when issuing multiple-block transfer
commands using the DAT line. If this bit is set to 0, it is not
necessary to set the Block Count register.
Values:
■ 0x0 (SINGLE): Single Block
■ 0x1 (MULTI): Multiple Block
Value After Reset: 0x0
Exists: Always

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Table 5-10 Fields for Register: XFER_MODE_R (Continued)

Memory
Bits Name Access Description

4 DATA_XFER_DIR R/W Data Transfer Direction Select

This bit defines the direction of DAT line data transfers. This
bit is set to 1 by the Host Driver to transfer data from the
SD/eMMC card to the Host Controller and it is set to 0 for all
other commands.
Values:
■ 0x1 (READ): Read (Card to Host)
■ 0x0 (WRITE): Write (Host to Card)
Value After Reset: 0x0
Exists: Always

3:2 AUTO_CMD_ENABLE R/W Auto Command Enable

This field determines use of Auto Command functions.
Note: In SDIO, this field must be set as 00b (Auto Command
Disabled).
Values:
■ 0x0 (AUTO_CMD_DISABLED): Auto Command Disabled
■ 0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable
■ 0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable
■ 0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Select
Value After Reset: 0x0
Exists: Always

1 BLOCK_COUNT_ENABLE R/W Block Count Enable

This bit is used to enable the Block Count register, which is
relevant for multiple block transfers. If this bit is set to 0, the
Block Count register is disabled, which is useful in executing
an infinite transfer.
Values:
■ 0x1 (ENABLED): Enable
■ 0x0 (DISABLED): Disable
Value After Reset: 0x0
Exists: Always

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Table 5-10 Fields for Register: XFER_MODE_R (Continued)

Memory
Bits Name Access Description

0 DMA_ENABLE R/W DMA Enable

This bit enables the DMA functionality. If this bit is set to 1, a
DMA operation begins when the Host Driver writes to the
Command register. You can select one of the DMA modes by
using DMA Select in the Host Control 1 register.
Values:
■ 0x1 (ENABLED): DMA Data transfer
■ 0x0 (DISABLED): No data transfer or Non-DMA data
transfer
Value After Reset: 0x0
Exists: Always

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5.1.6 CMD_R
■ Name: Command register
■ Description: This register is used to provide the information related to a command and a response
packet. This register is applicable for an SD/eMMC mode.
■ Size: 16 bits
■ Offset: 0xe
■ Exists: (DWC_MSHC_SD_EMMC_SUPPORT==1)

15:14
13:8
7:6

1:0
5
4
CMD_CRC_CHK_ENABLE 3
2
CMD_IDX_CHK_ENABLE
DATA_PRESENT_SEL

RESP_TYPE_SELECT
SUB_CMD_FLAG
CMD_INDEX
CMD_TYPE
RSVD

Table 5-11 Fields for Register: CMD_R

Memory
Bits Name Access Description

15:14 RSVD R These bits of the CMD_R register are reserved. They always
return 0.
Value After Reset: 0x0
Exists: Always

13:8 CMD_INDEX R/W Command Index

These bits are set to the command number that is specified
in bits 45-40 of the Command Format.
Value After Reset: 0x0
Exists: Always

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Table 5-11 Fields for Register: CMD_R (Continued)

Memory
Bits Name Access Description

7:6 CMD_TYPE R/W Command Type

These bits indicate the command type.
Note: While issuing Abort CMD using CMD12/CMD52 or
reset CMD using CMD0/CMD52, CMD_TYPE field shall be
set to 0x3. In case CMD0 is used for initialization set as 0x0
Values:
■ 0x3 (ABORT_CMD): Abort
■ 0x2 (RESUME_CMD): Resume
■ 0x1 (SUSPEND_CMD): Suspend
■ 0x0 (NORMAL_CMD): Normal
Value After Reset: 0x0
Exists: Always

5 DATA_PRESENT_SEL R/W Data Present Select

This bit is set to 1 to indicate that data is present and that the
data is transferred using the DAT line. This bit is set to 0 in
the following instances:
■ Command using the CMD line
■ Command with no data transfer but using busy signal on
the DAT[0] line
■ Resume Command

Values:
■ 0x0 (NO_DATA): No Data Present
■ 0x1 (DATA): Data Present
Value After Reset: 0x0
Exists: Always

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Table 5-11 Fields for Register: CMD_R (Continued)

Memory
Bits Name Access Description

4 CMD_IDX_CHK_ENABLE R/W Command Index Check Enable

This bit enables the Host Controller to check the index field in
the response to verify if it has the same value as the
command index. If the value is not the same, it is reported as
a Command Index error.
Note:
■ Index Check enable must be set to 0 for the command
with no response, R2 response, R3 response and R4
response.
■ For the tuning command, this bit must always be set to
enable the index check.

Values:
■ 0x0 (DISABLED): Disable
■ 0x1 (ENABLED): Enable
Value After Reset: 0x0
Exists: Always

3 CMD_CRC_CHK_ENABLE R/W Command CRC Check Enable

This bit enables the Host Controller to check the CRC field in
the response. If an error is detected, it is reported as a
Command CRC error.
Note:
■ CRC Check enable must be set to 0 for the command
with no response, R3 response, and R4 response.
■ For the tuning command, this bit must always be set to 1
to enable the CRC check.

Values:
■ 0x0 (DISABLED): Disable
■ 0x1 (ENABLED): Enable
Value After Reset: 0x0
Exists: Always

2 SUB_CMD_FLAG R/W Sub Command Flag

This bit distinguishes between a main command and a sub
command.
Values:
■ 0x0 (MAIN): Main Command
■ 0x1 (SUB): Sub Command
Value After Reset: 0x0
Exists: Always

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Table 5-11 Fields for Register: CMD_R (Continued)

Memory
Bits Name Access Description

1:0 RESP_TYPE_SELECT R/W Response Type Select

This bit indicates the type of response expected from the
card.
Values:
■ 0x0 (NO_RESP): No Response
■ 0x1 (RESP_LEN_136): Response Length 136
■ 0x2 (RESP_LEN_48): Response Length 48
■ 0x3 (RESP_LEN_48B): Response Length 48; Check
Busy after response
Value After Reset: 0x0
Exists: Always

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5.1.7 RESP01_R
■ Name: Response Register 0/1
■ Description: This register stores 39-08 bits of the Response Field for an SD/eMMC mode. In UHS-II
mode, this register stores the response of the TRANS_ABORT CCMD. The response for an
SD/eMMC command can be a maximum of 128 bits. These 128 bits are segregated into four 32-bit
registers: RESP01_R, RESP23_R, RESP45_R and RESP67_R.
■ Size: 32 bits
■ Offset: 0x10
■ Exists: Always

RESP01 31:0

Table 5-12 Fields for Register: RESP01_R

Memory
Bits Name Access Description

31:0 RESP01 R Command Response

These bits reflect 39-8 bits of SD/eMMC Response Field. In
UHS-II mode, it stores the response of the TRANS_ABORT
CCMD.
Note: For Auto CMD, the 32-bit response (bits 39-8 of the
Response Field) is updated in the RESP67_R register.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.8 RESP23_R
■ Name: Response Register 2/3
■ Description: This register stores 71-40 bits of the Response Field for an SD/eMMC mode. This
register is used to store the response from the cards. The response can be a maximum of 128 bits.
These 128 bits are segregated into four 32-bit registers: RESP01_R, RESP23_R, RESP45_R and
RESP67_R. In UHS-II mode, this register is reserved
■ Size: 32 bits
■ Offset: 0x14
■ Exists: Always

RESP23 31:0

Table 5-13 Fields for Register: RESP23_R

Memory
Bits Name Access Description

31:0 RESP23 R Command Response

These bits reflect 71-40 bits of the SD/eMMC Response
Field. In UHS-II mode, it is reserved.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.9 RESP45_R
■ Name: Response Register 4/5
■ Description: This register stores 103-72 bits of the Response Field for an SD/eMMC mode. In UHS-II
mode, this register is used to store the lower 4-byte CMD12 response. The response for SD/eMMC
command can be a maximum of 128 bits. These 128 bits are segregated into four 32-bit registers:
RESP01_R, RESP23_R, RESP45_R and RESP67_R.
■ Size: 32 bits
■ Offset: 0x18
■ Exists: Always

RESP45 31:0

Table 5-14 Fields for Register: RESP45_R

Memory
Bits Name Access Description

31:0 RESP45 R Command Response

These bits reflect 103-72 bits of the Response Field. In UHS-
II mode, it stores the lower 4-byte CMD12 response.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.10 RESP67_R
■ Name: Response Register 6/7
■ Description: This register stores 135-104 bits of the Response Field for an SD/eMMC mode. In UHS-
II mode, this register stores the upper 4-byte CMD12 response. The SD/eMMC response can be a
maximum of 128 bits. These 128 bits are segregated into four 32-bit registers: RESP01_R, RESP23_R,
RESP45_R and RESP67_R.
■ Size: 32 bits
■ Offset: 0x1c
■ Exists: Always

RESP67 31:0

Table 5-15 Fields for Register: RESP67_R

Memory
Bits Name Access Description

31:0 RESP67 R Command Response

These bits reflect bits 135-104 of SD/EMMC Response
Field. In UHS-II mode, it stores the upper 4-byte CMD12
response.
Note: For Auto CMD, this register also reflects the 32-bit
response (bits 39-8 of the Response Field).
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.11 BUF_DATA_R
■ Name: Buffer Data Port Register
■ Description: This register is used to access the packet buffer. This register is applicable for an
SD/eMMC/UHS-II mode.
■ Size: 32 bits
■ Offset: 0x20
■ Exists: Always

BUF_DATA 31:0

Table 5-16 Fields for Register: BUF_DATA_R

Memory
Bits Name Access Description

31:0 BUF_DATA R/W Buffer Data

These bits enable access to the Host Controller packet
buffer.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.12 PSTATE_REG
■ Name: Present State Register
■ Description: This register indicates the present status of the Host Controller. This register is
applicable for an SD/eMMC/UHS-II mode.
■ Size: 32 bits
■ Offset: 0x24
■ Exists: Always

23:20

15:12

7:4
31
30
29
28
27
26
25
24

19
CARD_DETECT_PIN_LEVEL 18
17
16

11
10
9
8

3
2
1
0
WR_PROTECT_SW_LVL

WR_XFER_ACTIVE

DAT_LINE_ACTIVE
CMD_INHIBIT_DAT
RD_XFER_ACTIVE
BUF_WR_ENABLE
UHS2_IF_DETECT

CMD_ISSUE_ERR

BUF_RD_ENABLE
CARD_INSERTED
IN_DORMANT_ST

HOST_REG_VOL
SUB_CMD_STAT

CMD_LINE_LVL

RE_TUNE_REQ
CARD_STABLE

CMD_INHIBIT
RSVD_15_12
LANE_SYNC

RSVD_26

DAT_3_0

DAT_7_4
Table 5-17 Fields for Register: PSTATE_REG

Memory
Bits Name Access Description

31 UHS2_IF_DETECT R UHS-II Interface Detection

This bit indicates whether a card supports the UHS-II
interface. For SD/eMMC mode, this bit always returns 0.
Values:
■ 0x0 (FALSE): UHS-II interface is not detected
■ 0x1 (TRUE): UHS-II interface is detected
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-17 Fields for Register: PSTATE_REG (Continued)

Memory
Bits Name Access Description

30 LANE_SYNC R Lane Synchronization

This bit indicates whether a lane is synchronized in the UHS-
II mode. For SD/eMMC mode, this bit always returns 0.
Values:
■ 0x0 (FALSE): UHS-II PHY is not initialized
■ 0x1 (TRUE): UHS-II PHY is initialized
Value After Reset: 0x0
Exists: Always
Volatile: true

29 IN_DORMANT_ST R In Dormant Status

This bit indicates whether UHS-II lanes enter Dormant state
in the UHS-II mode. For SD/eMMC mode, this bit always
returns 0.
Values:
■ 0x0 (FALSE): Not in DORMANT state
■ 0x1 (TRUE): In DORMANT state
Value After Reset:
=::DWC_mshc::mshc_present_state_in_dormant_reset_val
Exists: Always
Volatile: true

28 SUB_CMD_STAT R Sub Command Status

This bit is used to distinguish between a main command and
a sub command status.
Values:
■ 0x0 (FALSE): Main Command Status
■ 0x1 (TRUE): Sub Command Status
Value After Reset: 0x0
Exists: Always
Volatile: true

27 CMD_ISSUE_ERR R Command Not Issued by Error

This bit is set if a command cannot be issued after setting
the command register due to an error except the Auto
CMD12 error.
Values:
■ 0x0 (FALSE): No error for issuing a command
■ 0x1 (TRUE): Command cannot be issued
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-17 Fields for Register: PSTATE_REG (Continued)

Memory
Bits Name Access Description

26 RSVD_26 R This bit of the PRESENT_ST_R register is reserved bits. It

always returns 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

25 HOST_REG_VOL R Host Regulator Voltage Stable

This bit is used to check whether the host regulator voltage is
stable for switching the voltage of UHS-I mode. This bit
reflects the synchronized value of the host_reg_vol_stable
signal.
Values:
■ 0x0 (FALSE): Host Regulator Voltage is not stable
■ 0x1 (TRUE): Host Regulator Voltage is stable
Value After Reset: 0x0
Exists: Always
Volatile: true

24 CMD_LINE_LVL R Command-Line Signal Level

This bit is used to check the CMD line level to recover from
errors and for debugging. These bits reflect the value of the
sd_cmd_in signal. This bit is irrelevant for an UHS-II mode
and always returns 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

23:20 DAT_3_0 R DAT[3:0] Line Signal Level

This bit is used to check the DAT line level to recover from
errors and for debugging. These bits reflect the value of the
sd_dat_in (lower nibble) signal. These bits are irrelevant for
the UHS-II mode and always returns 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-17 Fields for Register: PSTATE_REG (Continued)

Memory
Bits Name Access Description

19 WR_PROTECT_SW_LVL R Write Protect Switch Pin Level

This bit is supported only for memory and combo cards. This
bit reflects the synchronized value of the card_write_prot
signal.
Values:
■ 0x0 (FALSE): Write protected
■ 0x1 (TRUE): Write enabled
Value After Reset: 0x0
Exists: Always
Volatile: true

18 CARD_DETECT_PIN_LEVEL R Card Detect Pin Level

This bit reflects the inverse synchronized value of the
card_detect_n signal.
Values:
■ 0x0 (FALSE): No card present
■ 0x1 (TRUE): Card Present
Value After Reset: 0x0
Exists: Always
Volatile: true

17 CARD_STABLE R Card Stable

This bit indicates the stability of the Card Detect Pin Level. A
card is not detected if this bit is set to 1 and the value of the
CARD_INSERTED bit is 0.
Values:
■ 0x0 (FALSE): Reset or Debouncing
■ 0x1 (TRUE): No Card or Inserted
Value After Reset: 0x0
Exists: Always
Volatile: true

16 CARD_INSERTED R Card Inserted

This bit indicates whether a card has been inserted. The
Host Controller debounces this signal so that Host Driver
need not wait for it to stabilize.
Values:
■ 0x0 (FALSE): Reset, Debouncing, or No card
■ 0x1 (TRUE): Card Inserted
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-17 Fields for Register: PSTATE_REG (Continued)

Memory
Bits Name Access Description

15:12 RSVD_15_12 R These bits of the PRESENT_STAT_R register are reserved.

They always return 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

11 BUF_RD_ENABLE R Buffer Read Enable

This bit is used for non-DMA transfers. This bit is set if valid
data exists in the Host buffer.
Values:
■ 0x0 (DISABLED): Read disable
■ 0x1 (ENABLED): Read enable
Value After Reset: 0x0
Exists: Always
Volatile: true

10 BUF_WR_ENABLE R Buffer Write Enable

This bit is used for non-DMA transfers. This bit is set if space
is available for writing data.
Values:
■ 0x0 (DISABLED): Write disable
■ 0x1 (ENABLED): Write enable
Value After Reset: 0x0
Exists: Always
Volatile: true

9 RD_XFER_ACTIVE R Read Transfer Active

This bit indicates whether a read transfer is active for
SD/eMMC mode. This bit irrelevant for the UHS-II mode and
always returns 0.
Values:
■ 0x0 (INACTIVE): No valid data
■ 0x1 (ACTIVE): Transferring data
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-17 Fields for Register: PSTATE_REG (Continued)

Memory
Bits Name Access Description

8 WR_XFER_ACTIVE R Write Transfer Active

This status indicates whether a write transfer is active for
SD/eMMC mode. It is irrelevant for UHS-II mode and always
returns 0.
Values:
■ 0x0 (INACTIVE): No valid data
■ 0x1 (ACTIVE): Transferring data
Value After Reset: 0x0
Exists: Always
Volatile: true

7:4 DAT_7_4 R DAT[7:4] Line Signal Level

This bit is used to check the DAT line level to recover from
errors and for debugging. These bits reflect the value of the
sd_dat_in (upper nibble) signal. These bits are irrelevant for
the UHS-II mode and always return 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

3 RE_TUNE_REQ R Re-Tuning Request

DWC_mshc does not generate retuning request. The
software must maintain the Retuning timer.
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-17 Fields for Register: PSTATE_REG (Continued)

Memory
Bits Name Access Description

2 DAT_LINE_ACTIVE R DAT Line Active (SD/eMMC Mode only)

This bit indicates whether one of the DAT lines on the
SD/eMMC bus is in use. This bit is irrelevant for the UHS-II
mode.

In the case of read transactions, this bit indicates whether a

read transfer is executing on the SD/eMMC bus.
In the case of write transactions, this bit indicates whether a
write transfer is executing on the SD/eMMC bus.
For a command with busy, this status indicates whether the
command executing busy is executing on an SD or eMMC
bus.
Values:
■ 0x0 (INACTIVE): DAT Line Inactive
■ 0x1 (ACTIVE): DAT Line Active
Value After Reset: 0x0
Exists: Always
Volatile: true

1 CMD_INHIBIT_DAT R Command Inhibit (DAT)

This bit is applicable for SD/eMMC mode and is generated if

either DAT line active or Read transfer active is set to 1. If
this bit is set to 0, it indicates that the Host Controller can
issue subsequent SD/eMMC commands. For the UHS-II
mode, this bit is irrelevant and always returns 0.
Values:
■ 0x0 (READY): Can issue command which used DAT line
■ 0x1 (NOT_READY): Cannot issue command which used
DAT line
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-17 Fields for Register: PSTATE_REG (Continued)

Memory
Bits Name Access Description

0 CMD_INHIBIT R Command Inhibit (CMD)

This bit indicates the following :

■ SD/eMMC mode: If this bit is set to 0, it indicates that the

CMD line is not in use and the Host controller can issue
an SD/eMMC command using the CMD line. This bit is
set when the command register is written. This bit is
cleared when the command response is received. This bit
is not cleared by the response of auto CMD12/23 but
cleared by the response of read/write command.

■ UHS-II mode: If this bit is set to 0, it indicates that a

command packet can be issued by the Host Controller.

Values:
■ 0x0 (READY): Host Controller is ready to issue a
command
■ 0x1 (NOT_READY): Host Controller is not ready to issue
a command
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.13 HOST_CTRL1_R
■ Name: Host Control 1 Register
■ Description: This register is used to control the operation of the Host Controller. This register is
applicable for an SD/eMMC/UHS-II mode.
■ Size: 8 bits
■ Offset: 0x28
■ Exists: Always

4:3
7
CARD_DETECT_TEST_LVL 6
5

2
1
0
CARD_DETECT_SIG_SEL

DAT_XFER_WIDTH
HIGH_SPEED_EN
EXT_DAT_XFER

LED_CTRL
DMA_SEL

Table 5-18 Fields for Register: HOST_CTRL1_R

Memory
Bits Name Access Description

7 CARD_DETECT_SIG_SEL R/W Card Detect Signal Selection

This bit selects a source for card detection. When the source
for the card detection is switched, the interrupt must be
disabled during the switching period.
Values:
■ 0x1 (CARD_DT_TEST_LEVEL): Card Detect Test Level
is selected (for test purpose)
■ 0x0 (SDCD_PIN): SDCD# (card_detect_n signal) is
selected (for normal use)
Value After Reset: 0x0
Exists: Always

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Table 5-18 Fields for Register: HOST_CTRL1_R (Continued)

Memory
Bits Name Access Description

6 CARD_DETECT_TEST_LVL R/W Card Detect Test Level

This bit is enabled while the Card Detect Signal Selection is
set to 1 and it indicates whether a card inserted or not.
Values:
■ 0x1 (CARD_INSERTED): Card Inserted
■ 0x0 (No_CARD): No Card
Value After Reset: 0x0
Exists: Always

5 EXT_DAT_XFER R/W Extended Data Transfer Width

This bit controls 8-bit bus width mode of embedded device.
This bit is not applicable for UHS-II mode.
Values:
■ 0x1 (EIGHT_BIT): 8-bit Bus Width
■ 0x0 (DEFAULT): Bus Width is selected by the Data
Transfer Width
Value After Reset: 0x0
Exists: Always

4:3 DMA_SEL R/W DMA Select

This field is used to select the DMA type.
When Host Version 4 Enable is 1 in Host Control 2 register:
■ 0x0 : SDMA is selected
■ 0x1 : Reserved
■ 0x2 : ADMA2 is selected
■ 0x3 : ADMA2 or ADMA3 is selected

When Host Version 4 Enable is 0 in Host Control 2 register:

■ 0x0 : SDMA is selected
■ 0x1 : Reserved
■ 0x2 : 32-bit Address ADMA2 is selected
■ 0x3 : 64-bit Address ADMA2 is selected

Values:
■ 0x0 (SDMA): SDMA is selected
■ 0x1 (RSVD_BIT): Reserved
■ 0x2 (ADMA2): ADMA2 is selected
■ 0x3 (ADMA2_3): ADMA2 or ADMA3 is selected
Value After Reset: 0x0
Exists: Always

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Table 5-18 Fields for Register: HOST_CTRL1_R (Continued)

Memory
Bits Name Access Description

2 HIGH_SPEED_EN R/W High Speed Enable (SD/eMMC Mode only)

In SD/eMMC mode, this bit is used to determine the

selection of preset value for High Speed mode. Before
setting this bit, the Host Driver checks the High Speed
Support in the Capabilities register.
Note: DWC_MSHC always outputs the sd_cmd_out and
sd_dat_out lines at the rising edge of cclk_tx clock
irrespective of this bit.Please refer the section Connecting
the Clock IO interface in the Mobile Storage Host Controller
user guide on clocking requirement for an SD/eMMC card.
In UHS-II mode, this bit is irrelevant.
Values:
■ 0x1 (HIGH_SPEED): High Speed mode
■ 0x0 (NORMAL_SPEED): Normal Speed mode
Value After Reset: 0x0
Exists: Always

1 DAT_XFER_WIDTH R/W Data Transfer Width

For SD/eMMC mode,this bit selects the data transfer width of
the Host Controller. The Host Driver sets it to match the data
width of the SD/eMMC card. In UHS-II mode, this bit is
irrelevant.
Values:
■ 0x1 (FOUR_BIT): 4-bit mode
■ 0x0 (ONE_BIT): 1-bit mode
Value After Reset: 0x0
Exists: Always

0 LED_CTRL R/W LED Control

This bit is used to caution the user not to remove the card
while the SD card is being accessed. The value is reflected
on the led_control signal.
Values:
■ 0x0 (OFF): LED off
■ 0x1 (ON): LED on
Value After Reset: 0x0
Exists: Always

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5.1.14 PWR_CTRL_R
■ Name: Power Control Register
■ Description: This register is used to control the bus power for the Card. This register is applicable for
an SD, eMMC, and UHS-II modes.
■ Size: 8 bits
■ Offset: 0x29
■ Exists: Always

7:5

3:1
SD_BUS_PWR_VDD2 4

SD_BUS_PWR_VDD1 0
SD_BUS_VOL_VDD2

SD_BUS_VOL_VDD1

Table 5-19 Fields for Register: PWR_CTRL_R

Memory
Bits Name Access Description

7:5 SD_BUS_VOL_VDD2 R/W SD Bus Voltage Select for VDD2.

This bit determines supply voltage range to VDD2 of UHS-II

card. This bit be can set to 0x5 if 1.8V VDD2 Support in the
Capabilities register is set to 1. This is irrelevant for
SD/eMMC card.
Values:
■ 0x7 (NOT_USED7): Not used
■ 0x6 (NOT_USED6): Not used
■ 0x5 (V_1_8): 1.8V
■ 0x4 (V_1_2): Reserved for 1.2V
■ 0x3 (RSVD3): Reserved
■ 0x2 (RSVD2): Reserved
■ 0x1 (RSVD1): Reserved
■ 0x0 (NO_VDD2): VDD2 Not Supported
Value After Reset: 0x0
Exists: Always

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Table 5-19 Fields for Register: PWR_CTRL_R (Continued)

Memory
Bits Name Access Description

4 SD_BUS_PWR_VDD2 R/W SD Bus Power for VDD2.

This bit enables VDD2 power of UHS-II card. This setting is

available on the sd_vdd2_on output of DWC_mshc so that it
can be used to control the VDD2 power supply of the card.
This is irrelevant for SD/eMMC card.
Values:
■ 0x0 (OFF): Power off
■ 0x1 (ON): Power on
Value After Reset: 0x0
Exists: Always

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Table 5-19 Fields for Register: PWR_CTRL_R (Continued)

Memory
Bits Name Access Description

3:1 SD_BUS_VOL_VDD1 R/W SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select
for VDD
These bits enable the Host Driver to select the voltage level
for an SD/eMMC card. Before setting this register, the Host
Driver checks the Voltage Support bits in the Capabilities
register. If an unsupported voltage is selected, the Host
System does not supply the SD Bus voltage. The value set in
this field is available on the DWC_mshc output signal
(sd_vdd1_sel), which is used by the voltage switching
circuitry.
SD Bus Voltage Select options:
■ 0x7 : 3.3V(Typical)
■ 0x6 : 3.0V(Typical)
■ 0x5 : 1.8V(Typical) for Embedded
■ 0x4 : 0x0 - Reserved

eMMC Bus Voltage Select options:

■ 0x7 : 3.3V(Typical)
■ 0x6 : 1.8V(Typical)
■ 0x5 : 1.2V(Typical)
■ 0x4 : 0x0 - Reserved

Values:
■ 0x7 (V_3_3): 3.3V (Typ.)
■ 0x6 (V_3_0): 3.0V (Typ.)
■ 0x5 (V_1_8): 1.8V (Typ.) for Embedded
■ 0x4 (RSVD4): Reserved
■ 0x3 (RSVD3): Reserved
■ 0x2 (RSVD2): Reserved
■ 0x1 (RSVD1): Reserved
■ 0x0 (RSVD0): Reserved
Value After Reset: 0x0
Exists: Always

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Table 5-19 Fields for Register: PWR_CTRL_R (Continued)

Memory
Bits Name Access Description

0 SD_BUS_PWR_VDD1 R/W SD Bus Power for VDD1

This bit enables VDD1 power of the card. This setting is
available on the sd_vdd1_on output of DWC_mshc so that it
can be used to control the VDD1 power supply of the card.
Before setting this bit, the SD Host Driver sets the SD Bus
Voltage Select bit. If the Host Controller detects a No Card
state, this bit is cleared.
In SD mode, if this bit is cleared, the Host Controller stops
the SD Clock by clearing the SD_CLK_IN bit in the
CLK_CTRL_R register.
In UHS-II mode, before clearing this bit, the Host Driver
clears the SD_CLK_IN bit in the CLK_CTRL_R register.
Values:
■ 0x0 (OFF): Power off
■ 0x1 (ON): Power on
Value After Reset: 0x0
Exists: Always

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5.1.15 BGAP_CTRL_R
■ Name: Block Gap Control Register
■ Description: This register is used by the host driver to control any operation related to Block Gap.
This register is applicable for an SD/eMMC/UHS-II mode.
■ Size: 8 bits
■ Offset: 0x2a
■ Exists: Always

7:4
3
2
CONTINUE_REQ 1
0
RD_WAIT_CTRL

STOP_BG_REQ
INT_AT_BGAP
RSVD_7_4

Table 5-20 Fields for Register: BGAP_CTRL_R

Memory
Bits Name Access Description

7:4 RSVD_7_4 R These bits of the Block Gap Control register are reserved.
They always return 0.
Value After Reset: 0x0
Exists: Always

3 INT_AT_BGAP R/W Interrupt At Block Gap

This bit is valid only in the 4-bit mode of an SDIO card and is
used to select a sample point in the interrupt cycle. Setting to
1 enables interrupt detection at the block gap for a multiple
block transfer. In UHS-II mode, this bit is disabled.
Values:
■ 0x0 (DISABLE): Disabled
■ 0x1 (ENABLE): Enabled
Value After Reset: 0x0
Exists: Always

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Table 5-20 Fields for Register: BGAP_CTRL_R (Continued)

Memory
Bits Name Access Description

2 RD_WAIT_CTRL R/W Read Wait Control

This bit is used to enable the read wait protocol to stop read
data using DAT[2] line if the card supports read wait.
Otherwise, the Host Controller has to stop the card clock to
hold the read data. In UHS-II mode, Read Wait is disabled.
Values:
■ 0x0 (DISABLE): Disable Read Wait Control
■ 0x1 (ENABLE): Enable Read Wait Control
Value After Reset: 0x0
Exists: Always

1 CONTINUE_REQ R/W Continue Request

This bit is used to restart the transaction, which was stopped
using the Stop At Block Gap Request. The Host Controller
automatically clears this bit when the transaction restarts. If
stop at block gap request is set to 1, any write to this bit is
ignored.
Values:
■ 0x0 (NO_AFFECT): No Affect
■ 0x1 (RESTART): Restart
Value After Reset: 0x0
Exists: Always
Volatile: true

0 STOP_BG_REQ R/W Stop At Block Gap Request

This bit is used to stop executing read and write transactions
at the next block gap for non-DMA, SDMA, and ADMA
transfers.
Values:
■ 0x0 (XFER): Transfer
■ 0x1 (STOP): Stop
Value After Reset: 0x0
Exists: Always

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5.1.16 WUP_CTRL_R
■ Name: Wakeup Control Register
■ Description: This register is mandatory for the Host Controller, but the wakeup functionality
depends on the Host Controller system hardware and software. The Host Driver maintains voltage
on the SD Bus by setting the SD Bus Power to 1 in the Power Control Register, while a wakeup event
through the Card Interrupt is desired.
■ Size: 8 bits
■ Offset: 0x2b
■ Exists: Always

7:3
CARD_REMOVAL 2
1
0
CARD_INSERT
RSVD_7_3

CARD_INT

Table 5-21 Fields for Register: WUP_CTRL_R

Memory
Bits Name Access Description

7:3 RSVD_7_3 R These bits of Wakeup Control register are reserved. They
always return 0.
Value After Reset: 0x0
Exists: Always

2 CARD_REMOVAL R/W Wakeup Event Enable on SD Card Removal

This bit enables wakeup event through Card Removal
assertion in the Normal Interrupt Status register. For the
SDIO card, Wake Up Support (FN_WUS) in the Card
Information Structure (CIS) register does not affect this bit.
Values:
■ 0x0 (DISABLED): Disable
■ 0x1 (ENABLED): Enable
Value After Reset: 0x0
Exists: Always

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Table 5-21 Fields for Register: WUP_CTRL_R (Continued)

Memory
Bits Name Access Description

1 CARD_INSERT R/W Wakeup Event Enable on SD Card Insertion

This bit enables wakeup event through Card Insertion
assertion in the Normal Interrupt Status register. FN_WUS
(Wake Up Support) in CIS does not affect this bit.
Values:
■ 0x0 (DISABLED): Disable
■ 0x1 (ENABLED): Enable
Value After Reset: 0x0
Exists: Always

0 CARD_INT R/W Wakeup Event Enable on Card Interrupt

This bit enables wakeup event through a Card Interrupt
assertion in the Normal Interrupt Status register. This bit can
be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1.
Values:
■ 0x0 (DISABLED): Disable
■ 0x1 (ENABLED): Enable
Value After Reset: 0x0
Exists: Always

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5.1.17 CLK_CTRL_R
■ Name: Clock Control Register
■ Description: This register controls SDCLK (card clock) in an SD/eMMC mode and RCLK in the
UHS-II mode. This register is applicable for an SD/eMMC/UHS-II mode.
■ Size: 16 bits
■ Offset: 0x2c
■ Exists: Always

15:8
7:6
5
4
3
2
INTERNAL_CLK_STABLE 1
0
INTERNAL_CLK_EN
UPPER_FREQ_SEL
CLK_GEN_SELECT

PLL_ENABLE
SD_CLK_EN
FREQ_SEL

RSVD_4

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Table 5-22 Fields for Register: CLK_CTRL_R

Memory
Bits Name Access Description

15:8 FREQ_SEL R/W SDCLK/RCLK Frequency Select

These bits are used to select the frequency of the SDCLK
signal. These bits depend on setting of Preset Value Enable
in the Host Control 2 register. If Preset Value Enable = 0,
these bits are set by the Host Driver. If Preset Value Enable =
1, these bits are automatically set to a value specified in one
of the Preset Value register. The value is reflected on the
lower 8-bit of the card_clk_freq_selsignal.

10-bit Divided Clock Mode:

■ 0x3FF : 1/2046 Divided clock
■ ..........
■ N : 1/2N Divided Clock
■ ..........
■ 0x002 : 1/4 Divided Clock
■ 0x001 : 1/2 Divided Clock
■ 0x000 : Base clock (10MHz - 255 MHz)

Programmable Clock Mode : Enables the Host System to

select a fine grain SD clock frequency:
■ 0x3FF : Base clock * M /1024
■ ..........
■ N-1 : Base clock * M /N
■ ..........
■ 0x002 : Base clock * M /3
■ 0x001 : Base clock * M /2
■ 0x000 : Base clock * M
Value After Reset: 0x0
Exists: Always
Volatile: true

7:6 UPPER_FREQ_SEL R/W These bits specify the upper 2 bits of 10-bit SDCLK/RCLK
Frequency Select control. The value is reflected on the upper
2 bits of the card_clk_freq_sel signal.
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-22 Fields for Register: CLK_CTRL_R (Continued)

Memory
Bits Name Access Description

5 CLK_GEN_SELECT R/W Clock Generator Select

This bit is used to select the clock generator mode in
SDCLK/RCLK Frequency Select. If Preset Value Enable = 0,
this bit is set by the Host Driver. If Preset Value Enable = 1,
this bit is automatically set to a value specified in one of the
Preset Value registers. The value is reflected on the
card_clk_gen_sel signal.
Values:
■ 0x0 (FALSE): Divided Clock Mode
■ 0x1 (TRUE): Programmable Clock Mode
Value After Reset: 0x0
Exists: Always
Volatile: true

4 RSVD_4 R This bit of the CLK_CTRL_R register is reserved. It always

returns 0.
Value After Reset: 0x0
Exists: Always

3 PLL_ENABLE R/W PLL Enable

This bit is used to activate the PLL (applicable when Host
Version 4 Enable = 1). When Host Version 4 Enable = 0,
INTERNAL_CLK_EN bit may be used to activate PLL. The
value is reflected on the card_clk_en signal.
Note: If this bit is not used to to active the PLL when Host
Version 4 Enable = 1, it is recommended to set this bit to '1' .
Values:
■ 0x0 (FALSE): PLL is in low power mode
■ 0x1 (TRUE): PLL is enabled
Value After Reset: 0x0
Exists: Always

2 SD_CLK_EN R/W SD/eMMC Clock Enable

This bit stops the SDCLK or RCLK when set to 0. The
SDCLK/RCLK Frequency Select bit can be changed when
this bit is set to 0. The value is reflected on the clk2card_on
pin.
Values:
■ 0x0 (FALSE): Disable providing SDCLK/RCLK
■ 0x1 (TRUE): Enable providing SDCLK/RCLK
Value After Reset: 0x0
Exists: Always

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Table 5-22 Fields for Register: CLK_CTRL_R (Continued)

Memory
Bits Name Access Description

1 INTERNAL_CLK_STABLE R Internal Clock Stable

This bit enables the Host Driver to check the clock stability
twice after the Internal Clock Enable bit is set and after the
PLL Enable bit is set. This bit reflects the synchronized value
of the intclk_stable signal after the Internal Clock Enable bit
is set to 1 and also reflects the synchronized value of the
card_clk_stable signal after the PLL Enable bit is set to 1.
Values:
■ 0x0 (FALSE): Not Ready
■ 0x1 (TRUE): Ready
Value After Reset: 0x0
Exists: Always
Volatile: true

0 INTERNAL_CLK_EN R/W Internal Clock Enable

This bit is set to 0 when the Host Driver is not using the Host
Controller or the Host Controller awaits a wakeup interrupt.
The Host Controller must stop its internal clock to enter a
very low power state. However, registers can still be read and
written to. The value is reflected on the intclk_en signal.
Note: If this bit is not used to control the internal clock (base
clock and master clock), it is recommended to set this bit to
'1' .
Values:
■ 0x0 (FALSE): Stop
■ 0x1 (TRUE): Oscillate
Value After Reset: 0x0
Exists: Always

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5.1.18 TOUT_CTRL_R
■ Name: Timeout Control Register
■ Description: This register is used to set the Data Timeout Counter value for an SD/eMMC mode
according to the timer clock defined by the Capabilities register, while initializig the Host Controller.
■ Size: 8 bits
■ Offset: 0x2e
■ Exists: (DWC_MSHC_SD_EMMC_SUPPORT==1)

7:4
TOUT_CNT 3:0
RSVD_7_4

Table 5-23 Fields for Register: TOUT_CTRL_R

Memory
Bits Name Access Description

7:4 RSVD_7_4 R These bits of the Timeout Control register are reserved.
They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-23 Fields for Register: TOUT_CTRL_R (Continued)

Memory
Bits Name Access Description

3:0 TOUT_CNT R/W Data Timeout Counter Value.

This value determines the interval by which DAT line
timeouts are detected. The Timeout clock frequency is
generated by dividing the base clock TMCLK value by this
value. When setting this register, prevent inadvertent timeout
events by clearing the Data Timeout Error Status Enable (in
the Error Interrupt Status Enable register). The values for
these bits are:
■ 0xF : Reserved
■ 0xE : TMCLK x 2^27
■ .........
■ 0x1 : TMCLK x 2^14
■ 0x0 : TMCLK x 2^13

Note: During a boot operating in an eMMC mode, an

application must configure the boot data timeout value
(approximately 1 sec) in this bit.
Value After Reset: 0x0
Exists: Always

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5.1.19 SW_RST_R
■ Name: Software Reset Register
■ Description: This register is used to generate a reset pulse by writing 1 to each bit of this register.
After completing the reset, the Host Controller clears each bit. As it takes some time to complete a
software reset, the Host Driver confirms that these bits are 0. This register is applicable for an
SD/eMMC/UHS-II mode.
Note: Refer Software Reset section in the DWC_mshc Databook for additional details.
■ Size: 8 bits
■ Offset: 0x2f
■ Exists: Always

7:3
2
SW_RST_CMD 1
0
SW_RST_DAT

SW_RST_ALL
RSVD_7_3

Table 5-24 Fields for Register: SW_RST_R

Memory
Bits Name Access Description

7:3 RSVD_7_3 R These bits of the SW_RST_R register are reserved. They
always return 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-24 Fields for Register: SW_RST_R (Continued)

Memory
Bits Name Access Description

2 SW_RST_DAT R/W Software Reset For DAT line

This bit is used in SD/eMMC mode and it resets only a part
of the data circuit and the DMA circuit is also reset.
The following registers and bits are cleared by this bit:
■ Buffer Data Port register
- Buffer is cleared and initialized.
■ Present state register
- Buffer Read Enable
- Buffer Write Enable
- Read Transfer Active
- Write Transfer Active
- DAT Line Active
- Command Inhibit (DAT)
■ Block Gap Control register
- Continue Request
- Stop At Block Gap Request
■ Normal Interrupt status register
- Buffer Read Ready
- Buffer Write Ready
- DMA Interrupt
- Block Gap Event
- Transfer Complete
In UHS-II mode, this bit shall be set to 0

Values:
■ 0x0 (FALSE): Work
■ 0x1 (TRUE): Reset
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-24 Fields for Register: SW_RST_R (Continued)

Memory
Bits Name Access Description

1 SW_RST_CMD R/W Software Reset For CMD line

This bit resets only a part of the command circuit to be able
to issue a command. It bit is also used to initialize a UHS-II
command circuit. This reset is effective only for a command
issuing circuit (including response error statuses related to
Command Inhibit (CMD) control) and does not affect the
data transfer circuit. Host Controller can continue data
transfer even after this reset is executed while handling
subcommand-response errors.
The following registers and bits are cleared by this bit:
■ Present State register : Command Inhibit (CMD) bit
■ Normal Interrupt Status register : Command Complete bit
■ Error Interrupt Status : Response error statuses related to
Command Inhibit (CMD) bit

Values:
■ 0x0 (FALSE): Work
■ 0x1 (TRUE): Reset
Value After Reset: 0x0
Exists: Always
Volatile: true

0 SW_RST_ALL R/W Software Reset For All

This reset affects the entire Host Controller except for the
card detection circuit. During its initialization, the Host Driver
sets this bit to 1 to reset the Host Controller. All registers are
reset except the capabilities register. If this bit is set to 1, the
Host Driver must issue reset command and reinitialize the
card.
Values:
■ 0x0 (FALSE): Work
■ 0x1 (TRUE): Reset
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.20 NORMAL_INT_STAT_R
■ Name: Normal Interrupt Status Register
■ Description: This register reflects the status of the Normal Interrupt. This register is applicable for an
SD/eMMC/UHS-II mode.
■ Size: 16 bits
■ Offset: 0x30
■ Exists: Always
15
14
13
12
11
10
9
CARD_INTERRUPT 8
7
6
5
4
3
2
1
0
CARD_INSERTION

XFER_COMPLETE
RE_TUNE_EVENT

DMA_INTERRUPT
ERR_INTERRUPT

CMD_COMPLETE
CARD_REMOVAL

BUF_WR_READY
BUF_RD_READY

BGAP_EVENT
CQE_EVENT
FX_EVENT

INT_C
INT_B
INT_A

Table 5-25 Fields for Register: NORMAL_INT_STAT_R

Memory
Bits Name Access Description

15 ERR_INTERRUPT R Error Interrupt

If any of the bits in the Error Interrupt Status register are set,
then this bit is set.
Values:
■ 0x0 (FALSE): No Error
■ 0x1 (TRUE): Error
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-25 Fields for Register: NORMAL_INT_STAT_R (Continued)

Memory
Bits Name Access Description

14 CQE_EVENT R/W1C Command Queuing Event

This status is set if Command Queuing/Crypto related event
has occurred in eMMC/SD mode. Read CQHCI's
CQIS/CRNQIS register for more details. In UHS-II Mode, this
bit is irrelevant.
Values:
■ 0x0 (FALSE): No Event
■ 0x1 (TRUE): Command Queuing Event is detected
Value After Reset: 0x0
Exists: Always
Volatile: true

13 FX_EVENT R FX Event
This status is set when R[14] of response register is set to 1
and Response Type R1/R5 is set to 0 in Transfer Mode
register. This interrupt is used with response check function.
Values:
■ 0x0 (FALSE): No Event
■ 0x1 (TRUE): FX Event is detected
Value After Reset: 0x0
Exists: Always
Volatile: true

12 RE_TUNE_EVENT R Re-tuning Event

This bit is set if the Re-Tuning Request changes from 0 to 1.
Re-Tuning request is not supported.
Value After Reset: 0x0
Exists: Always
Volatile: true

11 INT_C R INT_C (Embedded)

This bit is set if INT_C is enabled and if INT_C# pin is in low
level. The INT_C# pin is not supported.
Value After Reset: 0x0
Exists: Always
Volatile: true

10 INT_B R INT_B (Embedded)

This bit is set if INT_B is enabled and if INT_B# pin is in low
level. The INT_B# pin is not supported.
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-25 Fields for Register: NORMAL_INT_STAT_R (Continued)

Memory
Bits Name Access Description

9 INT_A R INT_A (Embedded)

This bit is set if INT_A is enabled and if INT_A# pin is in low
level. The INT_A# pin is not supported.
Value After Reset: 0x0
Exists: Always
Volatile: true

8 CARD_INTERRUPT R Card Interrupt

This bit reflects the synchronized value of:
■ DAT[1] Interrupt Input for SD Mode
■ DAT[2] Interrupt Input for UHS-II Mode

Values:
■ 0x0 (FALSE): No Card Interrupt
■ 0x1 (TRUE): Generate Card Interrupt
Value After Reset: 0x0
Exists: Always
Volatile: true

7 CARD_REMOVAL R/W1C Card Removal

This bit is set if the Card Inserted in the Present State
register changes from 1 to 0.
Values:
■ 0x0 (FALSE): Card state stable or Debouncing
■ 0x1 (TRUE): Card Removed
Value After Reset: 0x0
Exists: Always
Volatile: true

6 CARD_INSERTION R/W1C Card Insertion

This bit is set if the Card Inserted in the Present State
register changes from 0 to 1.
Values:
■ 0x0 (FALSE): Card state stable or Debouncing
■ 0x1 (TRUE): Card Inserted
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-25 Fields for Register: NORMAL_INT_STAT_R (Continued)

Memory
Bits Name Access Description

5 BUF_RD_READY R/W1C Buffer Read Ready

This bit is set if the Buffer Read Enable changes from 0 to 1.
Values:
■ 0x0 (FALSE): Not ready to read buffer
■ 0x1 (TRUE): Ready to read buffer
Value After Reset: 0x0
Exists: Always
Volatile: true

4 BUF_WR_READY R/W1C Buffer Write Ready

This bit is set if the Buffer Write Enable changes from 0 to 1.
Values:
■ 0x0 (FALSE): Not ready to write buffer
■ 0x1 (TRUE): Ready to write buffer
Value After Reset: 0x0
Exists: Always
Volatile: true

3 DMA_INTERRUPT R/W1C DMA Interrupt

This bit is set if the Host Controller detects the SDMA Buffer
Boundary during transfer. In case of ADMA, by setting the Int
field in the descriptor table, the Host controller generates this
interrupt. This interrupt is not generated after a Transfer
Complete.
Values:
■ 0x0 (FALSE): No DMA Interrupt
■ 0x1 (TRUE): DMA Interrupt is generated
Value After Reset: 0x0
Exists: Always
Volatile: true

2 BGAP_EVENT R/W1C Block Gap Event

This bit is set when both read/write transaction is stopped at
block gap due to a Stop at Block Gap Request.
Values:
■ 0x0 (FALSE): No Block Gap Event
■ 0x1 (TRUE): Transaction stopped at block gap
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-25 Fields for Register: NORMAL_INT_STAT_R (Continued)

Memory
Bits Name Access Description

1 XFER_COMPLETE R/W1C Transfer Complete

This bit is set when a read/write transfer and a command
with status busy is completed.
Values:
■ 0x0 (FALSE): Not complete
■ 0x1 (TRUE): Command execution is completed
Value After Reset: 0x0
Exists: Always
Volatile: true

0 CMD_COMPLETE R/W1C Command Complete

In an SD/eMMC Mode, this bit is set when the end bit of a
response except for Auto CMD12 and Auto CMD23. In UHS-
II Mode, this bit is set when response packet is received.
This interrupt is not generated when the Response Interrupt
Disable in Transfer Mode Register is set to 1.
Values:
■ 0x0 (FALSE): No command complete
■ 0x1 (TRUE): Command Complete
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.21 ERROR_INT_STAT_R
■ Name: Error Interrupt Status Register
■ Description: This register enables an interrupt when the Error Interrupt Status Enable is enabled and
at least one of the statuses is set to 1. Writing to 1 clears the bit and writing to 0 retains the bit
unchanged. Signals defined in this register can be enabled by the Error Interrupt Status Enable
register, but not by the Error Interrupt Signal Enable register. More than one status can be cleared
with a single register write. This register is applicable for an SD/eMMC/UHS-II mode.
■ Size: 16 bits
■ Offset: 0x32
■ Exists: Always
15
14
13
12
11
10
9
8
7
DATA_END_BIT_ERR 6
5
4
3
2
1
0
CMD_END_BIT_ERR
DATA_TOUT_ERR
AUTO_CMD_ERR

CMD_TOUT_ERR
BOOT_ACK_ERR

DATA_CRC_ERR

CMD_CRC_ERR
VENDOR_ERR3
VENDOR_ERR2
VENDOR_ERR1

CUR_LMT_ERR

CMD_IDX_ERR
TUNING_ERR
ADMA_ERR
RESP_ERR

Table 5-26 Fields for Register: ERROR_INT_STAT_R

Memory
Bits Name Access Description

15 VENDOR_ERR3 R/W1C This bit (VENDOR_ERR3) of the ERROR_INT_STAT_R

register is reserved. It always returns 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

14 VENDOR_ERR2 R/W1C This bit (VENDOR_ERR2) of the ERROR_INT_STAT_R

register is reserved. It always returns 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

13 VENDOR_ERR1 R/W1C This bit (VENDOR_ERR1) of the ERROR_INT_STAT_R

register is reserved. It always returns 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-26 Fields for Register: ERROR_INT_STAT_R (Continued)

Memory
Bits Name Access Description

12 BOOT_ACK_ERR R/W1C Boot Acknowledgement Error

This bit is set when there is a timeout for boot
acknowledgement or when detecting boot ack status having
a value other than 010. This is applicable only when boot
acknowledgement is expected in eMMC mode.
In SD/UHS-II mode, this bit is irrelevant.
Values:
■ 0x0 (FALSE): No error
■ 0x1 (TRUE): Error
Value After Reset: 0x0
Exists: Always
Volatile: true

11 RESP_ERR R/W1C Response Error

Host Controller Version 4.00 supports response error check
function to avoid overhead of response error check by Host
Driver during DMA execution. If Response Error Check
Enable is set to 1 in the Transfer Mode register, Host
Controller Checks R1 or R5 response. If an error is detected
in a response, this bit is set to 1.This is applicable in
SD/eMMC mode.
In UHS-II mode, this bit is irrelevant.
Values:
■ 0x0 (FALSE): No error
■ 0x1 (TRUE): Error
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-26 Fields for Register: ERROR_INT_STAT_R (Continued)

Memory
Bits Name Access Description

10 TUNING_ERR R/W1C Tuning Error

This bit is set when an unrecoverable error is detected in a
tuning circuit except during the tuning procedure (occurrence
of an error during tuning procedure is indicated by Sampling
Clock Select in the Host Control 2 register). By detecting
Tuning Error, Host Driver needs to abort a command
executing and perform tuning. To reset tuning circuit,
Sampling Clock Select is set to 0 before executing tuning
procedure. The Tuning Error is higher priority than the other
error interrupts generated during data transfer. By detecting
Tuning Error, the Host Driver must discard data transferred
by a current read/write command and retry data transfer after
the Host Controller retrieved from the tuning circuit error.
This is applicable in SD/eMMC mode.
In UHS-II mode, this bit is irrelevant.
Values:
■ 0x0 (FALSE): No error
■ 0x1 (TRUE): Error
Value After Reset: 0x0
Exists: Always
Volatile: true

9 ADMA_ERR R/W1C ADMA Error

This bit is set when the Host Controller detects error during
ADMA-based data transfer. The error could be due to
following reasons:
■ Error response received from System bus (Master I/F)
■ ADMA3,ADMA2 Descriptors invalid
■ CQE Task or Transfer descriptors invalid
When the error occurs, the state of the ADMA is saved in the
ADMA Error Status register.
In eMMC CQE mode:
The Host Controller generates this Interrupt when it detects
an invalid descriptor data (Valid=0) at the ST_FDS state.
ADMA Error State in the ADMA Error Status indicates that
an error has occurred in ST_FDS state. The Host Driver may
find that Valid bit is not set at the error descriptor.
Values:
■ 0x0 (FALSE): No error
■ 0x1 (TRUE): Error
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-26 Fields for Register: ERROR_INT_STAT_R (Continued)

Memory
Bits Name Access Description

8 AUTO_CMD_ERR R/W1C Auto CMD Error

This error status is used by Auto CMD12 and Auto CMD23 in
SD/eMMC mode. This bit is set when detecting that any of
the bits D00 to D05 in Auto CMD Error Status register has
changed from 0 to 1. D07 is effective in case of Auto CMD12.
Auto CMD Error Status register is valid while this bit is set to
1 and may be cleared by clearing of this bit.
In UHS-II mode, this bit is irrelevant.
Values:
■ 0x0 (FALSE): No error
■ 0x1 (TRUE): Error
Value After Reset: 0x0
Exists: Always
Volatile: true

7 CUR_LMT_ERR R/W1C Current Limit Error

By setting the SD Bus Power bit in the Power Control
register, the Host Controller is requested to supply power for
the SD Bus. If the Host Controller supports the Current Limit
function, it can be protected from an illegal card by stopping
power supply to the card in which case this bit indicates a
failure status. A reading of 1 for this bit means that the Host
Controller is not supplying power to the SD card due to some
failure. A reading of 0 for this bit means that the Host
Controller is supplying power and no error has occurred. The
Host Controller may require some sampling time to detect
the current limit. DWC_mshc Host Controller does not
support this function, this bit is always set to 0.
Values:
■ 0x0 (FALSE): No error
■ 0x1 (TRUE): Power Fail
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-26 Fields for Register: ERROR_INT_STAT_R (Continued)

Memory
Bits Name Access Description

6 DATA_END_BIT_ERR R/W1C Data End Bit Error

This error occurs in SD/eMMC mode either when detecting 0
at the end bit position of read data that uses the DAT line or
at the end bit position of the CRC status.
In UHS-II mode, this bit is irrelevant.
Values:
■ 0x0 (FALSE): No error
■ 0x1 (TRUE): Error
Value After Reset: 0x0
Exists: Always
Volatile: true

5 DATA_CRC_ERR R/W1C Data CRC Error

This error occurs in SD/eMMC mode when detecting CRC
error when transferring read data which uses the DAT line,
when detecting the Write CRC status having a value of other
than 010 or when write CRC status timeout.
In UHS-II mode, this bit is irrelevant.
Values:
■ 0x0 (FALSE): No error
■ 0x1 (TRUE): Error
Value After Reset: 0x0
Exists: Always
Volatile: true

4 DATA_TOUT_ERR R/W1C Data Timeout Error

This bit is set in SD/eMMC mode when detecting one of the
following timeout conditions:
■ Busy timeout for R1b, R5b type
■ Busy timeout after Write CRC status
■ Write CRC Status timeout
■ Read Data timeout

In UHS-II mode, this bit is irrelevant.

Values:
■ 0x0 (FALSE): No error
■ 0x1 (TRUE): Time out
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-26 Fields for Register: ERROR_INT_STAT_R (Continued)

Memory
Bits Name Access Description

3 CMD_IDX_ERR R/W1C Command Index Error

This bit is set if a Command Index error occurs in the
command respons in SD/eMMC mode.
In UHS-II mode, this bit is irrelevant.
Values:
■ 0x0 (FALSE): No error
■ 0x1 (TRUE): Error
Value After Reset: 0x0
Exists: Always
Volatile: true

2 CMD_END_BIT_ERR R/W1C Command End Bit Error

This bit is set when detecting that the end bit of a command
response is 0 in SD/eMMC mode.
In UHS-II mode, this bit is irrelevant.
Values:
■ 0x0 (FALSE): No error
■ 0x1 (TRUE): End Bit error generated
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-26 Fields for Register: ERROR_INT_STAT_R (Continued)

Memory
Bits Name Access Description

1 CMD_CRC_ERR R/W1C Command CRC Error

Command CRC Error is generated in SD/eMMC mode for
following two cases.
■ If a response is returned and the Command Timeout
Error is set to 0 (indicating no timeout), this bit is set to 1
when detecting a CRC error in the command response.
■ The Host Controller detects a CMD line conflict by
monitoring the CMD line when a command is issued. If
the Host Controller drives the CMD line to 1 level, but
detects 0 level on the CMD line at the next SD clock
edge, then the Host Controller aborts the command (stop
driving CMD line) and set this bit to 1. The Command
Timeout Error is also set to 1 to distinguish a CMD line
conflict.

In UHS-II mode, this bit is irrelevant.

Values:
■ 0x0 (FALSE): No error
■ 0x1 (TRUE): CRC error generated
Value After Reset: 0x0
Exists: Always
Volatile: true

0 CMD_TOUT_ERR R/W1C Command Timeout Error

In SD/eMMC Mode,this bit is set only if no response is
returned within 64 SD clock cycles from the end bit of the
command. If the Host Controller detects a CMD line conflict,
along with Command CRC Error bit, this bit is set to 1,
without waiting for 64 SD/eMMC card clock cycles. In UHS-II
mode, this bit is irrelevant.
Values:
■ 0x0 (FALSE): No error
■ 0x1 (TRUE): Time out
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.22 NORMAL_INT_STAT_EN_R
■ Name: Normal Interrupt Status Enable Register
■ Description: This register enables the Interrupt Status for Normal Interrupt Status register
(NORMAL_INT_STAT_R) when NORMAL_INT_STAT_R is set to 1. This register is applicable for an
SD/eMMC/UHS-II mode.
■ Size: 16 bits
■ Offset: 0x34
■ Exists: Always
15
14
13
12
11
10
9
CARD_INTERRUPT_STAT_EN 8
7
6
5
4
3
2
1
0
CARD_INSERTION_STAT_EN

XFER_COMPLETE_STAT_EN
RE_TUNE_EVENT_STAT_EN

DMA_INTERRUPT_STAT_EN

CMD_COMPLETE_STAT_EN
CARD_REMOVAL_STAT_EN

BUF_WR_READY_STAT_EN
BUF_RD_READY_STAT_EN

BGAP_EVENT_STAT_EN
CQE_EVENT_STAT_EN
FX_EVENT_STAT_EN

INT_C_STAT_EN
INT_B_STAT_EN
INT_A_STAT_EN
RSVD_15

Table 5-27 Fields for Register: NORMAL_INT_STAT_EN_R

Memory
Bits Name Access Description

15 RSVD_15 R This bit of the NORMAL_INT_STAT_EN_R register is

reserved. It always returns 0.
Value After Reset: 0x0
Exists: Always

14 CQE_EVENT_STAT_EN R/W CQE Event Status Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

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Table 5-27 Fields for Register: NORMAL_INT_STAT_EN_R (Continued)

Memory
Bits Name Access Description

13 FX_EVENT_STAT_EN R/W FX Event Status Enable

This bit is added from Version 4.10.
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

12 RE_TUNE_EVENT_STAT_EN R/W Re-Tuning Event (UHS-I only) Status Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

11 INT_C_STAT_EN R/W INT_C (Embedded) Status Enable

If this bit is set to 0, the Host Controller clears the interrupt
request to the System. The Host Driver may clear this bit
before servicing the INT_C and may set this bit again after all
interrupt requests to INT_C pin are cleared to prevent
inadvertent interrupts.
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

10 INT_B_STAT_EN R/W INT_B (Embedded) Status Enable

If this bit is set to 0, the Host Controller clears the interrupt
request to the System. The Host Driver may clear this bit
before servicing the INT_B and may set this bit again after all
interrupt requests to INT_B pin are cleared to prevent
inadvertent interrupts.
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

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Table 5-27 Fields for Register: NORMAL_INT_STAT_EN_R (Continued)

Memory
Bits Name Access Description

9 INT_A_STAT_EN R/W INT_A (Embedded) Status Enable

If this bit is set to 0, the Host Controller clears the interrupt
request to the System. The Host Driver may clear this bit
before servicing the INT_A and may set this bit again after all
interrupt requests to INT_A pin are cleared to prevent
inadvertent interrupts.
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

8 CARD_INTERRUPT_STAT_EN R/W Card Interrupt Status Enable

If this bit is set to 0, the Host Controller clears the interrupt
request to the System. The Card Interrupt detection is
stopped when this bit is cleared and restarted when this bit is
set to 1. The Host Driver may clear the Card Interrupt Status
Enable before servicing the Card Interrupt and may set this
bit again after all interrupt requests from the card are cleared
to prevent inadvertent interrupts.
By setting this bit to 0, interrupt input must be masked by
implementation so that the interrupt input is not affected by
external signal in any state (for example, floating).
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

7 CARD_REMOVAL_STAT_EN R/W Card Removal Status Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

6 CARD_INSERTION_STAT_EN R/W Card Insertion Status Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

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Table 5-27 Fields for Register: NORMAL_INT_STAT_EN_R (Continued)

Memory
Bits Name Access Description

5 BUF_RD_READY_STAT_EN R/W Buffer Read Ready Status Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

4 BUF_WR_READY_STAT_EN R/W Buffer Write Ready Status Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

3 DMA_INTERRUPT_STAT_EN R/W DMA Interrupt Status Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

2 BGAP_EVENT_STAT_EN R/W Block Gap Event Status Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

1 XFER_COMPLETE_STAT_EN R/W Transfer Complete Status Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

0 CMD_COMPLETE_STAT_EN R/W Command Complete Status Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

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5.1.23 ERROR_INT_STAT_EN_R
■ Name: Error Interrupt Status Enable Register
■ Description: This register sets the Interrupt Status for Error Interrupt Status register
(ERROR_INT_STAT_R), when ERROR_INT_STAT_EN_R is set to 1. This register is applicable for an
SD/eMMC/UHS-II mode.
■ Size: 16 bits
■ Offset: 0x36
■ Exists: Always
15
14
13
12
11
10
9
8
7
DATA_END_BIT_ERR_STAT_EN 6
5
4
3
2
1
0
CMD_END_BIT_ERR_STAT_EN
DATA_TOUT_ERR_STAT_EN
AUTO_CMD_ERR_STAT_EN

CMD_TOUT_ERR_STAT_EN
BOOT_ACK_ERR_STAT_EN

DATA_CRC_ERR_STAT_EN

CMD_CRC_ERR_STAT_EN
VENDOR_ERR_STAT_EN3
VENDOR_ERR_STAT_EN2
VENDOR_ERR_STAT_EN1

CUR_LMT_ERR_STAT_EN

CMD_IDX_ERR_STAT_EN
TUNING_ERR_STAT_EN
ADMA_ERR_STAT_EN
RESP_ERR_STAT_EN

Table 5-28 Fields for Register: ERROR_INT_STAT_EN_R

Memory
Bits Name Access Description

15 VENDOR_ERR_STAT_EN3 R/W The 15th bit of Error Interrupt Status Enable register is
reserved.
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

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Table 5-28 Fields for Register: ERROR_INT_STAT_EN_R (Continued)

Memory
Bits Name Access Description

14 VENDOR_ERR_STAT_EN2 R/W The 14th bit of Error Interrupt Status Enable register is
reserved.
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

13 VENDOR_ERR_STAT_EN1 R/W The 13th bit of Error Interrupt Status Enable register is
reserved.
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

12 BOOT_ACK_ERR_STAT_EN R/W Boot Acknowledgment Error (eMMC Mode only)

Setting this bit to 1 enables setting of Boot Acknowledgment
Error in Error Interrupt Status register
(ERROR_INT_STAT_R).
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

11 RESP_ERR_STAT_EN R/W Response Error Status Enable (SD Mode only)

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

10 TUNING_ERR_STAT_EN R/W Tuning Error Status Enable (UHS-I Mode only)

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

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Table 5-28 Fields for Register: ERROR_INT_STAT_EN_R (Continued)

Memory
Bits Name Access Description

9 ADMA_ERR_STAT_EN R/W ADMA Error Status Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

8 AUTO_CMD_ERR_STAT_EN R/W Auto CMD Error Status Enable (SD/eMMC Mode only).
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

7 CUR_LMT_ERR_STAT_EN R/W Current Limit Error Status Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

6 DATA_END_BIT_ERR_STAT_EN R/W Data End Bit Error Status Enable (SD/eMMC Mode only).
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

5 DATA_CRC_ERR_STAT_EN R/W Data CRC Error Status Enable (SD/eMMC Mode only)
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

4 DATA_TOUT_ERR_STAT_EN R/W Data Timeout Error Status Enable (SD/eMMC Mode only)
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

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Table 5-28 Fields for Register: ERROR_INT_STAT_EN_R (Continued)

Memory
Bits Name Access Description

3 CMD_IDX_ERR_STAT_EN R/W Command Index Error Status Enable (SD/eMMC Mode only)
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

2 CMD_END_BIT_ERR_STAT_EN R/W Command End Bit Error Status Enable (SD/eMMC Mode
only)
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

1 CMD_CRC_ERR_STAT_EN R/W Command CRC Error Status Enable (SD/eMMC Mode only)
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

0 CMD_TOUT_ERR_STAT_EN R/W Command Timeout Error Status Enable (SD/eMMC Mode

only).
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

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5.1.24 NORMAL_INT_SIGNAL_EN_R
■ Name: Normal Interrupt Signal Enable Register
■ Description: This register is used to select the interrupt status that is indicated to the Host System as
the interrupt. All these status bits share the same 1-bit interrupt line. Setting any of these bits to 1,
enables interrupt generation. This register is applicable for an SD/eMMC/UHS-II mode.
■ Size: 16 bits
■ Offset: 0x38
■ Exists: Always
15
14
13
12
11
10
9
CARD_INTERRUPT_SIGNAL_EN 8
7
6
5
4
3
2
1
0
CARD_INSERTION_SIGNAL_EN

XFER_COMPLETE_SIGNAL_EN
RE_TUNE_EVENT_SIGNAL_EN

DMA_INTERRUPT_SIGNAL_EN

CMD_COMPLETE_SIGNAL_EN
CARD_REMOVAL_SIGNAL_EN

BUF_WR_READY_SIGNAL_EN
BUF_RD_READY_SIGNAL_EN

BGAP_EVENT_SIGNAL_EN
CQE_EVENT_SIGNAL_EN
FX_EVENT_SIGNAL_EN

INT_C_SIGNAL_EN
INT_B_SIGNAL_EN
INT_A_SIGNAL_EN
RSVD_15

Table 5-29 Fields for Register: NORMAL_INT_SIGNAL_EN_R

Memory
Bits Name Access Description

15 RSVD_15 R This bit of the NORMAL_INT_STAT_R register is reserved. It

always returns 0.
Value After Reset: 0x0
Exists: Always

14 CQE_EVENT_SIGNAL_EN R/W Command Queuing Engine Event Signal Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

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Table 5-29 Fields for Register: NORMAL_INT_SIGNAL_EN_R (Continued)

Memory
Bits Name Access Description

13 FX_EVENT_SIGNAL_EN R/W FX Event Signal Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

12 RE_TUNE_EVENT_SIGNAL_EN R/W Re-Tuning Event (UHS-I only) Signal Enable.

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

11 INT_C_SIGNAL_EN R/W INT_C (Embedded) Signal Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

10 INT_B_SIGNAL_EN R/W INT_B (Embedded) Signal Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

9 INT_A_SIGNAL_EN R/W INT_A (Embedded) Signal Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

8 CARD_INTERRUPT_SIGNAL_EN R/W Card Interrupt Signal Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

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Table 5-29 Fields for Register: NORMAL_INT_SIGNAL_EN_R (Continued)

Memory
Bits Name Access Description

7 CARD_REMOVAL_SIGNAL_EN R/W Card Removal Signal Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

6 CARD_INSERTION_SIGNAL_EN R/W Card Insertion Signal Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

5 BUF_RD_READY_SIGNAL_EN R/W Buffer Read Ready Signal Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

4 BUF_WR_READY_SIGNAL_EN R/W Buffer Write Ready Signal Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

3 DMA_INTERRUPT_SIGNAL_EN R/W DMA Interrupt Signal Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

2 BGAP_EVENT_SIGNAL_EN R/W Block Gap Event Signal Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

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Table 5-29 Fields for Register: NORMAL_INT_SIGNAL_EN_R (Continued)

Memory
Bits Name Access Description

1 XFER_COMPLETE_SIGNAL_EN R/W Transfer Complete Signal Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

0 CMD_COMPLETE_SIGNAL_EN R/W Command Complete Signal Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

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5.1.25 ERROR_INT_SIGNAL_EN_R
■ Name: Error Interrupt Signal Enable Register
■ Description: This register is used to select the interrupt status that is notified to the Host System as
an interrupt. All these status bits share the same 1-bit interrupt line. Setting any of these bits to 1
enables interrupt generation. This register is applicable for an SD/eMMC/UHS-II mode.
■ Size: 16 bits
■ Offset: 0x3a
■ Exists: Always
15
14
13
12
11
10
9
8
7
DATA_END_BIT_ERR_SIGNAL_EN 6
5
4
3
2
1
0
CMD_END_BIT_ERR_SIGNAL_EN
DATA_TOUT_ERR_SIGNAL_EN
AUTO_CMD_ERR_SIGNAL_EN

CMD_TOUT_ERR_SIGNAL_EN
BOOT_ACK_ERR_SIGNAL_EN

DATA_CRC_ERR_SIGNAL_EN

CMD_CRC_ERR_SIGNAL_EN
VENDOR_ERR_SIGNAL_EN3
VENDOR_ERR_SIGNAL_EN2
VENDOR_ERR_SIGNAL_EN1

CUR_LMT_ERR_SIGNAL_EN

CMD_IDX_ERR_SIGNAL_EN
TUNING_ERR_SIGNAL_EN
ADMA_ERR_SIGNAL_EN
RESP_ERR_SIGNAL_EN

Table 5-30 Fields for Register: ERROR_INT_SIGNAL_EN_R

Memory
Bits Name Access Description

15 VENDOR_ERR_SIGNAL_EN3 R/W The 16th bit of Error Interrupt Signal Enable is reserved.
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

14 VENDOR_ERR_SIGNAL_EN2 R/W The 15th bit of Error Interrupt Signal Enable is reserved.
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

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Table 5-30 Fields for Register: ERROR_INT_SIGNAL_EN_R (Continued)

Memory
Bits Name Access Description

13 VENDOR_ERR_SIGNAL_EN1 R/W The 14th bit of Error Interrupt Signal Enable is reserved.
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

12 BOOT_ACK_ERR_SIGNAL_EN R/W Boot Acknowledgment Error (eMMC Mode only).

Setting this bit to 1 enables generating interrupt signal when
Boot Acknowledgement Error in Error Interrupt Status
register is set.
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

11 RESP_ERR_SIGNAL_EN R/W Response Error Signal Enable (SD Mode only)

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

10 TUNING_ERR_SIGNAL_EN R/W Tuning Error Signal Enable (UHS-I Mode only)

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

9 ADMA_ERR_SIGNAL_EN R/W ADMA Error Signal Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

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Table 5-30 Fields for Register: ERROR_INT_SIGNAL_EN_R (Continued)

Memory
Bits Name Access Description

8 AUTO_CMD_ERR_SIGNAL_EN R/W Auto CMD Error Signal Enable (SD/eMMC Mode only)
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

7 CUR_LMT_ERR_SIGNAL_EN R/W Current Limit Error Signal Enable

Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

6 DATA_END_BIT_ERR_SIGNAL_ R/W Data End Bit Error Signal Enable (SD/eMMC Mode only)
EN Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

5 DATA_CRC_ERR_SIGNAL_EN R/W Data CRC Error Signal Enable (SD/eMMC Mode only)
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

4 DATA_TOUT_ERR_SIGNAL_EN R/W Data Timeout Error Signal Enable (SD/eMMC Mode only)
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

3 CMD_IDX_ERR_SIGNAL_EN R/W Command Index Error Signal Enable (SD/eMMC Mode only)
Values:
■ 0x0 (FALSE): No error
■ 0x1 (TRUE): Error
Value After Reset: 0x0
Exists: Always

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Table 5-30 Fields for Register: ERROR_INT_SIGNAL_EN_R (Continued)

Memory
Bits Name Access Description

2 CMD_END_BIT_ERR_SIGNAL_E R/W Command End Bit Error Signal Enable (SD/eMMC Mode
N only)
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

1 CMD_CRC_ERR_SIGNAL_EN R/W Command CRC Error Signal Enable (SD/eMMC Mode only)
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

0 CMD_TOUT_ERR_SIGNAL_EN R/W Command Timeout Error Signal Enable (SD/eMMC Mode

only)
Values:
■ 0x0 (FALSE): Masked
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

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5.1.26 AUTO_CMD_STAT_R
■ Name: Auto CMD Status Register
■ Description: This register is used to indicate the CMD12 response error of Auto CMD12, and the
CMD23 response error of Auto CMD23. The Host driver can determine the kind of Auto
CMD12/CMD23 errors that can occur in this register. Auto CMD23 errors are indicated in bit 04-01.
This register is valid only when Auto CMD Error is set. This register is applicable for an SD/eMMC
mode.
■ Size: 16 bits
■ Offset: 0x3c
■ Exists: (DWC_MSHC_SD_EMMC_SUPPORT==1)
15:8
CMD_NOT_ISSUED_AUTO_CMD12 7
6
5
4
3
2
1
0
AUTO_CMD12_NOT_EXEC
AUTO_CMD_RESP_ERR

AUTO_CMD_TOUT_ERR
AUTO_CMD_EBIT_ERR
AUTO_CMD_CRC_ERR
AUTO_CMD_IDX_ERR
RSVD_15_8

RSVD_6

Table 5-31 Fields for Register: AUTO_CMD_STAT_R

Memory
Bits Name Access Description

15:8 RSVD_15_8 R These bits of the AUTO_CMD_STAT_R register are reserved

bits. They always return 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-31 Fields for Register: AUTO_CMD_STAT_R (Continued)

Memory
Bits Name Access Description

7 CMD_NOT_ISSUED_AUTO_CM R Command Not Issued By Auto CMD12 Error

D12 If this bit is set to 1, CMD_wo_DAT is not executed due to an
Auto CMD12 Error (D04-D01) in this register.
This bit is set to 0 when Auto CMD Error is generated by
Auto CMD23.
Values:
■ 0x1 (TRUE): Not Issued
■ 0x0 (FALSE): No Error
Value After Reset: 0x0
Exists: Always
Volatile: true

6 RSVD_6 R This bit of the AUTO_CMD_STAR_R register is reserved. It

always returns 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

5 AUTO_CMD_RESP_ERR R Auto CMD Response Error

This bit is set when Response Error Check Enable in the
Transfer Mode register is set to 1 and an error is detected in
R1 response of either Auto CMD12 or CMD13. This status is
ignored if any bit between D00 to D04 is set to 1.
Values:
■ 0x1 (TRUE): Error
■ 0x0 (FALSE): No Error
Value After Reset: 0x0
Exists: Always
Volatile: true

4 AUTO_CMD_IDX_ERR R Auto CMD Index Error

This bit is set if the command index error occurs in response
to a command.
Values:
■ 0x1 (TRUE): Error
■ 0x0 (FALSE): No Error
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-31 Fields for Register: AUTO_CMD_STAT_R (Continued)

Memory
Bits Name Access Description

3 AUTO_CMD_EBIT_ERR R Auto CMD End Bit Error

This bit is set when detecting that the end bit of command
response is 0.
Values:
■ 0x1 (TRUE): End Bit Error Generated
■ 0x0 (FALSE): No Error
Value After Reset: 0x0
Exists: Always
Volatile: true

2 AUTO_CMD_CRC_ERR R Auto CMD CRC Error

This bit is set when detecting a CRC error in the command
response.
Values:
■ 0x1 (TRUE): CRC Error Generated
■ 0x0 (FALSE): No Error
Value After Reset: 0x0
Exists: Always
Volatile: true

1 AUTO_CMD_TOUT_ERR R Auto CMD Timeout Error

This bit is set if no response is returned with 64 SDCLK
cycles from the end bit of the command.
If this bit is set to 1, error status bits (D04-D01) are
meaningless.
Values:
■ 0x1 (TRUE): Time out
■ 0x0 (FALSE): No Error
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-31 Fields for Register: AUTO_CMD_STAT_R (Continued)

Memory
Bits Name Access Description

0 AUTO_CMD12_NOT_EXEC R Auto CMD12 Not Executed

If multiple memory block data transfer is not started due to a
command error, this bit is not set because it is not necessary
to issue an Auto CMD12. Setting this bit to 1 means that the
Host Controller cannot issue Auto CMD12 to stop multiple
memory block data transfer, due to some error. If this bit is
set to 1, error status bits (D04-D01) is meaningless.
This bit is set to 0 when Auto CMD Error is generated by
Auto CMD23.
Values:
■ 0x1 (TRUE): Not Executed
■ 0x0 (FALSE): Executed
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.27 HOST_CTRL2_R
■ Name: Host Control 2 Register
■ Description: This register is used to control how the Host Controller operates. This register is
applicable for an SD/eMMC/UHS-II mode.
■ Size: 16 bits
■ Offset: 0x3e
■ Exists: Always

5:4

2:0
PRESET_VAL_ENABLE 15
14
13
12
11
10
9
8
7
6

3
DRV_STRENGTH_SEL
HOST_VER4_ENABLE
ASYNC_INT_ENABLE

ADMA2_LEN_MODE

SAMPLE_CLK_SEL
UHS2_IF_ENABLE

UHS_MODE_SEL
CMD23_ENABLE

SIGNALING_EN
EXEC_TUNING
ADDRESSING

RSVD_9

Table 5-32 Fields for Register: HOST_CTRL2_R

Memory
Bits Name Access Description

15 PRESET_VAL_ENABLE R/W Preset Value Enable

This bit enables automatic selection of SDCLK frequency
and Driver strength Preset Value registers. When Preset
Value Enable is set, SDCLK frequency generation
(Frequency Select and Clock Generator Select) and the
driver strength selection are performed by the controller.
These values are selected from set of Preset Value registers
based on selected speed mode.
Note: For more information, see the FAQ on Preset Register
in the DWC_mshc Databook.
Values:
■ 0x0 (FALSE): SDCLK and Driver Strength are controlled
by Host Driver
■ 0x1 (TRUE): Automatic Selection by Preset Value are
Enabled
Value After Reset: 0x0
Exists: Always

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Table 5-32 Fields for Register: HOST_CTRL2_R (Continued)

Memory
Bits Name Access Description

14 ASYNC_INT_ENABLE R/W Asynchronous Interrupt Enable

This bit can be set if a card supports asynchronous
interrupts and Asynchronous Interrupt Support is set to 1 in
the Capabilities register.
Values:
■ 0x0 (FALSE): Disabled
■ 0x1 (TRUE): Enabled
Value After Reset: 0x0
Exists: Always

13 ADDRESSING R/W 64-bit Addressing

This bit is effective when Host Version 4 Enable is set to 1.
Values:
■ 0x0 (FALSE): 32 bits addressing
■ 0x1 (TRUE): 64 bits addressing
Value After Reset: 0x0
Exists: Always

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Table 5-32 Fields for Register: HOST_CTRL2_R (Continued)

Memory
Bits Name Access Description

12 HOST_VER4_ENABLE R/W Host Version 4 Enable

This bit selects either Version 3.00 compatible mode or
Version 4 mode.
Functions of following fields are modified for Host Version 4
mode:
■ SDMA Address: SDMA uses ADMA System Address
(05Fh-058h) instead of SDMA System Address register
(003h-000h)
■ ADMA2/ADMA3 selection: ADMA3 is selected by DMA
select in Host Control 1 register
■ 64-bit ADMA Descriptor Size: 128-bit descriptor is used
instead of 96-bit descriptor when 64-bit Addressing is set
to 1
■ Selection of 32-bit/64-bit System Addressing: Either 32-
bit or 64-bit system addressing is selected by 64-bit
Addressing bit in this register
■ 32-bit Block Count: SDMA System Address register
(003h-000h) is modified to 32-bit Block Count register

Note: It is recommended not to program ADMA3 Integrated

Descriptor Address registers, UHS-II registers and
Command Queuing registers (if applicable) while operating
in Host version less than 4 mode (Host Version 4 Enable =
0).
Values:
■ 0x0 (FALSE): Version 3.00 compatible mode
■ 0x1 (TRUE): Version 4 mode
Value After Reset: 0x0
Exists: Always

11 CMD23_ENABLE R/W CMD23 Enable

If the card supports CMD23, this bit is set to 1. This bit is
used to select Auto CMD23 or Auto CMD12 for ADMA3 data
transfer.
Values:
■ 0x0 (FALSE): Auto CMD23 is disabled
■ 0x1 (TRUE): Auto CMD23 is enabled
Value After Reset: 0x0
Exists: Always

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Table 5-32 Fields for Register: HOST_CTRL2_R (Continued)

Memory
Bits Name Access Description

10 ADMA2_LEN_MODE R/W ADMA2 Length Mode

This bit selects ADMA2 Length mode to be either 16-bit or
26-bit.
Values:
■ 0x0 (FALSE): 16-bit Data Length Mode
■ 0x1 (TRUE): 26-bit Data Length Mode
Value After Reset: 0x0
Exists: Always

9 RSVD_9 R This bit of the HOST_CTRL2_R register is reserved. It

always returns 0.
Value After Reset: 0x0
Exists: Always

8 UHS2_IF_ENABLE R/W UHS-II Interface Enable

This bit is used to enable the UHS-II Interface. The value is
reflected on the uhs2_if_en pin.
Values:
■ 0x0 (FALSE): SD/eMMC Interface Enabled
■ 0x1 (TRUE): UHS-II Interface Enabled
Value After Reset: 0x0
Exists: Always

7 SAMPLE_CLK_SEL R/W Sampling Clock Select

This bit is used by the Host Controller to select the sampling
clock in SD/eMMC mode to receive CMD and DAT. This bit is
set by the tuning procedure and is valid after the completion
of tuning (when Execute Tuning is cleared). Setting this bit to
1 means that tuning is completed successfully and setting
this bit to 0 means that tuning has failed. The value is
reflected on the sample_cclk_sel pin.This bit is irrelevant in
UHS-II mode
Values:
■ 0x0 (FALSE): Fixed clock is used to sample data
■ 0x1 (TRUE): Tuned clock is used to sample data
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-32 Fields for Register: HOST_CTRL2_R (Continued)

Memory
Bits Name Access Description

6 EXEC_TUNING R/W Execute Tuning

This bit is set to 1 to start the tuning procedure in UHS-
I/eMMC speed modes and this bit is automatically cleared
when tuning procedure is completed.This bit is irrelevant in
UHS-II mode
Values:
■ 0x0 (FALSE): Not Tuned or Tuning completed
■ 0x1 (TRUE): Execute Tuning
Value After Reset: 0x0
Exists: Always
Volatile: true

5:4 DRV_STRENGTH_SEL R/W Driver Strength Select

This bit is used to select the Host Controller output driver in
1.8V signaling UHS-I/eMMC speed modes. The bit depends
on setting of Preset Value Enable. The value is reflected on
the uhs1_drv_sth pin.This bit is irrelevant in UHS-II mode
Values:
■ 0x0 (TYPEB): Driver TYPEB is selected
■ 0x1 (TYPEA): Driver TYPEA is selected
■ 0x2 (TYPEC): Driver TYPEC is selected
■ 0x3 (TYPED): Driver TYPED is selected
Value After Reset: 0x0
Exists: Always
Volatile: true

3 SIGNALING_EN R/W 1.8V Signaling Enable

This bit controls voltage regulator for I/O cell in UHS-I/eMMC
speed modes. Setting this bit from 0 to 1 starts changing the
signal voltage from 3.3V to 1.8V. Host Controller clears this
bit if switching to 1.8 signaling fails. The value is reflected on
the uhs1_swvolt_en pin.This bit shall be set to 0 in UHS-II
mode
Note: This bit must be set for all UHS-I speed modes
(SDR12/SDR25/SDR50/SDR104/DDR50).
Values:
■ 0x0 (V_3_3): 3.3V Signalling
■ 0x1 (V_1_8): 1.8V Signalling
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-32 Fields for Register: HOST_CTRL2_R (Continued)

Memory
Bits Name Access Description

2:0 UHS_MODE_SEL R/W UHS Mode/eMMC Speed Mode Select

These bits are used to select UHS mode in the SD mode of
operation. In eMMC mode, these bits are used to select
eMMC Speed mode.

UHS Mode (SD/UHS-II mode only):

■ 0x0: SDR12
■ 0x1: SDR25
■ 0x2: SDR50
■ 0x3: SDR104
■ 0x4: DDR50
■ 0x5: Reserved
■ 0x6: Reserved
■ 0x7: UHS-II
eMMC Speed Mode (eMMC mode only):
■ 0x0: Legacy
■ 0x1: High Speed SDR
■ 0x2: Reserved
■ 0x3: HS200
■ 0x4: High Speed DDR
■ 0x5: Reserved
■ 0x6: Reserved
■ 0x7: HS400

Values:
■ 0x0 (SDR12): SDR12/Legacy
■ 0x1 (SDR25): SDR25/High Speed SDR
■ 0x2 (SDR50): SDR50
■ 0x3 (SDR104): SDR104/HS200
■ 0x4 (DDR50): DDR50/High Speed DDR
■ 0x5 (RSVD5): Reserved
■ 0x6 (RSVD6): Reserved
■ 0x7 (UHS2): UHS-II/HS400
Value After Reset: 0x0
Exists: Always

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5.1.28 CAPABILITIES1_R
■ Name: Capabilities 1 Register - 0 to 31
■ Description: This register provides the Host Driver with information specific to the Host Controller
implementation. The host controller may implement these values as fixed or loaded from the flash
memory during power on initialization. Capabilities register is segregated into two 32-bit registers:
CAPABILITIES1_R and CAPABILITIES2_R. The CAPABILITIES1_R register is the lower part of
Capabilities register.
■ Size: 32 bits
■ Offset: 0x40
■ Exists: Always
31:30

17:16
15:8

5:0
29
28
27
26
25
24
23
22
HIGH_SPEED_SUPPORT 21
20
19
18

7
6
ASYNC_INT_SUPPORT

SUS_RES_SUPPORT
SYS_ADDR_64_V3
SYS_ADDR_64_V4

ADMA2_SUPPORT

TOUT_CLK_FREQ
BASE_CLK_FREQ
SDMA_SUPPORT

TOUT_CLK_UNIT
Embedded_8_BIT
MAX_BLK_LEN
SLOT_TYPE_R

RSVD_20
VOLT_18
VOLT_30
VOLT_33

RSVD_6

Table 5-33 Fields for Register: CAPABILITIES1_R

Memory
Bits Name Access Description

31:30 SLOT_TYPE_R R Slot Type

These bits indicate usage of a slot by a specific Host
System.
Values:
■ 0x0 (REMOVABLE_SLOT): Removable Card Slot
■ 0x1 (EMBEDDED_SLOT): Embedded Slot for one Device
■ 0x2 (SHARED_SLOT): Shared Bus Slot (SD mode)
■ 0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple
Embedded Devices
Value After Reset: DWC_MSHC_SLOT_TYPE
Exists: Always

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Table 5-33 Fields for Register: CAPABILITIES1_R (Continued)

Memory
Bits Name Access Description

29 ASYNC_INT_SUPPORT R Asynchronous Interrupt Support (SD Mode only)

Values:
■ 0x0 (FALSE): Asynchronous Interrupt Not Supported
■ 0x1 (TRUE): Asynchronous Interrupt Supported
Value After Reset: DWC_MSHC_ASYNCINT_SUPPORT
Exists: Always

28 SYS_ADDR_64_V3 R 64-bit System Address Support for V3

This bit sets the Host controller to support 64-bit System
Addressing of V3 mode.
SDMA cannot be used in 64-bit Addressing in Version 3
Mode.
If this bit is set to 1, 64-bit ADMA2 with using 96-bit
Descriptor can be enabled by setting Host Version 4 Enable
(HOST_VER4_ENABLE = 0) and DMA select (DMA_SEL =
11b).
Values:
■ 0x0 (FALSE): 64-bit System Address for V3 is Not
Supported
■ 0x1 (TRUE): 64-bit System Address for V3 is Supported
Value After Reset: DWC_MSHC_ADDR64_V3_SUPPORT
Exists: Always

27 SYS_ADDR_64_V4 R 64-bit System Address Support for V4

This bit sets the Host Controller to support 64-bit System
Addressing of V4 mode. When this bit is set to 1, full or part
of 64-bit address must be used to decode the Host Controller
Registers so that Host Controller Registers can be placed
above system memory area. 64-bit address decode of Host
Controller registers is effective regardless of setting to 64-bit
Addressing in Host Control 2.
If this bit is set to 1, 64-bit DMA Addressing for version 4 is
enabled by setting Host Version 4 Enable
(HOST_VER4_ENABLE = 1) and by setting 64-bit
Addressing (ADDRESSING =1) in the Host Control 2
register. SDMA can be used and ADMA2 uses 128-bit
Descriptor.
Values:
■ 0x0 (FALSE): 64-bit System Address for V4 is Not
Supported
■ 0x1 (TRUE): 64-bit System Address for V4 is Supported
Value After Reset: DWC_MSHC_ADDR64_V4_SUPPORT
Exists: Always

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Table 5-33 Fields for Register: CAPABILITIES1_R (Continued)

Memory
Bits Name Access Description

26 VOLT_18 R Voltage Support for 1.8V

Values:
■ 0x0 (FALSE): 1.8V Not Supported
■ 0x1 (TRUE): 1.8V Supported
Value After Reset:
DWC_MSHC_VOLT18_VDD1_SUPPORT
Exists: Always

25 VOLT_30 R Voltage Support for SD 3.0V or Embedded 1.2V

Values:
■ 0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported
■ 0x1 (TRUE): SD 3.0V or Embedded Supported
Value After Reset:
DWC_MSHC_VOLT30_VDD1_SUPPORT
Exists: Always

24 VOLT_33 R Voltage Support for 3.3V

Values:
■ 0x0 (FALSE): 3.3V Not Supported
■ 0x1 (TRUE): 3.3V Supported
Value After Reset:
DWC_MSHC_VOLT33_VDD1_SUPPORT
Exists: Always

23 SUS_RES_SUPPORT R Suspense/Resume Support

This bit indicates whether the Host Controller supports
Suspend/Resume functionality. If this bit is 0, the Host Driver
does not issue either Suspend or Resume commands
because the Suspend and Resume mechanism is not
supported.
Values:
■ 0x0 (FALSE): Not Supported
■ 0x1 (TRUE): Supported
Value After Reset: DWC_MSHC_SUSRES_SUPPORT
Exists: Always

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Table 5-33 Fields for Register: CAPABILITIES1_R (Continued)

Memory
Bits Name Access Description

22 SDMA_SUPPORT R SDMA Support

This bit indicates whether the Host Controller is capable of
using SDMA to transfer data between the system memory
and the Host Controller directly.
Values:
■ 0x0 (FALSE): SDMA not Supported
■ 0x1 (TRUE): SDMA Supported
Value After Reset: DWC_MSHC_SDMA_SUPPORT
Exists: Always

21 HIGH_SPEED_SUPPORT R High Speed Support

This bit indicates whether the Host Controller and the Host
System supports High Speed mode and they can supply the
SD Clock frequency from 25 MHz to 50 MHz.
Values:
■ 0x0 (FALSE): High Speed not Supported
■ 0x1 (TRUE): High Speed Supported
Value After Reset: DWC_MSHC_HIGHSPD_SUPPORT
Exists: Always

20 RSVD_20 R This bit of the CAPABILITIES1_R is a reserved. It always

returns 0.
Value After Reset: 0x0
Exists: Always

19 ADMA2_SUPPORT R ADMA2 Support

This bit indicates whether the Host Controller is capable of
using ADMA2.
Values:
■ 0x0 (FALSE): ADMA2 not Supported
■ 0x1 (TRUE): ADMA2 Supported
Value After Reset: DWC_MSHC_ADMA2_SUPPORT
Exists: Always

18 Embedded_8_BIT R 8-bit Support for Embedded Device

This bit indicates whether the Host Controller is capable of
using an 8-bit bus width mode. This bit is not effective when
the Slot Type is set to 10b.
Values:
■ 0x0 (FALSE): 8-bit Bus Width not Supported
■ 0x1 (TRUE): 8-bit Bus Width Supported
Value After Reset: DWC_MSHC_BUS_8BIT_SUPPORT
Exists: Always

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Table 5-33 Fields for Register: CAPABILITIES1_R (Continued)

Memory
Bits Name Access Description

17:16 MAX_BLK_LEN R Maximum Block Length

This bit indicates the maximum block size that the Host
driver can read and write to the buffer in the Host Controller.
The buffer transfers this block size without wait cycles. The
transfer block length is always 512 bytes for the SD Memory
irrespective of this bit
Values:
■ 0x0 (ZERO): 512 Byte
■ 0x1 (ONE): 1024 Byte
■ 0x2 (TWO): 2048 Byte
■ 0x3 (THREE): Reserved
Value After Reset: DWC_MSHC_MAX_BLK_SIZE
Exists: Always

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Table 5-33 Fields for Register: CAPABILITIES1_R (Continued)

Memory
Bits Name Access Description

15:8 BASE_CLK_FREQ R Base Clock Frequency for SD clock

These bits indicate the base (maximum) clock frequency for
the SD Clock. The definition of these bits depend on the Host
Controller Version.
■ 6-Bit Base Clock Frequency: This mode is supported by
the Host Controller version 1.00 and 2.00. The upper 2
bits are not effective and are always 0. The unit values
are 1 MHz. The supported clock range is 10 MHz to 63
MHz.
- 0x00 : Get information through another method
- 0x01 : 1 MHz
- 0x02 : 2 MHz
- .............
- 0x3F : 63 MHz
- 0x40-0xFF : Not Supported
■ 8-Bit Base Clock Frequency: This mode is supported by
the Host Controller version 3.00. The unit values are 1
MHz. The supported clock range is 10 MHz to 255 MHz.
- 0x00 : Get information through another method
- 0x01 : 1 MHz
- 0x02 : 2 MHz
- ............
- 0xFF : 255 MHz
If the frequency is 16.5 MHz, the larger value is set to
0001001b (17 MHz) because the Host Driver uses this value
to calculate the clock divider value and it does not exceed
the upper limit of the SD Clock frequency. If these bits are all
0, the Host system has to get information using a different
method.
Value After Reset: DWC_MSHC_BASE_CLK_FREQ_SD
Exists: Always

7 TOUT_CLK_UNIT R Timeout Clock Unit

This bit shows the unit of base clock frequency used to
detect Data TImeout Error.
Values:
■ 0x0 (KHZ): KHz
■ 0x1 (MHZ): MHz
Value After Reset:
DWC_MSHC_TIMER_CLK_FREQ_UNIT
Exists: Always

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Table 5-33 Fields for Register: CAPABILITIES1_R (Continued)

Memory
Bits Name Access Description

6 RSVD_6 R This bit of the CAPABILITIES1_R register is reserved. It

always returns 0.
Value After Reset: 0x0
Exists: Always

5:0 TOUT_CLK_FREQ R Timeout Clock Frequency

This bit shows the base clock frequency used to detect Data
Timeout Error. The Timeout Clock unit defines the unit of
timeout clock frequency. It can be KHz or MHz.
■ 0x00 : Get information through another method
■ 0x01 : 1KHz / 1MHz
■ 0x02 : 2KHz / 2MHz
■ 0x03 : 3KHz / 3MHz
■ ...........
■ 0x3F : 63KHz / 63MHz
Value After Reset: DWC_MSHC_TIMER_CLK_FREQ
Exists: Always

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5.1.29 CAPABILITIES2_R
■ Name: Capabilities Register - 32 to 63
■ Description: This register provides the Host Driver with information specific to the Host Controller
implementation. The host controller may implement these values as fixed or as loaded from flash
memory during power on initialization. Capabilities register is segregated into two 32-bit registers,
namely CAPABILITIES1_R and CAPABILITIES2_R. The CAPABILITIES2_R register is upper part of
Capabilities register.
■ Size: 32 bits
■ Offset: 0x44
■ Exists: Always
31:30

26:24
23:16
15:14

11:8
29
VDD2_18V_SUPPORT 28
27

USE_TUNING_SDR50 13
12

7
6
5
4
3
2
1
0
RE_TUNING_MODES

SDR104_SUPPORT
ADMA3_SUPPORT

DDR50_SUPPORT

SDR50_SUPPORT
UHS2_SUPPORT
RETUNE_CNT
RSVD_62_63

RSVD_56_58

DRV_TYPED
DRV_TYPEC
DRV_TYPEA
CLK_MUL
RSVD_61

RSVD_44

RSVD_39

Table 5-34 Fields for Register: CAPABILITIES2_R

Memory
Bits Name Access Description

31:30 RSVD_62_63 R These bits (RSVD_62_63) of the CAPABILITIES2_R register

are reserved bits. They always return 0.
Value After Reset: 0x0
Exists: Always

29 RSVD_61 R This bit (RSVD_61) of the CAPABILITIES2_R register is

reserved. It always returns 0.
Value After Reset: 0x0
Exists: Always

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Table 5-34 Fields for Register: CAPABILITIES2_R (Continued)

Memory
Bits Name Access Description

28 VDD2_18V_SUPPORT R 1.8V VDD2 Support

This bit indicates support of VDD2 for the Host System.
Values:
■ 0x0 (FALSE): 1.8V VDD2 is not Supported
■ 0x1 (TRUE): 1.8V VDD2 is Supported
Value After Reset:
DWC_MSHC_VOLT18_VDD2_SUPPORT
Exists: Always

27 ADMA3_SUPPORT R ADMA3 Support

This bit indicates whether the Host Controller is capable of
using ADMA3.
Values:
■ 0x0 (FALSE): ADMA3 not Supported
■ 0x1 (TRUE): ADMA3 Supported
Value After Reset: DWC_MSHC_ADMA3_SUPPORT
Exists: Always

26:24 RSVD_56_58 R These bits (RSVD_56_58) of the CAPABILITIES2_R register

are reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

23:16 CLK_MUL R Clock Multiplier

These bits indicate the clock multiplier of the programmable
clock generator. Setting these bits to 0 means that the Host
Controller does not support a programmable clock generator.
■ 0x0: Clock Multiplier is not Supported
■ 0x1: Clock Multiplier M = 2
■ 0x2: Clock Multiplier M = 3
■ .........
■ 0xFF: Clock Multiplier M = 256
Value After Reset: DWC_MSHC_CLK_MULTIPLIER
Exists: Always

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Table 5-34 Fields for Register: CAPABILITIES2_R (Continued)

Memory
Bits Name Access Description

15:14 RE_TUNING_MODES R Re-Tuning Modes (UHS-I only)

These bits select the re-tuning method and limit the
maximum data length.
Values:
■ 0x0 (MODE1): Timer
■ 0x1 (MODE2): Timer and Re-Tuning Request (Not
supported)
■ 0x2 (MODE3): Auto Re-Tuning (for transfer)
■ 0x3 (RSVD_MODE): Reserved
Value After Reset:
(DWC_MSHC_RETUNE_MODE)?0x2:0x0
Exists: Always

13 USE_TUNING_SDR50 R Use Tuning for SDR50 (UHS-I only)

Values:
■ 0x0 (ZERO): SDR50 does not require tuning
■ 0x1 (ONE): SDR50 requires tuning
Value After Reset: DWC_MSHC_TUNE_SDR50_EN
Exists: Always

12 RSVD_44 R This bit (RSVD_44) of the CAPABILITIES2_R register is

reserved. It always returns 0.
Value After Reset: 0x0
Exists: Always

11:8 RETUNE_CNT R Timer Count for Re-Tuning (UHS-I only)

■ 0x0: Re-Tuning Timer disabled
■ 0x1: 1 seconds
■ 0x2: 2 seconds
■ 0x3: 4 seconds
■ ........
■ 0xB: 1024 seconds
■ 0xC: Reserved
■ 0xD: Reserved
■ 0xE: Reserved
■ 0xF: Get information from other source
Value After Reset: DWC_MSHC_RETUNE_TIMER
Exists: Always

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Table 5-34 Fields for Register: CAPABILITIES2_R (Continued)

Memory
Bits Name Access Description

7 RSVD_39 R This bit (RSVD_39) of the CAPABILITIES2_R register is

reserved. It always returns 0.
Value After Reset: 0x0
Exists: Always

6 DRV_TYPED R Driver Type D Support (UHS-I only)

This bit indicates support of Driver Type D for 1.8 Signaling.
Values:
■ 0x0 (FALSE): Driver Type D is not supported
■ 0x1 (TRUE): Driver Type D is supported
Value After Reset:
DWC_MSHC_DRV_TYPE_D_SUPPORT
Exists: Always

5 DRV_TYPEC R Driver Type C Support (UHS-I only)

This bit indicates support of Driver Type C for 1.8 Signaling.
Values:
■ 0x0 (FALSE): Driver Type C is not supported
■ 0x1 (TRUE): Driver Type C is supported
Value After Reset:
DWC_MSHC_DRV_TYPE_C_SUPPORT
Exists: Always

4 DRV_TYPEA R Driver Type A Support (UHS-I only)

This bit indicates support of Driver Type A for 1.8 Signaling.
Values:
■ 0x0 (FALSE): Driver Type A is not supported
■ 0x1 (TRUE): Driver Type A is supported
Value After Reset:
DWC_MSHC_DRV_TYPE_A_SUPPORT
Exists: Always

3 UHS2_SUPPORT R UHS-II Support (UHS-II only)

This bit indicates whether Host Controller supports UHS-II.
Values:
■ 0x0 (FALSE): UHS-II is not supported
■ 0x1 (TRUE): UHS-II is supported
Value After Reset: DWC_MSHC_UHS2_SUPPORT
Exists: Always

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Table 5-34 Fields for Register: CAPABILITIES2_R (Continued)

Memory
Bits Name Access Description

2 DDR50_SUPPORT R DDR50 Support (UHS-I only)

Values:
■ 0x0 (FALSE): DDR50 is not supported
■ 0x1 (TRUE): DDR50 is supported
Value After Reset: DWC_MSHC_DDR50_SUPPORT
Exists: Always

1 SDR104_SUPPORT R SDR104 Support (UHS-I only)

This bit mentions that SDR104 requires tuning.
Values:
■ 0x0 (FALSE): SDR104 is not supported
■ 0x1 (TRUE): SDR104 is supported
Value After Reset: DWC_MSHC_SDR104_SUPPORT
Exists: Always

0 SDR50_SUPPORT R SDR50 Support (UHS-I only)

Thsi bit indicates that SDR50 is supported. The bit 13
(USE_TUNING_SDR50) indicates whether SDR50 requires
tuning or not.
Values:
■ 0x0 (FALSE): SDR50 is not supported
■ 0x1 (TRUE): SDR50 is supported
Value After Reset: DWC_MSHC_SDR50_SUPPORT
Exists: Always

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5.1.30 CURR_CAPABILITIES1_R
■ Name: Maximum Current Capabilities Register - 0 to 31
■ Description: This register indicate the maximum current capability for each voltage, for VDD1. The
value is meaningful if the Voltage Support is set in the Capabilities register. If this information is
supplied by the Host System through another method, all the Maximum Current Capabilities
registers are set to 0.
■ Size: 32 bits
■ Offset: 0x48
■ Exists: Always

31:24
MAX_CUR_18V 23:16
MAX_CUR_30V 15:8
MAX_CUR_33V 7:0
RSVD_31_24

Table 5-35 Fields for Register: CURR_CAPABILITIES1_R

Memory
Bits Name Access Description

31:24 RSVD_31_24 R These bits of the CURR_CAPABILITIES1_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

23:16 MAX_CUR_18V R Maximum Current for 1.8V

This bit specifies the Maximum Current for 1.8V VDD1 power
supply for the card.
■ 0: Get information through another method
■ 1: 4mA
■ 2: 8mA
■ 3: 13mA
■ .......
■ 255: 1020mA
Value After Reset:
DWC_MSHC_MAXCUR_VOLT18_VDD1
Exists: Always

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Table 5-35 Fields for Register: CURR_CAPABILITIES1_R (Continued)

Memory
Bits Name Access Description

15:8 MAX_CUR_30V R Maximum Current for 3.0V

This bit specifies the Maximum Current for 3.0V VDD1 power
supply for the card.
■ 0: Get information through another method
■ 1: 4mA
■ 2: 8mA
■ 3: 13mA
■ .......
■ 255: 1020mA
Value After Reset:
DWC_MSHC_MAXCUR_VOLT30_VDD1
Exists: Always

7:0 MAX_CUR_33V R Maximum Current for 3.3V

This bit specifies the Maximum Current for 3.3V VDD1 power
supply for the card.
■ 0: Get information through another method
■ 1: 4mA
■ 2: 8mA
■ 3: 13mA
■ .......
■ 255: 1020mA
Value After Reset:
DWC_MSHC_MAXCUR_VOLT33_VDD1
Exists: Always

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5.1.31 CURR_CAPABILITIES2_R
■ Name: Maximum Current Capabilities Register - 32 to 63
■ Description: This register indicates the maximum current capability for each voltage (for VDD2). The
value is meaningful if Voltage Support is set in the Capabilities register. If this information is
supplied by the Host System through another method, all the Maximum Current Capabilities
registers are set to 0.
■ Size: 32 bits
■ Offset: 0x4c
■ Exists: Always

31:8
MAX_CUR_VDD2_18V 7:0
RSVD_63_40

Table 5-36 Fields for Register: CURR_CAPABILITIES2_R

Memory
Bits Name Access Description

31:8 RSVD_63_40 R These bits of the CURR_CAPABILITIES2_R register are

reserved. They always return 0.
Reserved Field: Yes
Value After Reset: 0x0
Exists: Always

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Table 5-36 Fields for Register: CURR_CAPABILITIES2_R (Continued)

Memory
Bits Name Access Description

7:0 MAX_CUR_VDD2_18V R Maximum Current for 1.8V VDD2

This bit specifies the Maximum Current for 1.8V VDD2 power
supply for the UHS-II card.
■ 0: Get information through another method
■ 1: 4mA
■ 2: 8mA
■ 3: 13mA
■ .......
■ 255: 1020mA
Value After Reset:
DWC_MSHC_MAXCUR_VOLT18_VDD2
Exists: Always

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5.1.32 FORCE_AUTO_CMD_STAT_R
■ Name: Force Event Register for Auto CMD Error Status register
■ Description: The register is not a physically implemented but is an address at which the Auto CMD
Error Status register can be written.This register is applicable for an SD/eMMC mode.
❑ 1 : Sets each bit of the Auto CMD Error Status register
❑ 0 : No effect
■ Size: 16 bits
■ Offset: 0x50
■ Exists: (DWC_MSHC_SD_EMMC_SUPPORT==1)
15:8
FORCE_CMD_NOT_ISSUED_AUTO_CMD12 7
6
5
4
3
2
1
0
FORCE_AUTO_CMD12_NOT_EXEC
FORCE_AUTO_CMD_RESP_ERR

FORCE_AUTO_CMD_TOUT_ERR
FORCE_AUTO_CMD_EBIT_ERR
FORCE_AUTO_CMD_CRC_ERR
FORCE_AUTO_CMD_IDX_ERR
RSVD_15_8

RSVD_6

Table 5-37 Fields for Register: FORCE_AUTO_CMD_STAT_R

Memory
Bits Name Access Description

15:8 RSVD_15_8 R These bits of the FORCE_AUTO_CMD_STAT_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-37 Fields for Register: FORCE_AUTO_CMD_STAT_R (Continued)

Memory
Bits Name Access Description

7 FORCE_CMD_NOT_ISSUED_AU W Force Event for Command Not Issued By Auto CMD12 Error
TO_CMD12 Values:
■ 0x1 (TRUE): Command Not Issued By Auto CMD12 Error
Status is set
■ 0x0 (FALSE): Not Affected
Value After Reset: 0x0
Exists: Always

6 RSVD_6 R This bit of the FORCE_AUTO_CMD_STAT_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

5 FORCE_AUTO_CMD_RESP_ER W Force Event for Auto CMD Response Error

R Values:
■ 0x1 (TRUE): Auto CMD Response Error Status is set
■ 0x0 (FALSE): Not Affected
Value After Reset: 0x0
Exists: Always

4 FORCE_AUTO_CMD_IDX_ERR W Force Event for Auto CMD Index Error

Values:
■ 0x1 (TRUE): Auto CMD Index Error Status is set
■ 0x0 (FALSE): Not Affected
Value After Reset: 0x0
Exists: Always

3 FORCE_AUTO_CMD_EBIT_ERR W Force Event for Auto CMD End Bit Error

Values:
■ 0x1 (TRUE): Auto CMD End Bit Error Status is set
■ 0x0 (FALSE): Not Affected
Value After Reset: 0x0
Exists: Always

2 FORCE_AUTO_CMD_CRC_ERR W Force Event for Auto CMD CRC Error

Values:
■ 0x1 (TRUE): Auto CMD CRC Error Status is set
■ 0x0 (FALSE): Not Affected
Value After Reset: 0x0
Exists: Always

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Table 5-37 Fields for Register: FORCE_AUTO_CMD_STAT_R (Continued)

Memory
Bits Name Access Description

1 FORCE_AUTO_CMD_TOUT_ER W Force Event for Auto CMD Timeout Error

R Values:
■ 0x1 (TRUE): Auto CMD Timeout Error Status is set
■ 0x0 (FALSE): Not Affected
Value After Reset: 0x0
Exists: Always

0 FORCE_AUTO_CMD12_NOT_EX W Force Event for Auto CMD12 Not Executed

EC Values:
■ 0x1 (TRUE): Auto CMD12 Not Executed Status is set
■ 0x0 (FALSE): Not Affected
Value After Reset: 0x0
Exists: Always

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5.1.33 FORCE_ERROR_INT_STAT_R
■ Name: Force Event Register for Error Interrupt Status
■ Description: This register is not physically implemented but is an address at which the Error
Interrupt Status register can be written. The effect of a write to this address is reflected in the Error
Interrupt Status register if the corresponding bit of the Error Interrupt Status Enable register is set.
This register is applicable for an SD/eMMC/UHS-II mode.
■ Size: 16 bits
■ Offset: 0x52
■ Exists: Always
15
14
13
12
11
10
9
8
7
FORCE_DATA_END_BIT_ERR 6
5
4
3
2
1
0
FORCE_CMD_END_BIT_ERR
FORCE_DATA_TOUT_ERR
FORCE_AUTO_CMD_ERR

FORCE_CMD_TOUT_ERR
FORCE_BOOT_ACK_ERR

FORCE_DATA_CRC_ERR

FORCE_CMD_CRC_ERR
FORCE_VENDOR_ERR3
FORCE_VENDOR_ERR2
FORCE_VENDOR_ERR1

FORCE_CUR_LMT_ERR

FORCE_CMD_IDX_ERR
FORCE_TUNING_ERR
FORCE_ADMA_ERR
FORCE_RESP_ERR

Table 5-38 Fields for Register: FORCE_ERROR_INT_STAT_R

Memory
Bits Name Access Description

15 FORCE_VENDOR_ERR3 W This bit (FORCE_VENDOR_ERR3) of the

FORCE_ERROR_INT_STAT_R register is reserved. It
always returns 0.
Value After Reset: 0x0
Exists: Always

14 FORCE_VENDOR_ERR2 W This bit (FORCE_VENDOR_ERR2) of the

FORCE_ERROR_INT_STAT_R register is reserved. It
always returns 0.
Value After Reset: 0x0
Exists: Always

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Table 5-38 Fields for Register: FORCE_ERROR_INT_STAT_R (Continued)

Memory
Bits Name Access Description

13 FORCE_VENDOR_ERR1 W This bit (FORCE_VENDOR_ERR1) of the

FORCE_ERROR_INT_STAT_R register is reserved. It
always returns 0.
Value After Reset: 0x0
Exists: Always

12 FORCE_BOOT_ACK_ERR W Force Event for Boot Ack error

Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Boot ack Error Status is set
Value After Reset: 0x0
Exists: Always

11 FORCE_RESP_ERR W Force Event for Response Error (SD Mode only)

Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Response Error Status is set
Value After Reset: 0x0
Exists: Always

10 FORCE_TUNING_ERR W Force Event for Tuning Error (UHS-I Mode only)

Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Tuning Error Status is set
Value After Reset: 0x0
Exists: Always

9 FORCE_ADMA_ERR W Force Event for ADMA Error

Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): ADMA Error Status is set
Value After Reset: 0x0
Exists: Always

8 FORCE_AUTO_CMD_ERR W Force Event for Auto CMD Error (SD/eMMC Mode only)
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Auto CMD Error Status is set
Value After Reset: 0x0
Exists: Always

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Table 5-38 Fields for Register: FORCE_ERROR_INT_STAT_R (Continued)

Memory
Bits Name Access Description

7 FORCE_CUR_LMT_ERR W Force Event for Current Limit Error

Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Current Limit Error Status is set
Value After Reset: 0x0
Exists: Always

6 FORCE_DATA_END_BIT_ERR W Force Event for Data End Bit Error (SD/eMMC Mode only)
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Data End Bit Error Status is set
Value After Reset: 0x0
Exists: Always

5 FORCE_DATA_CRC_ERR W Force Event for Data CRC Error (SD/eMMC Mode only)
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Data CRC Error Status is set
Value After Reset: 0x0
Exists: Always

4 FORCE_DATA_TOUT_ERR W Force Event for Data Timeout Error (SD/eMMC Mode only)
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Data Timeout Error Status is set
Value After Reset: 0x0
Exists: Always

3 FORCE_CMD_IDX_ERR W Force Event for Command Index Error (SD/eMMC Mode

only)
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Command Index Error Status is set
Value After Reset: 0x0
Exists: Always

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Table 5-38 Fields for Register: FORCE_ERROR_INT_STAT_R (Continued)

Memory
Bits Name Access Description

2 FORCE_CMD_END_BIT_ERR W Force Event for Command End Bit Error (SD/eMMC Mode
only)
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Command End Bit Error Status is set
Value After Reset: 0x0
Exists: Always

1 FORCE_CMD_CRC_ERR W Force Event for Command CRC Error (SD/eMMC Mode

only)
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Command CRC Error Status is set
Value After Reset: 0x0
Exists: Always

0 FORCE_CMD_TOUT_ERR W Force Event for Command Timeout Error (SD/eMMC Mode

only)
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Command Timeout Error Status is set
Value After Reset: 0x0
Exists: Always

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5.1.34 ADMA_ERR_STAT_R
■ Name: ADMA Error Status Register
■ Description: This register stores the ADMA state during an ADMA error. This register is applicable
for an SD/eMMC/UHS-II mode.
■ Size: 8 bits
■ Offset: 0x54
■ Exists: (DWC_MSHC_MST_IF_PRESENT==1)

7:3

ADMA_ERR_STATES 1:0
2
ADMA_LEN_ERR
RSVD_7_3

Table 5-39 Fields for Register: ADMA_ERR_STAT_R

Memory
Bits Name Access Description

7:3 RSVD_7_3 R These bits of the ADMA_ERR_STAT_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-39 Fields for Register: ADMA_ERR_STAT_R (Continued)

Memory
Bits Name Access Description

2 ADMA_LEN_ERR R ADMA Length Mismatch Error States

This error occurs in the following instances:
■ While the Block Count Enable is being set, the total data
length specified by the Descriptor table is different from
that specified by the Block Count and Block Length
■ When the total data length cannot be divided by the block
length

Values:
■ 0x0 (NO_ERR): No Error
■ 0x1 (ERROR): Error
Value After Reset: 0x0
Exists: Always
Volatile: true

1:0 ADMA_ERR_STATES R ADMA Error States

These bits indicate the state of ADMA when an error occurs
during ADMA data transfer.
Values:
■ 0x0 (ST_STOP): Stop DMA - SYS_ADR register points to
a location next to the error descriptor
■ 0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register
points to the error descriptor
■ 0x2 (UNUSED): Never set this state
■ 0x3 (ST_TFR): Transfer Data - SYS_ADR register points
to a location next to the error descriptor
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.35 ADMA_SA_LOW_R
■ Name: ADMA System Address Register - Low
■ Description: This register holds the lower 32-bit system address for DMA transfer. This register is
applicable for an SD/eMMC/UHS-II mode.
■ Size: 32 bits
■ Offset: 0x58
■ Exists: (DWC_MSHC_MST_IF_PRESENT==1)

ADMA_SA_LOW 31:0

Table 5-40 Fields for Register: ADMA_SA_LOW_R

Memory
Bits Name Access Description

31:0 ADMA_SA_LOW R/W ADMA System Address

These bits indicate the lower 32 bits of the ADMA system
address.
■ SDMA: If Host Version 4 Enable is set to 1, this register
stores the system address of the data location
■ ADMA2: This register stores the byte address of the
executing command of the descriptor table
■ ADMA3: This register is set by ADMA3. ADMA2
increments the address of this register that points to the
next line, every time a Descriptor line is fetched.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.36 ADMA_SA_HIGH_R
■ Name: ADMA System Address Register - High
■ Description: This register holds the upper 32-bit system address for the DMA transfer. This register
is applicable for an SD/eMMC/UHS-II mode.
■ Size: 32 bits
■ Offset: 0x5c
■ Exists: (DWC_MSHC_MST_IF_PRESENT==1) && (DWC_MSHC_MBIU_AW==64)

ADMA_SA_HIGH 31:0

Table 5-41 Fields for Register: ADMA_SA_HIGH_R

Memory
Bits Name Access Description

31:0 ADMA_SA_HIGH R/W ADMA System Address

These bits indicate the higher 32-bit of the ADMA system
address.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.37 PRESET_INIT_R
■ Name: Preset Value for Initialization
■ Description: This register defines Preset Value for Initialization in SD/eMMC mode.
■ Size: 16 bits
■ Offset: 0x60
■ Exists: Always

15:14
13:11

9:0
CLK_GEN_SEL_VAL 10
FREQ_SEL_VAL
DRV_SEL_VAL
RSVD_13_11

Table 5-42 Fields for Register: PRESET_INIT_R

Memory
Bits Name Access Description

15:14 DRV_SEL_VAL R Driver Strength Select Value

These bits indicate that the Driver strength is supported by
1.8V signaling bus speed modes. These bits are
meaningless for 3.3V signaling.
Values:
■ 0x0 (TYPEB): Driver Type B is selected
■ 0x1 (TYPEA): Driver Type A is selected
■ 0x2 (TYPEC): Driver Type C is selected
■ 0x3 (TYPED): Driver Type D is selected
Value After Reset: 0x0
Exists: Always

13:11 RSVD_13_11 R These bits of the PRESET_INIT_R register are reserved.

They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-42 Fields for Register: PRESET_INIT_R (Continued)

Memory
Bits Name Access Description

10 CLK_GEN_SEL_VAL R Clock Generator Select Value

This bit is effective when the Host Controller supports a
programmable clock generator.
Values:
■ 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock
Generator
■ 0x1 (PROG): Programmable Clock Generator
Value After Reset: DWC_MSHC_CLKGEN_SEL_INIT
Exists: Always

9:0 FREQ_SEL_VAL R SDCLK/RCLK Frequency Select Value

10-bit preset value to be set in SDCLK/RCLK Frequency
Select field of the Clock Control register described by a Host
System.
Value After Reset: DWC_MSHC_FREQ_SEL_INIT
Exists: Always

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5.1.38 PRESET_DS_R
■ Name: Preset Value for Default Speed
■ Description: This register defines Preset Value for Default Speed mode in SD mode.
■ Size: 16 bits
■ Offset: 0x62
■ Exists: Always

15:14
13:11

9:0
CLK_GEN_SEL_VAL 10
FREQ_SEL_VAL
DRV_SEL_VAL
RSVD_13_11

Table 5-43 Fields for Register: PRESET_DS_R

Memory
Bits Name Access Description

15:14 DRV_SEL_VAL R Driver Strength Select Value

These bits indicate the Driver strength value supported by
1.8V signaling bus speed modes. This field is meaningless
for the Default speed mode as it uses 3.3V signaling.
Values:
■ 0x0 (TYPEB): Driver Type B is selected
■ 0x1 (TYPEA): Driver Type A is selected
■ 0x2 (TYPEC): Driver Type C is selected
■ 0x3 (TYPED): Driver Type D is selected
Value After Reset: 0x0
Exists: Always

13:11 RSVD_13_11 R These bits of the PRESET_DS_R register are reserved.

They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-43 Fields for Register: PRESET_DS_R (Continued)

Memory
Bits Name Access Description

10 CLK_GEN_SEL_VAL R Clock Generator Select Value

This bit is effective when Host Controller supports
programmable clock generator.
Values:
■ 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock
Generator
■ 0x1 (PROG): Programmable Clock Generator
Value After Reset: DWC_MSHC_CLKGEN_SEL_DFLTSPD
Exists: Always

9:0 FREQ_SEL_VAL R SDCLK/RCLK Frequency Select Value

10-bit preset value to be set in SDCLK/RCLK Frequency
Select field of the Clock Control register described by a Host
System.
Value After Reset: DWC_MSHC_FREQ_SEL_DFLTSPD
Exists: Always

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5.1.39 PRESET_HS_R
■ Name: Preset Value for High Speed
■ Description: This register defines Preset Value for High Speed mode in SD mode.
■ Size: 16 bits
■ Offset: 0x64
■ Exists: Always

15:14
13:11

9:0
CLK_GEN_SEL_VAL 10
FREQ_SEL_VAL
DRV_SEL_VAL
RSVD_13_11

Table 5-44 Fields for Register: PRESET_HS_R

Memory
Bits Name Access Description

15:14 DRV_SEL_VAL R Driver Strength Select Value

These bits indicate the Driver strength value supported by
1.8V signaling bus speed modes. This field is meaningless
for High speed mode as it uses 3.3V signaling.
Values:
■ 0x0 (TYPEB): Driver Type B is selected
■ 0x1 (TYPEA): Driver Type A is selected
■ 0x2 (TYPEC): Driver Type C is selected
■ 0x3 (TYPED): Driver Type D is selected
Value After Reset: 0x0
Exists: Always

13:11 RSVD_13_11 R These bits of the PRESET_HS_R register are reserved.

They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-44 Fields for Register: PRESET_HS_R (Continued)

Memory
Bits Name Access Description

10 CLK_GEN_SEL_VAL R Clock Generator Select Value

This bit is effective when Host Controller supports
programmable clock generator.
Values:
■ 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock
Generator
■ 0x1 (PROG): Programmable Clock Generator
Value After Reset: DWC_MSHC_CLKGEN_SEL_HSPD
Exists: Always

9:0 FREQ_SEL_VAL R SDCLK/RCLK Frequency Select Value

10-bit preset value to be set in SDCLK/RCLK Frequency
Select field of the Clock Control register described by a Host
System.
Value After Reset: DWC_MSHC_FREQ_SEL_HSPD
Exists: Always

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5.1.40 PRESET_SDR12_R
■ Name: Preset Value for SDR12
■ Description: This register defines Preset Value for SDR12 and Legacy speed mode in SD and eMMC
mode respectively.
■ Size: 16 bits
■ Offset: 0x66
■ Exists: Always

15:14
13:11

9:0
CLK_GEN_SEL_VAL 10
FREQ_SEL_VAL
DRV_SEL_VAL
RSVD_13_11

Table 5-45 Fields for Register: PRESET_SDR12_R

Memory
Bits Name Access Description

15:14 DRV_SEL_VAL R Driver Strength Select Value

These bits indicate the Driver strength value supported for
the SDR12 bus speed mode. These bits are meaningless for
3.3V signaling.
Values:
■ 0x0 (TYPEB): Driver Type B is selected
■ 0x1 (TYPEA): Driver Type A is selected
■ 0x2 (TYPEC): Driver Type C is selected
■ 0x3 (TYPED): Driver Type D is selected
Value After Reset: DWC_MSHC_DRV_SEL_SDR12
Exists: Always

13:11 RSVD_13_11 R These bits of the PRESET_SDR12_R register are reserved.

They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-45 Fields for Register: PRESET_SDR12_R (Continued)

Memory
Bits Name Access Description

10 CLK_GEN_SEL_VAL R Clock Generator Select Value

This bit is effective when Host Controller supports
programmable clock generator
Values:
■ 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock
Generator
■ 0x1 (PROG): Programmable Clock Generator
Value After Reset: DWC_MSHC_CLKGEN_SEL_SDR12
Exists: Always

9:0 FREQ_SEL_VAL R SDCLK/RCLK Frequency Select Value

10-bit preset value to be set in SDCLK/RCLK Frequency
Select field of the Clock Control register described by a Host
System.
Value After Reset: DWC_MSHC_FREQ_SEL_SDR12
Exists: Always

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5.1.41 PRESET_SDR25_R
■ Name: Preset Value for SDR25
■ Description: This register defines Preset Value for SDR25 and High Speed SDR speed mode in SD
and eMMC mode respectively.
■ Size: 16 bits
■ Offset: 0x68
■ Exists: Always

15:14
13:11

9:0
CLK_GEN_SEL_VAL 10
FREQ_SEL_VAL
DRV_SEL_VAL
RSVD_13_11

Table 5-46 Fields for Register: PRESET_SDR25_R

Memory
Bits Name Access Description

15:14 DRV_SEL_VAL R Driver Strength Select Value

These bits indicate the Driver strength value supported for
the SDR25 bus speed mode. These bits are meaningless for
3.3V signaling.
Values:
■ 0x0 (TYPEB): Driver Type B is selected
■ 0x1 (TYPEA): Driver Type A is selected
■ 0x2 (TYPEC): Driver Type C is selected
■ 0x3 (TYPED): Driver Type D is selected
Value After Reset: DWC_MSHC_DRV_SEL_SDR25
Exists: Always

13:11 RSVD_13_11 R These bits of the PRESET_SDR25_R register are reserved.

They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-46 Fields for Register: PRESET_SDR25_R (Continued)

Memory
Bits Name Access Description

10 CLK_GEN_SEL_VAL R Clock Generator Select Value

This bit is effective when Host Controller supports
programmable clock generator.
Values:
■ 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock
Generator
■ 0x1 (PROG): Programmable Clock Generator
Value After Reset: DWC_MSHC_CLKGEN_SEL_SDR25
Exists: Always

9:0 FREQ_SEL_VAL R SDCLK/RCLK Frequency Select Value

10-bit preset value to be set in SDCLK/RCLK Frequency
Select field of the Clock Control register described by a Host
System.
Value After Reset: DWC_MSHC_FREQ_SEL_SDR25
Exists: Always

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5.1.42 PRESET_SDR50_R
■ Name: Preset Value for SDR50
■ Description: This register defines Preset Value for SDR50 speed mode in SD mode.
■ Size: 16 bits
■ Offset: 0x6a
■ Exists: Always

15:14
13:11

9:0
CLK_GEN_SEL_VAL 10
FREQ_SEL_VAL
DRV_SEL_VAL
RSVD_13_11

Table 5-47 Fields for Register: PRESET_SDR50_R

Memory
Bits Name Access Description

15:14 DRV_SEL_VAL R Driver Strength Select Value

These bits indicate Driver strength value supported for
SDR50 bus speed mode. These bits are meaningless for
3.3V signaling.
Values:
■ 0x0 (TYPEB): Driver Type B is selected
■ 0x1 (TYPEA): Driver Type A is selected
■ 0x2 (TYPEC): Driver Type C is selected
■ 0x3 (TYPED): Driver Type D is selected
Value After Reset: DWC_MSHC_DRV_SEL_SDR50
Exists: Always

13:11 RSVD_13_11 R These bits of the PRESET_SDR50_R register are reserved.

They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-47 Fields for Register: PRESET_SDR50_R (Continued)

Memory
Bits Name Access Description

10 CLK_GEN_SEL_VAL R Clock Generator Select Value

This bit is effective when Host Controller supports
programmable clock generator.
Values:
■ 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock
Generator
■ 0x1 (PROG): Programmable Clock Generator
Value After Reset: DWC_MSHC_CLKGEN_SEL_SDR50
Exists: Always

9:0 FREQ_SEL_VAL R SDCLK/RCLK Frequency Select Value

10-bit preset value to be set in SDCLK/RCLK Frequency
Select field of the Clock Control register described by a Host
System.
Value After Reset: DWC_MSHC_FREQ_SEL_SDR50
Exists: Always

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5.1.43 PRESET_SDR104_R
■ Name: Preset Value for SDR104
■ Description: This register defines Preset Value for SDR104 and HS200 speed modes in the SD and
eMMC modes, respectively.
■ Size: 16 bits
■ Offset: 0x6c
■ Exists: Always

15:14
13:11

9:0
CLK_GEN_SEL_VAL 10
FREQ_SEL_VAL
DRV_SEL_VAL
RSVD_13_11

Table 5-48 Fields for Register: PRESET_SDR104_R

Memory
Bits Name Access Description

15:14 DRV_SEL_VAL R Driver Strength Select Value

These bits indicate Driver strength value supported for
SDR104 bus speed mode. These bits are meaningless for
3.3V signaling.
Values:
■ 0x0 (TYPEB): Driver Type B is selected
■ 0x1 (TYPEA): Driver Type A is selected
■ 0x2 (TYPEC): Driver Type C is selected
■ 0x3 (TYPED): Driver Type D is selected
Value After Reset: DWC_MSHC_DRV_SEL_SDR104
Exists: Always

13:11 RSVD_13_11 R These bits of the PRESET_SDR104_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-48 Fields for Register: PRESET_SDR104_R (Continued)

Memory
Bits Name Access Description

10 CLK_GEN_SEL_VAL R Clock Generator Select Value

This bit is effective when Host Controller supports
programmable clock generator.
Values:
■ 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock
Generator
■ 0x1 (PROG): Programmable Clock Generator
Value After Reset: DWC_MSHC_CLKGEN_SEL_SDR104
Exists: Always

9:0 FREQ_SEL_VAL R SDCLK/RCLK Frequency Select Value

These bits specify a 10-bit preset value that must be set in
the SDCLK/RCLK Frequency Select field of the Clock
Control register described by a Host System.
Value After Reset: DWC_MSHC_FREQ_SEL_SDR104
Exists: Always

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5.1.44 PRESET_DDR50_R
■ Name: Preset Value for DDR50
■ Description: This register defines the Preset Value for DDR50 and High Speed DDR speed modes in
the SD and eMMC modes, respectively.
■ Size: 16 bits
■ Offset: 0x6e
■ Exists: Always

15:14
13:11

9:0
CLK_GEN_SEL_VAL 10
FREQ_SEL_VAL
DRV_SEL_VAL
RSVD_13_11

Table 5-49 Fields for Register: PRESET_DDR50_R

Memory
Bits Name Access Description

15:14 DRV_SEL_VAL R Driver Strength Select Value

These bits indicate Driver strength value supported for
DDR50 bus speed mode. These bits are meaningless for
3.3V signaling.
Values:
■ 0x0 (TYPEB): Driver Type B is selected
■ 0x1 (TYPEA): Driver Type A is selected
■ 0x2 (TYPEC): Driver Type C is selected
■ 0x3 (TYPED): Driver Type D is selected
Value After Reset: DWC_MSHC_DRV_SEL_DDR50
Exists: Always

13:11 RSVD_13_11 R These bits of the PRESET_DDR50_R register are reserved.

They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-49 Fields for Register: PRESET_DDR50_R (Continued)

Memory
Bits Name Access Description

10 CLK_GEN_SEL_VAL R Clock Generator Select Value

This bit is effective when Host Controller supports
programmable clock generator.
Values:
■ 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock
Generator
■ 0x1 (PROG): Programmable Clock Generator
Value After Reset: DWC_MSHC_CLKGEN_SEL_DDR50
Exists: Always

9:0 FREQ_SEL_VAL R SDCLK/RCLK Frequency Select Value

These bits specify a 10-bit preset value that must be set in
the SDCLK/RCLK Frequency Select field of the Clock
Control register, as described by a Host System.
Value After Reset: DWC_MSHC_FREQ_SEL_DDR50
Exists: Always

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5.1.45 PRESET_UHS2_R
■ Name: Preset Value for UHS-II
■ Description: This register is used to hold the preset value for UHS-II and HS400 speed modes in the
SD and eMMC modes, respectively.
■ Size: 16 bits
■ Offset: 0x74
■ Exists: Always

15:14
13:11

9:0
CLK_GEN_SEL_VAL 10
FREQ_SEL_VAL
DRV_SEL_VAL
RSVD_13_11

Table 5-50 Fields for Register: PRESET_UHS2_R

Memory
Bits Name Access Description

15:14 DRV_SEL_VAL R Driver Strength Select Value

These bits indicate the Driver strength value supported by
1.8V signaling bus speed modes in the SD mode. This field
is meaningless for UHS-II mode. In eMMC mode, these bits
can be used for selecting the Drive strength value for HS400
mode.
Values:
■ 0x0 (TYPEB): Driver Type B is selected
■ 0x1 (TYPEA): Driver Type A is selected
■ 0x2 (TYPEC): Driver Type C is selected
■ 0x3 (TYPED): Driver Type D is selected
Value After Reset: DWC_MSHC_DRV_SEL_HS400
Exists: Always

13:11 RSVD_13_11 R These bits of UHS-II Preset register are reserved. They
always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-50 Fields for Register: PRESET_UHS2_R (Continued)

Memory
Bits Name Access Description

10 CLK_GEN_SEL_VAL R Clock Generator Select Value

This bit is effective when the Host Controller supports a
programmable clock generator.
Values:
■ 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock
Generator
■ 0x1 (PROG): Programmable Clock Generator
Value After Reset: DWC_MSHC_CLKGEN_SEL_UHS2
Exists: Always

9:0 FREQ_SEL_VAL R SDCLK/RCLK Frequency Select Value

These bits specify the 10-bit preset value that must be set in
the SDCLK/RCLK Frequency Select field of the Clock
Control register, as described by a Host System.
Value After Reset: DWC_MSHC_FREQ_SEL_UHS2
Exists: Always

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5.1.46 ADMA_ID_LOW_R
■ Name: ADMA3 Integrated Descriptor Address Register - Low
■ Description: This register holds the lower 32-bit Integrated Descriptor address.This register is
applicable for an SD/eMMC/UHS-II mode.
■ Size: 32 bits
■ Offset: 0x78
■ Exists: (DWC_MSHC_ADMA3_SUPPORT==1)

ADMA_ID_LOW 31:0

Table 5-51 Fields for Register: ADMA_ID_LOW_R

Memory
Bits Name Access Description

31:0 ADMA_ID_LOW R/W ADMA Integrated Descriptor Address

These bits indicate the lower 32-bit of the ADMA Integrated
Descriptor address. The start address of Integrated
Descriptor is set to these register bits. The ADMA3 fetches
one Descriptor Address and increments these bits to indicate
the next Descriptor address.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.47 ADMA_ID_HIGH_R
■ Name: ADMA3 Integrated Descriptor Address Register - High
■ Description: This register holds the upper 32-bit Integrated Descriptor address.This register is
applicable for an SD/eMMC/UHS-II mode.
■ Size: 32 bits
■ Offset: 0x7c
■ Exists: (DWC_MSHC_ADMA3_SUPPORT==1) && (DWC_MSHC_MBIU_AW==64)

ADMA_ID_HIGH 31:0

Table 5-52 Fields for Register: ADMA_ID_HIGH_R

Memory
Bits Name Access Description

31:0 ADMA_ID_HIGH R/W ADMA Integrated Descriptor Address

These bits indicate the higher 32 bit of the ADMA Integrated
Descriptor address.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.48 UHS_II_BLOCK_SIZE_R
■ Name: UHS-II Block Size Register
■ Description: This register specifies block size of data packet and SDMA buffer boundary. This
register is applicable for UHS-II mode only.
■ Size: 16 bits
■ Offset: 0x80
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

UHS_II_SDMA_BOUND 14:12
11:0
15

UHS_II_BLK_SIZE
RSVD_15

Table 5-53 Fields for Register: UHS_II_BLOCK_SIZE_R

Memory
Bits Name Access Description

15 RSVD_15 R This bit of the UHS_II_BLOCK_SIZE_R register is reserved.

It always returns 0.
Value After Reset: 0x0
Exists: Always

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Table 5-53 Fields for Register: UHS_II_BLOCK_SIZE_R (Continued)

Memory
Bits Name Access Description

14:12 UHS_II_SDMA_BOUND R/W UHS-II SDMA Buffer Boundary (SDMA only)

These bits set the page size of the system memory
management. When system memory is managed by paging,
SDMA data transfer is performed in units of paging. The Host
controller generates DMA interrupt at the page boundary and
requests the Host driver to update the ADMA system
address register. The SDMA waits until the ADMA system
address register is written. This is active when DMA Enable
in the UHS-II Transfer Mode register is set to 1.
Values:
■ 0x0 (BYTES_4K): 4K bytes UHS-II SDMA Boundary
■ 0x1 (BYTES_8K): 8K bytes UHS-II SDMA Boundary
■ 0x2 (BYTES_16K): 16K bytes UHS-II SDMA Boundary
■ 0x3 (BYTES_32K): 32K bytes UHS-II SDMA Boundary
■ 0x4 (BYTES_64K): 64K bytes UHS-II SDMA Boundary
■ 0x5 (BYTES_128K): 128K bytes UHS-II SDMA Boundary
■ 0x6 (BYTES_256K): 256K bytes UHS-II SDMA Boundary
■ 0x7 (BYTES_512K): 512K bytes UHS-II SDMA Boundary
Value After Reset: 0x0
Exists: Always

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Table 5-53 Fields for Register: UHS_II_BLOCK_SIZE_R (Continued)

Memory
Bits Name Access Description

11:0 UHS_II_BLK_SIZE R/W UHS-II Block Size

This register specifies the block size of the data packet. SD
memory card uses fixed block size of 512 bytes. Variable
block size can be used for SDIO. This register is effective
when Data Present is set to 1 in the UHS-II Command
register.
■ 0x0001 : 1 Byte
■ 0x0002 : 2 Bytes
■ 0x0003 : 3 Bytes
■ .........
■ .........
■ .........
■ 0x01FF : 511 Bytes
■ 0x0200 : 512 Bytes
■ .........
■ .........
■ .........
■ 0x0800 : 2048 Bytes

Note: UHS-II Block size must be programmed with non-zero

value for a data transfer.
Value After Reset: 0x0
Exists: Always

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5.1.49 UHS_II_BLOCK_COUNT_R
■ Name: UHS-II Block Count Register
■ Description: This register determines the length of the data transfer. This register is applicable for
UHS-II mode only.
■ Size: 32 bits
■ Offset: 0x84
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

BLK_COUNT 31:0

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Table 5-54 Fields for Register: UHS_II_BLOCK_COUNT_R

Memory
Bits Name Access Description

31:0 BLK_COUNT R/W UHS-II Blocks Count

These bits specify the number of blocks to be transferred.
This register is effective when Data Present is set to 1 in the
UHS-II Command register and is enabled when Block Count
Enable is set to 1 and Block/Byte Mode is set to 0 in the
UHS-II Transfer Mode register.
■ 0x00000000 : Stop Count
■ 0x00000001 : 1 block
■ 0x00000002 : 2 blocks
■ ...........
■ ...........
■ ...........
■ 0xFFFFFFFF : 4G-1 blocks

Note:
■ When this register is read during a data transfer, it may
return an invalid value. This register must be read only
when there is no data transfer in progress or after a data
transfer had completed.
■ UHS-II Block count must be programmed with a non-zero
value for data transfer when Block Count Enable is set to
1 in the UHS-II Transfer Mode Register.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.50 UHS_II_COMMAND_PKT_0_3_R
■ Name: UHS-II Command Packet Register (Byte 0, 1, 2 and 3)
■ Description: This register specifies byte 0-3 of UHS-II command packet. This register is applicable for
UHS-II mode only.
■ Size: 32 bits
■ Offset: 0x88
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

COMMAND_PKT_0_3 31:0

Table 5-55 Fields for Register: UHS_II_COMMAND_PKT_0_3_R

Memory
Bits Name Access Description

31:0 COMMAND_PKT_0_3 R/W UHS-II command packet

This register represents byte number 0 to byte number 3 of
UHS-II command packet. These bytes must be programmed
in Little-endian format. The UHS-II command packet can be
a maximum of 20 bytes. The command length is specified by
the UHS-II Command register.
For more information on the UHS-II command packet, refer
the UHS-II Addendum.
Value After Reset: 0x0
Exists: Always

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5.1.51 UHS_II_COMMAND_PKT_4_7_R
■ Name: UHS-II Command Packet Register (Byte 4, 5, 6 and 7)
■ Description: This register specifies byte 4-7 of the UHS-II command packet. This register is
applicable for UHS-II mode only.
■ Size: 32 bits
■ Offset: 0x8c
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

COMMAND_PKT_4_7 31:0

Table 5-56 Fields for Register: UHS_II_COMMAND_PKT_4_7_R

Memory
Bits Name Access Description

31:0 COMMAND_PKT_4_7 R/W UHS-II command packet

This register represents byte number 4 to byte number 7 of
UHS-II command packet. These bytes must be programmed
in Little-endian format. The UHS-II command packet can be
a maximum of 20 bytes. The command length is specified by
the UHS-II Command register.
For more information on the UHS-II command packet, refer
the UHS-II Addendum.
Value After Reset: 0x0
Exists: Always

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5.1.52 UHS_II_COMMAND_PKT_8_11_R
■ Name: UHS-II Command Packet Register (Byte 8, 9, 10 and 11)
■ Description: This register specifies byte 8-11 of the UHS-II command packet. This register is
applicable for UHS-II mode only.
■ Size: 32 bits
■ Offset: 0x90
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

COMMAND_PKT_8_11 31:0

Table 5-57 Fields for Register: UHS_II_COMMAND_PKT_8_11_R

Memory
Bits Name Access Description

31:0 COMMAND_PKT_8_11 R/W UHS-II command packet

These bits represent byte number 8 to byte number 11 of
UHS-II command packet. These bytes must be programmed
in Little-endian format. The UHS-II command packet can be
a maximum of 20 bytes. The command length is specified by
the UHS-II Command register.
For more information on the UHS-II command packet, refer
the UHS-II Addendum.
Value After Reset: 0x0
Exists: Always

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5.1.53 UHS_II_COMMAND_PKT_12_15_R
■ Name: UHS-II Command Packet Register (Byte 12, 13, 14 and 15)
■ Description: This register specifies byte 12-15 of UHS-II command packet. This register is applicable
for UHS-II mode only.
■ Size: 32 bits
■ Offset: 0x94
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

COMMAND_PKT_12_15 31:0

Table 5-58 Fields for Register: UHS_II_COMMAND_PKT_12_15_R

Memory
Bits Name Access Description

31:0 COMMAND_PKT_12_15 R/W UHS-II command packet

These bits represent byte number 12 to byte number 15 of
UHS-II command packet. These bytes must be programmed
in Little-endian format. The UHS-II command packet can be
a maximum of 20 bytes. The command length is specified by
the UHS-II Command register.
For more information on the UHS-II command packet, refer
the UHS-II Addendum.
Value After Reset: 0x0
Exists: Always

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5.1.54 UHS_II_COMMAND_PKT_16_19_R
■ Name: UHS-II Command Packet Register (Byte 16, 17, 18 and 19)
■ Description: This register specifies byte 16-19 of UHS-II command packet. This register is applicable
for UHS-II mode only.
■ Size: 32 bits
■ Offset: 0x98
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

COMMAND_PKT_16_19 31:0

Table 5-59 Fields for Register: UHS_II_COMMAND_PKT_16_19_R

Memory
Bits Name Access Description

31:0 COMMAND_PKT_16_19 R/W UHS-II command packet

These bits represent byte number 16 to byte number 19 of
the UHS-II command packet. These bytes must be
programmed in Little-endian format. The UHS-II command
packet can be a maximum of 20 bytes. The command length
is specified by the UHS-II Command register.
For more information on the UHS-II command packet, refer
the UHS-II Addendum.
Value After Reset: 0x0
Exists: Always

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5.1.55 UHS_II_XFER_MODE_R
■ Name: UHS-II Transfer Mode Register
■ Description: This register specifies all the attributes of UHS-II data transfer for the reference of the
Host controller. This register is applicable for UHS-II mode only.
■ Size: 16 bits
■ Offset: 0x9c
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

13:9

3:2
15
14

RESP_INTR_DISABLE 8
7
6
5
4

1
0
RESP_ERR_CHK_EN

BLK_BYTE_MODE
RESERVED_13_9

DATA_XFER_DIR
HALF_FULL_SEL

RESERVED_3_2
BLK_CNT_EN
EBSY_WAIT

RESP_TYP

DMA_EN
Table 5-60 Fields for Register: UHS_II_XFER_MODE_R

Memory
Bits Name Access Description

15 HALF_FULL_SEL R/W Half/Full Select

This bit is used to select the two-lane half-duplex mode.
This bit must be set to 1 only when both the host and the
device support two-lane half-duplex mode. The Host driver
must read the UHS-II General Capabilities register to idenfity
the capability of the Host to support two-lane half-duplex
mode.
Values:
■ 0x0 (FULL_DUPLEX): Full Duplex mode
■ 0x1 (HALF_DUPLEX): Half Duplex mode
Value After Reset: 0x0
Exists: Always

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Table 5-60 Fields for Register: UHS_II_XFER_MODE_R (Continued)

Memory
Bits Name Access Description

14 EBSY_WAIT R/W EBSY Wait

This bit is set while issuing a command that is accompanied
by the EBSY packet to indicate end of command execution. If
this bit is set to 1, the Host controller waits to receive EBSY
packet and on receiving an EBSY packet, the Transfer
Complete interrupt in the Normal Interrupt Status register is
set to 1 to indicate end of busy.
If error is indicated in the EBSY packet, the EBSY Error in
the UHS-II Error Interrupt Status register is set to 1 and the
Error Interrupt in the Normal Interrupt Status register is also
set.
Values:
■ 0x0 (CMD_WITHOUT_EBSY_WAIT): Issue a command
without busy
■ 0x1 (CMD_WITH_EBSY_WAIT): Wait EBSY while
issuing command with busy
Value After Reset: 0x0
Exists: Always

13:9 RESERVED_13_9 R These bits (RESERVED_13_9) of the

UHS_II_XFER_MODE_R register are reserved. They always
return 0.
Value After Reset: 0x0
Exists: Always

8 RESP_INTR_DISABLE R/W Response Interrupt Disable

This bit along with the Response Error Check Enable bit
enable the Host controller to check the response error. The
Host controller version 4.00 supports response error check
function to avoid overhead of response error check by Host
driver. The Command Complete interrupt is disabled when
this bit is set to 1 regardless of Command Complete Signal
Enable. Note that only response of type R1 and R5 can be
checked by the Host controller.
If this bit is set to 0, the Host driver must check the response
register after generation of the Command Complete
interrupt.
Values:
■ 0x0 (ENABLE_RESP_INTR): Response Interrupt is
enabled
■ 0x1 (DISABLE_RESP_INTR): Response Interrupt is
disabled
Value After Reset: 0x0
Exists: Always

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Table 5-60 Fields for Register: UHS_II_XFER_MODE_R (Continued)

Memory
Bits Name Access Description

7 RESP_ERR_CHK_EN R/W Response Error Check Enable

This bit along with the Response Interrupt Disable enables
the Host controller to check the response error. If Host driver
checks the response error, this bit is set to 0 and Response
Interrupt Disable is set to 0. Host controller version 4.00
supports response error check function to avoid overhead of
response error check by Host driver.
If an error is detected, the RES Packet error interrupt is
generated in the UHS-II Error Interrupt Status register.
Values:
■ 0x0 (DISABLE_RESP_ERR_CHK): Response Error
Check is disabled
■ 0x1 (ENABLE_RESP_ERR_CHK): Response Error
Check is enabled
Value After Reset: 0x0
Exists: Always

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Table 5-60 Fields for Register: UHS_II_XFER_MODE_R (Continued)

Memory
Bits Name Access Description

6 RESP_TYP R/W Response Type R1/R5

This bit selects a response type when the response error
check is enabled.
Note: Following errors in the response are checked by Host
controller:
Error statuses checked in R1
■ Bit31 OUT_OF_RANGE
■ Bit30 ADDRESS_ERROR
■ Bit29 BLOCK_LEN_ERROR
■ Bit26 WP_VIOLATION
■ Bit25 CARD_IS_LOCKED
■ Bit23 COM_CRC_ERROR
■ Bit21 CARD_ECC_FAILED
■ Bit20 CC_ERROR
■ Bit19 ERROR
Error statuses checked in R5
■ Bit07 COM_CRC_ERROR
■ Bit03 ERROR
■ Bit01 FUNCTION_NUMBER
■ Bit00 OUT_OF_RANGE

Values:
■ 0x0 (RESP_R1): R1 response (Memory)
■ 0x1 (RESP_R5): R5 response (SDIO)
Value After Reset: 0x0
Exists: Always

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Table 5-60 Fields for Register: UHS_II_XFER_MODE_R (Continued)

Memory
Bits Name Access Description

5 BLK_BYTE_MODE R/W Block/Byte Mode

This bit specifies whether the data transfer is in block mode
or byte mode when the Data Present bit in the UHS-II
Command register is set to 1.
Note:
■ Block mode: UHS-II Block size register represents the
size of one DATA packet and UHS-II Block Count register
represents the number of data blocks to be
transmitted/received when block count is enabled. If block
count is not enabled then it is treated as infinite transfer
by the Host controller. An Abort command must be issued
to end the infinite transfer. In the special case when
ADMA2 is used and block count is disabled, transfer is
ended after completing the last descriptor line.
■ Byte mode: Only one DATA packet is
transmitted/received. Size of this DATA packet is dictated
by the UHS-II Block Size register. Block count and block
count enable is not considered for byte mode.

Values:
■ 0x0 (BLOCK_MODE): Block mode
■ 0x1 (BYTE_MODE): Byte mode
Value After Reset: 0x0
Exists: Always

4 DATA_XFER_DIR R/W Data Transfer Direction

This bit specifies direction of data transfer when Data
Present in the UHS-II Command register is set to 1.
Values:
■ 0x0 (READ): Read (Card to Host)
■ 0x1 (WRITE): Write (Host to Card)
Value After Reset: 0x0
Exists: Always

3:2 RESERVED_3_2 R These bits (RESERVED_3_2) of the

UHS_II_XFER_MODE_R register are reserved. They always
return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-60 Fields for Register: UHS_II_XFER_MODE_R (Continued)

Memory
Bits Name Access Description

1 BLK_CNT_EN R/W Block Count Enable

This bit terminates data transfer by the block count that is
specified using the UHS-II Block Count register. If this bit is
set to 0, data transfer can either be terminated by end of
descriptor line for ADMA2 operation, by CMD12, or by the
TRANS_ABORT command.
Values:
■ 0x0 (DISABLE_BLK_CNT): Block Count is disabled
■ 0x1 (ENABLE_BLK_CNT): Block Count is enabled
Value After Reset: 0x0
Exists: Always

0 DMA_EN R/W DMA Enable

This bit specifies whether DMA is used or not. DMA type is
selected using DMA Select in Host Control1 register.
Values:
■ 0x0 (DISABLE_DMA): DMA is disabled
■ 0x1 (ENABLE_DMA): DMA is enabled
Value After Reset: 0x0
Exists: Always

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5.1.56 UHS_II_CMD_R
■ Name: UHS-II Command Register
■ Description: This register specifies attributes of the UHS-II Command. Writing to upper byte of this
register acts as a trigger to issue the Command Packet. This register is applicable for UHS-II mode
only.
■ Size: 16 bits
■ Offset: 0x9e
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

15:13
UHS_II_CMD_PKT_LEN 12:8
7:6

4:3

1:0
5

2
RESERVED_15_13

UHS_II_CMD_TYP

SUB_CMD_FLAG
DATA_PRESENT
RESERVED_4_3

RESERVED_1_0

Table 5-61 Fields for Register: UHS_II_CMD_R

Memory
Bits Name Access Description

15:13 RESERVED_15_13 R These bits (RESERVED_15_13) of the UHS_II_CMD_R

register are reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-61 Fields for Register: UHS_II_CMD_R (Continued)

Memory
Bits Name Access Description

12:8 UHS_II_CMD_PKT_LEN R/W UHS-II Command Packet Length

These bits set the command packet length, which is set in
the UHS-II Command Packet register.
■ 0x03-0x00 : 3-0 Bytes (Not used)
■ 0x04 : 4 Bytes
■ .........
■ 0x0C : 12 Bytes
■ .........
■ 0x14 : 20 Bytes
■ 0x1F-0x15 : Not used

Note: The UHS-II protocol defines all command packet

lengths in multiples of four. Setting these bits to a non-
multiple of four is not recommended.
Value After Reset: 0x0
Exists: Always

7:6 UHS_II_CMD_TYP R/W UHS-II Command Type

These bits are used to distinguish different command types.
Note:
While issuing UHS-II GO_DORMANT_STATE CCMD or
FULL_RESET CCMD, UHS_II_CMD_TYPE shall be set to
0x3
For different command types, the response of the command
(UHS-II RES packet) is stored in different register as shown
below:
■ 0x0 : UHS-II Response register (0B3h-0A0h)
■ 0x1 : Response register (013h-010h)
■ 0x2 : Response register (01Fh-018h)
■ 0x3 : UHS-II Response register (0B3h-0A0h)

Values:
■ 0x0 (NORMAL_CCMD): Normal Command
■ 0x1 (TRANS_ABORT_CCMD): TRANS_ABORT
command
■ 0x2 (CMD12_OR_SDIO_ABORT): CMD12 or SDIO
Abort command
■ 0x3 (GO_DORMANT_CCMD): Go Dormant Command
Value After Reset: 0x0
Exists: Always

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Table 5-61 Fields for Register: UHS_II_CMD_R (Continued)

Memory
Bits Name Access Description

5 DATA_PRESENT R/W Data Present

This bit specifies whether the command is accompanied by
data packet.
Values:
■ 0x0 (NO_DATA_PRESENT): No data present
■ 0x1 (DATA_PRESENT): Data present
Value After Reset: 0x0
Exists: Always

4:3 RESERVED_4_3 R These bits (RESERVED_4_3) of the UHS_II_CMD_R

register are reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

2 SUB_CMD_FLAG R/W Sub Command Flag

This bit is used to distinguish between the main command
and the sub command. Setting of this bit is checked by the
Sub Command Status in the Present state register.
Note: The Host controller does not refer to this bit to issue a
command. This bit is by the Host driver to manage the main
command and the sub command. For more information, refer
the Sub Command Status field in the Present State register.
Values:
■ 0x0 (SUB_CMD): Sub Command
■ 0x1 (MAIN_CMD): Main Command
Value After Reset: 0x0
Exists: Always

1:0 RESERVED_1_0 R These bits (RESERVED_1_0) of the UHS_II_CMD_R

register are reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

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5.1.57 UHS_II_RESP_0_3_R
■ Name: UHS-II Response Register (Byte 0, 1, 2 and 3)
■ Description: This register specifies byte 0-3 of UHS-II response packet. This register is applicable for
UHS-II mode only.
■ Size: 32 bits
■ Offset: 0xa0
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

RESP_PKT_0_3 31:0

Table 5-62 Fields for Register: UHS_II_RESP_0_3_R

Memory
Bits Name Access Description

31:0 RESP_PKT_0_3 R UHS-II response packet

This register represents byte number 0 to byte number 3 of
UHS-II response packet. These bytes are stored in Little-
endian format. The UHS-II response packet can be a
maximum of 20 bytes
For more information on the format of a UHS-II response
packet, refer the UHS-II Addendum.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.58 UHS_II_RESP_4_7_R
■ Name: UHS-II Response Register (Byte 4, 5, 6 and 7)
■ Description: This register specifies byte 4-7 of UHS-II response packet. This register is applicable for
UHS-II mode only.
■ Size: 32 bits
■ Offset: 0xa4
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

RESP_PKT_4_7 31:0

Table 5-63 Fields for Register: UHS_II_RESP_4_7_R

Memory
Bits Name Access Description

31:0 RESP_PKT_4_7 R UHS-II response packet

This register represents byte number 4 to byte number 7 of
UHS-II response packet. These bytes are stored in Little-
endian format. The UHS-II response packet can be a
maximum of 20 bytes
For more information on the format of a UHS-II response
packet, refer the UHS-II Addendum.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.59 UHS_II_RESP_8_11_R
■ Name: UHS-II Response Register (Byte 8, 9, 10 and 11)
■ Description: This register specifies byte 8-11 of UHS-II response packet. This register is applicable for
UHS-II mode only.
■ Size: 32 bits
■ Offset: 0xa8
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

RESP_PKT_8_11 31:0

Table 5-64 Fields for Register: UHS_II_RESP_8_11_R

Memory
Bits Name Access Description

31:0 RESP_PKT_8_11 R UHS-II response packet

These bits represent byte number 8 to byte number 11 of
UHS-II response packet. These bytes are stored in Little-
endian format. The UHS-II response packet can be a
maximum of 20 bytes
For more information on the format of a UHS-II response
packet, refer the UHS-II Addendum.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.60 UHS_II_RESP_12_15_R
■ Name: UHS-II Response Register (Byte 12, 13, 14 and 15)
■ Description: This register specifies byte 12-15 of UHS-II response packet. This register is applicable
for UHS-II mode only.
■ Size: 32 bits
■ Offset: 0xac
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

RESP_PKT_12_15 31:0

Table 5-65 Fields for Register: UHS_II_RESP_12_15_R

Memory
Bits Name Access Description

31:0 RESP_PKT_12_15 R UHS-II response packet

These bits represent byte number 12 to byte number 15 of
the UHS-II response packet. These bytes are stored in Little-
endian format. The UHS-II response packet can be a
maximum of 20 bytes.
For more information on the format of a UHS-II response
packet, refer the UHS-II Addendum.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.61 UHS_II_RESP_16_19_R
■ Name: UHS-II Response Register (Byte 16, 17, 18 and 19)
■ Description: This register specifies byte 16-19 of UHS-II response packet. This register is applicable
for UHS-II mode only.
■ Size: 32 bits
■ Offset: 0xb0
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

RESP_PKT_16_19 31:0

Table 5-66 Fields for Register: UHS_II_RESP_16_19_R

Memory
Bits Name Access Description

31:0 RESP_PKT_16_19 R UHS-II response packets

This bit represents the byte number 16 to byte number 19 of
the UHS-II response packet. These bytes are stored in Little-
endian format. The UHS-II response packets can be a
maximum of 20 bytes.
For more information on the format of a UHS-II response
packet, refer the UHS-II Addendum.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.62 UHS_II_MSG_SEL_R
■ Name: UHS-II MSG Select Register
■ Description: This register selects one of last four messages stored in host controller. This register is
applicable for UHS-II mode only.
■ Size: 8 bits
■ Offset: 0xb4
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

7:2
UHS_II_MSG_SEL 1:0
RESERVED_7_2

Table 5-67 Fields for Register: UHS_II_MSG_SEL_R

Memory
Bits Name Access Description

7:2 RESERVED_7_2 R These bits of the UHS_II_MSG_SEL_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

1:0 UHS_II_MSG_SEL R/W UHS-II MSG Select

These bits denote one of the four messages that can be
read from the UHS-II MSG register. The host controller holds
the last four message packets received from the UHS-II card.
These bits select one of these four messages that can be
read from the UHS-II MSG register.
Values:
■ 0x0 (LATEST_MSG): The latest MSG
■ 0x1 (PREV_FIRST_MSG): One MSG before
■ 0x2 (PREV_SECOND_MSG): Two MSGs before
■ 0x3 (PREV_THIRD_MSG): Three MSGs before
Value After Reset: 0x0
Exists: Always

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5.1.63 UHS_II_MSG_R
■ Name: UHS-II MSG Register
■ Description: This register points to one of last four UHS_II MSG packets selected by UHS-II MSG
Select register. This register is applicable for UHS-II mode only.
■ Size: 32 bits
■ Offset: 0xb8
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

UHS_II_MSG 31:0

Table 5-68 Fields for Register: UHS_II_MSG_R

Memory
Bits Name Access Description

31:0 UHS_II_MSG R UHS-II MSG

These bits contain the MSG packet selected by the UHS-II
MSG Packet Select register. The Host controller holds the
last four MSG packets received from the UHS-II card.
Usually two duplicate MSG packets are sent from the UHS-II
card. One of these two MSG packets that are recognized as
valid is stored in the MSG packet buffer.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.64 UHS_II_DEV_INTR_STATUS_R
■ Name: UHS-II Device Interrupt Status Register
■ Description: This register shows the device from which INT MSG is received and is effective when
INT MSG Enable is set to 1 in the UHS-II Device Select register. On receiving the INT MSG from a
device, the Host controller saves the INT MSG to the UHS-II Device Interrupt Code register. A bit of
this register, which is correspondent to the Device ID is set to 1 and generates the Card Interrupt in
the Normal Interrupt Status register.
If INT MSG Enable is set to 0, this register is cleared and the Host controller ignores the receipt of INT
MSG.
The effective bit range of this register is determined by the Number of devices in the UHS-II General
Capabilities register.
This register is applicable for UHS-II mode only.
■ Size: 16 bits
■ Offset: 0xbc
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)
DEV_INTR_STATUS15 15
DEV_INTR_STATUS14 14
DEV_INTR_STATUS13 13
DEV_INTR_STATUS12 12
DEV_INTR_STATUS11 11
DEV_INTR_STATUS10 10
9
8
7
6
5
4
3
2
1
0
DEV_INTR_STATUS9
DEV_INTR_STATUS8
DEV_INTR_STATUS7
DEV_INTR_STATUS6
DEV_INTR_STATUS5
DEV_INTR_STATUS4
DEV_INTR_STATUS3
DEV_INTR_STATUS2
DEV_INTR_STATUS1
DEV_INTR_STATUS0

Table 5-69 Fields for Register: UHS_II_DEV_INTR_STATUS_R

Memory
Bits Name Access Description

15 DEV_INTR_STATUS15 R/W1C This bit indicates that the INT MSG is received from Device
ID 15.
Values:
■ 0x0 (NO_INT): No INT MSG received
■ 0x1 (INT): INT MSG received
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-69 Fields for Register: UHS_II_DEV_INTR_STATUS_R (Continued)

Memory
Bits Name Access Description

14 DEV_INTR_STATUS14 R/W1C This bit indicates that the INT MSG is received from Device
ID 14.
Values:
■ 0x0 (NO_INT): No INT MSG received
■ 0x1 (INT): INT MSG received
Value After Reset: 0x0
Exists: Always
Volatile: true

13 DEV_INTR_STATUS13 R/W1C This bit indicates that the INT MSG is received from Device
ID 13.
Values:
■ 0x0 (NO_INT): No INT MSG received
■ 0x1 (INT): INT MSG received
Value After Reset: 0x0
Exists: Always
Volatile: true

12 DEV_INTR_STATUS12 R/W1C This bit indicates that the INT MSG is received from Device
ID 12.
Values:
■ 0x0 (NO_INT): No INT MSG received
■ 0x1 (INT): INT MSG received
Value After Reset: 0x0
Exists: Always
Volatile: true

11 DEV_INTR_STATUS11 R/W1C This bit indicates that the INT MSG is received from Device
ID 11.
Values:
■ 0x0 (NO_INT): No INT MSG received
■ 0x1 (INT): INT MSG received
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-69 Fields for Register: UHS_II_DEV_INTR_STATUS_R (Continued)

Memory
Bits Name Access Description

10 DEV_INTR_STATUS10 R/W1C This bit indicates that the INT MSG is received from Device
ID 10.
Values:
■ 0x0 (NO_INT): No INT MSG received
■ 0x1 (INT): INT MSG received
Value After Reset: 0x0
Exists: Always
Volatile: true

9 DEV_INTR_STATUS9 R/W1C This bit indicates that the INT MSG is received from Device
ID 9.
Values:
■ 0x0 (NO_INT): No INT MSG received
■ 0x1 (INT): INT MSG received
Value After Reset: 0x0
Exists: Always
Volatile: true

8 DEV_INTR_STATUS8 R/W1C This bit indicates that the INT MSG is received from Device
ID 8.
Values:
■ 0x0 (NO_INT): No INT MSG received
■ 0x1 (INT): INT MSG received
Value After Reset: 0x0
Exists: Always
Volatile: true

7 DEV_INTR_STATUS7 R/W1C This bit indicates that the INT MSG is received from Device
ID 7.
Values:
■ 0x0 (NO_INT): No INT MSG received
■ 0x1 (INT): INT MSG received
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-69 Fields for Register: UHS_II_DEV_INTR_STATUS_R (Continued)

Memory
Bits Name Access Description

6 DEV_INTR_STATUS6 R/W1C This bit indicates that the INT MSG is received from Device
ID 6.
Values:
■ 0x0 (NO_INT): No INT MSG received
■ 0x1 (INT): INT MSG received
Value After Reset: 0x0
Exists: Always
Volatile: true

5 DEV_INTR_STATUS5 R/W1C This bit indicates that the INT MSG is received from Device
ID 5.
Values:
■ 0x0 (NO_INT): No INT MSG received
■ 0x1 (INT): INT MSG received
Value After Reset: 0x0
Exists: Always
Volatile: true

4 DEV_INTR_STATUS4 R/W1C This bit indicates that the INT MSG is received from Device
ID 4.
Values:
■ 0x0 (NO_INT): No INT MSG received
■ 0x1 (INT): INT MSG received
Value After Reset: 0x0
Exists: Always
Volatile: true

3 DEV_INTR_STATUS3 R/W1C This bit indicates that the INT MSG is received from Device
ID 3.
Values:
■ 0x0 (NO_INT): No INT MSG received
■ 0x1 (INT): INT MSG received
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-69 Fields for Register: UHS_II_DEV_INTR_STATUS_R (Continued)

Memory
Bits Name Access Description

2 DEV_INTR_STATUS2 R/W1C This bit indicates that the INT MSG is received from Device
ID 2.
Values:
■ 0x0 (NO_INT): No INT MSG received
■ 0x1 (INT): INT MSG received
Value After Reset: 0x0
Exists: Always
Volatile: true

1 DEV_INTR_STATUS1 R/W1C This bit indicates that the INT MSG is received from Device
ID 1.
Values:
■ 0x0 (NO_INT): No INT MSG received
■ 0x1 (INT): INT MSG received
Value After Reset: 0x0
Exists: Always
Volatile: true

0 DEV_INTR_STATUS0 R/W1C This bit of the UHS_II_DEV_INTR_STATUS_R register is

reserved. It always returns 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.65 UHS_II_DEV_SEL_R
■ Name: UHS-II Device Select Register
■ Description: This register is used to select the UHS-II device from which INT message is received.
This register is applicable for UHS-II mode only.
■ Size: 8 bits
■ Offset: 0xbe
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

RESERVED_6_4 6:4
3:0
7
INT_MSG_EN

DEV_SEL

Table 5-70 Fields for Register: UHS_II_DEV_SEL_R

Memory
Bits Name Access Description

7 INT_MSG_EN R/W INT MSG Enable

This bit enables receipt of the INT MSG. If this bit is set to 1,
receipt of INT MSG is informed by the Card Interrupt in the
Normal Interrupt Status register. If this bit is set to 0,the Host
Controller ignores receipt of INT MSG and may not set the
UHS-II Device Interrupt Code register.
Support of INT MSG Interrupt is optional. If an attempt is
made to set this bit to 1 while this bit is read 0, the INT MSG
Interrupt is not supported by the Host Controller. In this case,
the UHS-II Device Interrupt Status register always reads 0
and the UHS-II Device Interrupt Code register may not be
implemented.
Values:
■ 0x0 (DISABLE_INT_MSG): Reception of INT MSG is
disabled
■ 0x1 (ENABLE_INT_MSG): Reception of INT MSG is
enabled
Value After Reset: 0x0
Exists: Always

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Table 5-70 Fields for Register: UHS_II_DEV_SEL_R (Continued)

Memory
Bits Name Access Description

6:4 RESERVED_6_4 R These bits of the UHS_II_DEV_SEL_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

3:0 DEV_SEL R/W UHS-II Device Select

Host controller holds an INT MSG packet per device. One of
the INT MSGs (up to 15) can be selected by this field and
read from UHS-II Device Interrupt Code register(0BFh). This
field is effective when INT MSG Enable is set to 1.
The number of devices implemented in the Host Controller is
indicated by the Number of Devices Supported in the UHS-II
General Capabilities register.
■ 0x0 : Unselected (Default)
■ 0x1 : INT MSG of Device ID 1 is selected
■ 0x2 : INT MSG of Device ID 2 is selected
■ ........
■ ........
■ ........
■ 0xF : INT MSG of Device ID 15 is selected
Value After Reset: 0x0
Exists: Always

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5.1.66 UHS_II_DEV_INR_CODE_R
■ Name: UHS-II Device Interrupt Code Register
■ Description: This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select
register. Host Controller holds an INT MSG packet per device. One of INT MSGs (Code length is 1
byte) upto 15 can be read from this register by selecting UHS-II Device Select. The number of the
registers to hold INT MSGs is determined by Number of Devices Supported in the UHS-II General
Capabilities register. Device ID is supposed to be assigned from 1 sequentially at the UHS-II
initialization. This register is applicable for UHS-II mode only.
■ Size: 8 bits
■ Offset: 0xbf
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

DEV_INTR_CODE 7:0

Table 5-71 Fields for Register: UHS_II_DEV_INR_CODE_R

Memory
Bits Name Access Description

7:0 DEV_INTR_CODE R Device Interrupt Code

These bits specify the INT MSG Packet of the selected
device.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.67 UHS_II_SOFT_RESET_R
■ Name: UHS-II Software Reset Register
■ Description: This register is used to enable UHS-II software resets. This register is applicable for
UHS-II mode only.
■ Size: 16 bits
■ Offset: 0xc0
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

15:2
HOST_SD_TRAN_RST 1
0
HOST_FULL_RST
RESERVED_15_2

Table 5-72 Fields for Register: UHS_II_SOFT_RESET_R

Memory
Bits Name Access Description

15:2 RESERVED_15_2 R These bits of UHS_II_SOFT_RESET_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-72 Fields for Register: UHS_II_SOFT_RESET_R (Continued)

Memory
Bits Name Access Description

1 HOST_SD_TRAN_RST R/W Host SD-TRAN Reset

This bit is set to 1 by the Host Driver to reset the SD-TRAN
layer when an Abort command or CMD0 is issued to the
device or when a data transfer error occurs. This bit is
cleared automatically at completion. If CMD0 is issued, SD-
TRAN Initialization sequence from CMD8 is required to use
UHS-II mode assuming that the bus power is maintained.
Note that CM-TRAN Initialization is not required.
The Host Controller does the following:
■ SD Clock Enable is maintained (Continue to provide
RCLK).
■ All setting register is maintained.
■ Internal sequences are reset to be able to issue a
command.
■ All Interrupt Status, Status Enable and Signal Enable are
cleared.
■ Data transfer is terminated and data in buffer is
discarded.

Values:
■ 0x0 (FALSE): Continue normal operation
■ 0x1 (TRUE): Reset SD-TRAN
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-72 Fields for Register: UHS_II_SOFT_RESET_R (Continued)

Memory
Bits Name Access Description

0 HOST_FULL_RST R/W Host Full Reset

This bit is set by the Host Driver to reset Host controller, on
issuing the FULL_RESET CCMD (to reset the device). This
bit is automatically cleared on completion of the Host
controller reset. The initialization sequence from PHY
initialization is required to use the UHS-II mode considering
that the bus power is maintained.
The Host Controller does the following:
■ SD Clock Enable is cleared (Internal Clock is still
synchronized)
■ All setting registers are cleared
■ Internal sequencers are reset to same the values as
those just after power on
■ Interrupt Status, Status Enable, and Signal Enable are
cleared

Values:
■ 0x0 (FALSE): Continue normal operation
■ 0x1 (TRUE): Reset Host controller
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.68 UHS_II_TIMER_CNTRL_R
■ Name: UHS-II Timer Control Register
■ Description: This register is used to control the UHS-II timeout counters. This register is applicable
for UHS-II mode only.
■ Size: 16 bits
■ Offset: 0xc2
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

15:8
7:4
TIMEOUT_CNT_CMD_RES 3:0
TIMER_CNT_DEADLOCK
RESERVED_15_8

Table 5-73 Fields for Register: UHS_II_TIMER_CNTRL_R

Memory
Bits Name Access Description

15:8 RESERVED_15_8 R These bits of the UHS_II_TIMER_CNTRL_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-73 Fields for Register: UHS_II_TIMER_CNTRL_R (Continued)

Memory
Bits Name Access Description

7:4 TIMER_CNT_DEADLOCK R/W Timeout Counter Value for Deadlock

These bits determine the deadlock period while the host is
expecting to receive any packet other than the response
packet (1 second). While setting these bits, prevent
inadvertent timeout events by clearing the Timeout for
Deadlock (in the UHS-II Error Interrupt Status Enable
register). TMCLK represents the timer clock. DWC_mshc
has an extra clock input specifically for the timer. The timeout
counter value must be programmed considering the timer
clock frequency.
■ 0xF : Reserved
■ 0xE : TMCLK x 2^27
■ .......
■ .......
■ .......
■ 0x1 : TMCLK x 2^14
■ 0x0 : TMCLK x 2^13

Note: The Host driver can get information about the timer
clock frequency from the Capabilities register
(Capabilities_1_R). The Timer clock frequency for
DWC_mshc must be configured using the
DWC_MSHC_TIMER_CLK_FREQ_UNIT and the
DWC_MSHC_TIMER_CLK_FREQ parameters.
Value After Reset: 0x0
Exists: Always

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Table 5-73 Fields for Register: UHS_II_TIMER_CNTRL_R (Continued)

Memory
Bits Name Access Description

3:0 TIMEOUT_CNT_CMD_RES R/W Timeout Counter Value for CMD_RES

These bits determine the interval between the command
packet and the response packet(5ms). While setting this
register, prevent inadvertent timeout events by clearing the
Time out for CMD_RES (in the UHS-II Error Interrupt Status
Enable register). TMCLK represents the timer clock.
DWC_mshc has an extra clock input specifically for the timer
(tmclk). The timeout counter value must be programmed
considering timer clock frequency.
■ 0xF : Reserved
■ 0xE : TMCLK x 2^27
■ .......
■ .......
■ .......
■ 0x1 : TMCLK x 2^14
■ 0x0 : TMCLK x 2^13

Note: Host driver can get information about timer clock

frequency from Capabilities register (Capabilities_1_R).
Timer clock frequency for DWC_mshc must be configured
using parameters DWC_MSHC_TIMER_CLK_FREQ_UNIT
and DWC_MSHC_TIMER_CLK_FREQ.
Value After Reset: 0x0
Exists: Always

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5.1.69 UHS_II_ERR_INTR_STATUS_R
■ Name: UHS-II Error Interrupt Status Register
■ Description: When any of these fields is set to 1, Error Interrupt in the Normal Interrupt Status
register is set to 1. Note that the duplicate MSG packets are sent from the UHS-II card during the data
transfer as described in the UHS-II Addendum. If either of these packets is recognized as wrong, the
Host controller does not assert an error interrupt while continuing with the data transfer. This
register is applicable for UHS-II mode only.
■ Size: 32 bits
■ Offset: 0xc4
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1) 26:18

14:9
VENDOR_SPECIFIC_ERR4 31
VENDOR_SPECIFIC_ERR3 30
VENDOR_SPECIFIC_ERR2 29
VENDOR_SPECIFIC_ERR1 28
VENDOR_SPECIFIC_ERR0 27

17
16
15

8
7
6
5
4
3
2
1
0
UNRECOVERABLE_ERR
TIMEOUT_DEADLOCK
TIMEOUT_CMD_RES
RESERVED_26_18

RETRY_EXPIRED
RESERVED_14_9

FRAMING_ERR

RES_PKT_ERR
HEADER_ERR
RESERVED_6
ADMA_ERR

EBSY_ERR

CRC_ERR
TID_ERR

Table 5-74 Fields for Register: UHS_II_ERR_INTR_STATUS_R

Memory
Bits Name Access Description

31 VENDOR_SPECIFIC_ERR4 R/W1C This bit (VENDOR_SPECIFIC_ERR4) of the

UHS_II_ERR_INTR_STATUS_R register is reserved. It
always returns 0.
Values:
■ 0x0 (FALSE): Interrupt is not generated
■ 0x1 (TRUE): Vendor Specific Error
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-74 Fields for Register: UHS_II_ERR_INTR_STATUS_R (Continued)

Memory
Bits Name Access Description

30 VENDOR_SPECIFIC_ERR3 R/W1C This bit (VENDOR_SPECIFIC_ERR3) of the

UHS_II_ERR_INTR_STATUS_R register is reserved. It
always returns 0.
Values:
■ 0x0 (FALSE): Interrupt is not generated
■ 0x1 (TRUE): Vendor Specific Error
Value After Reset: 0x0
Exists: Always
Volatile: true

29 VENDOR_SPECIFIC_ERR2 R/W1C This bit (VENDOR_SPECIFIC_ERR2) of the

UHS_II_ERR_INTR_STATUS_R register is reserved. It
always returns 0.
Values:
■ 0x0 (FALSE): Interrupt is not generated
■ 0x1 (TRUE): Vendor Specific Error
Value After Reset: 0x0
Exists: Always
Volatile: true

28 VENDOR_SPECIFIC_ERR1 R/W1C This bit (VENDOR_SPECIFIC_ERR1) of the

UHS_II_ERR_INTR_STATUS_R register is reserved. It
always returns 0.
Values:
■ 0x0 (FALSE): Interrupt is not generated
■ 0x1 (TRUE): Vendor Specific Error
Value After Reset: 0x0
Exists: Always
Volatile: true

27 VENDOR_SPECIFIC_ERR0 R/W1C This bit (VENDOR_SPECIFIC_ERR0) of the

UHS_II_ERR_INTR_STATUS_R register is reserved. It
always returns 0.
Values:
■ 0x0 (FALSE): Interrupt is not generated
■ 0x1 (TRUE): Vendor Specific Error
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-74 Fields for Register: UHS_II_ERR_INTR_STATUS_R (Continued)

Memory
Bits Name Access Description

26:18 RESERVED_26_18 R These bits (RESERVED_26_18) of the

UHS_II_ERR_INTR_STATUS_R register are reserved bits.
They always return 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

17 TIMEOUT_DEADLOCK R/W1C Timeout for Deadlock

Setting this bit indicates that a deadlock timeout has
occurred. When the Host expects to receive a packet and if
does not receive it within a specified time (1 second), then
this bit is set to 1. The Timeout value is determined by the
setting of Timeout Counter Value for Deadlock in UHS-II
Timer Control register.
Values:
■ 0x0 (FALSE): Interrupt is not generated
■ 0x1 (TRUE): Timeout for Deadlock Error
Value After Reset: 0x0
Exists: Always
Volatile: true

16 TIMEOUT_CMD_RES R/W1C Timeout for CMD_RES

Setting of this bit indicates that an RES packet timeout has
occurred. When the Host expects to receive a RES packet
and if does not receive it within a specified time (5ms), then
this bit is set to 1. The Timeout value is determined by the
setting of Timeout Counter Value for CMD_RES in UHS-II
Timer Control register.
Values:
■ 0x0 (FALSE): Interrupt is not generated
■ 0x1 (TRUE): Timeout for CMD_RES Error
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-74 Fields for Register: UHS_II_ERR_INTR_STATUS_R (Continued)

Memory
Bits Name Access Description

15 ADMA_ERR R/W1C ADMA Error

This bit denotes that an ADMA error has occurred in the
UHS-II mode. The ADMA error status is indicated in the
ADMA Error Status register.
Note: There are two ADMA Error bits. One is in Error
Interrupt Status register and other one is in the UHS-II Error
Interrupt Status register. The former must be enabled and
used for SD mode, and latter must be enabled and used for
UHS-II mode.
Values:
■ 0x0 (FALSE): Interrupt is not generated
■ 0x1 (TRUE): ADMA Error
Value After Reset: 0x0
Exists: Always
Volatile: true

14:9 RESERVED_14_9 R These bits (RESERVED_14_9) of the

UHS_II_ERR_INTR_STATUS_R register are reserved. They
always return 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

8 EBSY_ERR R/W1C EBSY Error

This bit is set if a packet indicates an error after receiving an
EBSY packet. If the EBSY wait bit in UHS-II Transfer mode
register is set, the Transfer complete interrupt in the Normal
Interrupt Status register is set along with the Error Interrupt if
the EBSY packet indicated an error.
Values:
■ 0x0 (FALSE): Interrupt is not generated
■ 0x1 (TRUE): EBSY Error
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-74 Fields for Register: UHS_II_ERR_INTR_STATUS_R (Continued)

Memory
Bits Name Access Description

7 UNRECOVERABLE_ERR R/W1C Unrecoverable Error

Setting of this bit means that Unrecoverable error is set in a
packet from a device.
Values:
■ 0x0 (FALSE): Interrupt is not generated
■ 0x1 (TRUE): Unrecoverable Error
Value After Reset: 0x0
Exists: Always
Volatile: true

6 RESERVED_6 R This bit (RESERVED_6) of the

UHS_II_ERR_INTR_STATUS_R register is reserved. It
always returns 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

5 TID_ERR R/W1C TID Error

This bit indicates that a TID error has occurred. The Host
controller checks the Transaction ID (TID) of the command
with that of received packets in a transfer. If there is any
mismatch, a TID error is generated.
Values:
■ 0x0 (FALSE): Interrupt is not generated
■ 0x1 (TRUE): TID Error
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-74 Fields for Register: UHS_II_ERR_INTR_STATUS_R (Continued)

Memory
Bits Name Access Description

4 FRAMING_ERR R/W1C Framing Error

This bit indicates that a Framing error has occurred while
receiving a packet.
Note: This bit is not set in following scenarios even if
Framing error occurs while receiving a packet:
■ Framing error occurs in receiving one of the two duplicate
MSG packets and the other is received correctly.
■ Framing error occurs in receiving data packets and a retry
counter has not yet expired.

Values:
■ 0x0 (FALSE): Interrupt is not generated
■ 0x1 (TRUE): Framing Error
Value After Reset: 0x0
Exists: Always
Volatile: true

3 CRC_ERR R/W1C CRC Error

This bit indicates that a CRC error has occurred while
receiving a packet.
Note: This bit is not set in the following two scenarios even if
CRC error occurs while receiving a packet.
■ CRC error occurs in receiving one of two duplicate MSG
packets and the other is received correctly.
■ CRC error occurs in receiving data packets and the retry
counter has not yet expired.

Values:
■ 0x0 (FALSE): Interrupt is not generated
■ 0x1 (TRUE): CRC Error
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-74 Fields for Register: UHS_II_ERR_INTR_STATUS_R (Continued)

Memory
Bits Name Access Description

2 RETRY_EXPIRED R/W1C Retry Expired Error

This bit indicates that the Retry Counter Expired Error has
occurred during data transfer. If this bit is set, either a
Framing Error or a CRC Error in this register is set. Retry
count must be programmed in the UHS-II LINK/TRAN
Settings register.
Values:
■ 0x0 (FALSE): Interrupt is not generated
■ 0x1 (TRUE): Retry expired Error
Value After Reset: 0x0
Exists: Always
Volatile: true

1 RES_PKT_ERR R/W1C RES Packet Error

Host controller version 4.00 supports response error check
function to avoid overhead of response error check by Host
Driver during DMA execution. If Response Error Check
Enable is set to 1 in the UHS-II Transfer mode register, Host
Controller Checks R1 or R5 response. If an error is detected
in a response, this bit is set to 1.
Note: Refer the Response Type field of the UHS-II Transfer
Mode register to know the errors that are checked by the
Host controller.
Values:
■ 0x0 (FALSE): Interrupt is not generated
■ 0x1 (TRUE): RES Packet Error
Value After Reset: 0x0
Exists: Always
Volatile: true

0 HEADER_ERR R/W1C Header Error

This bit indicates that a Header error has occurred in a
received packet. The Host controller checks the Destination
ID and the Transaction ID of the command with the received
packets (RES, MSG and DATA) in a transfer. If there is any
mismatch, this error is generated.
Values:
■ 0x0 (FALSE): Interrupt is not generated
■ 0x1 (TRUE): Header Error
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.1.70 UHS_II_ERR_INTR_STATUS_EN_R
■ Name: UHS-II Error Interrupt Status Enable Register
■ Description: This register is used to enable setting of error bits in the UHS-II Error Interrupt Status
register. This register is applicable for UHS-II mode only.
■ Size: 32 bits
■ Offset: 0xc8
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

26:18

14:9
VENDOR_SPECIFIC_ERR4 31
VENDOR_SPECIFIC_ERR3 30
VENDOR_SPECIFIC_ERR2 29
VENDOR_SPECIFIC_ERR1 28
VENDOR_SPECIFIC_ERR0 27

17
16
15

8
7
6
5
4
3
2
1
0
UNRECOVERABLE_ERR
TIMEOUT_DEADLOCK
TIMEOUT_CMD_RES
RESERVED_26_18

RETRY_EXPIRED
RESERVED_14_9

FRAMING_ERR

RES_PKT_ERR
HEADER_ERR
RESERVED_6
ADMA_ERR

EBSY_ERR

CRC_ERR
TID_ERR

Table 5-75 Fields for Register: UHS_II_ERR_INTR_STATUS_EN_R

Memory
Bits Name Access Description

31 VENDOR_SPECIFIC_ERR4 R/W This bit (VENDOR_SPECIFIC_ERR4) of the

UHS_II_ERR_INTR_STATUS_EN_R register is reserved. It
always returns 0.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

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Table 5-75 Fields for Register: UHS_II_ERR_INTR_STATUS_EN_R (Continued)

Memory
Bits Name Access Description

30 VENDOR_SPECIFIC_ERR3 R/W This bit (VENDOR_SPECIFIC_ERR3) of the

UHS_II_ERR_INTR_STATUS_EN_R register is reserved. It
always returns 0.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

29 VENDOR_SPECIFIC_ERR2 R/W This bit (VENDOR_SPECIFIC_ERR2) of the

UHS_II_ERR_INTR_STATUS_EN_R register is reserved. It
always returns 0.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

28 VENDOR_SPECIFIC_ERR1 R/W This bit (VENDOR_SPECIFIC_ERR1) of the

UHS_II_ERR_INTR_STATUS_EN_R register is reserved. It
always returns 0.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

27 VENDOR_SPECIFIC_ERR0 R/W This bit (VENDOR_SPECIFIC_ERR0) of the

UHS_II_ERR_INTR_STATUS_EN_R register is reserved. It
always returns 0.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

26:18 RESERVED_26_18 R These bits (RESERVED_26_18) of the

UHS_II_ERR_INTR_STATUS_EN_R register are reserved.
They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-75 Fields for Register: UHS_II_ERR_INTR_STATUS_EN_R (Continued)

Memory
Bits Name Access Description

17 TIMEOUT_DEADLOCK R/W Timeout for Deadlock

This bit sets the Timeout for Deadlock bit in the UHS-II Error
Interrupt Status register.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

16 TIMEOUT_CMD_RES R/W Timeout for CMD_RES

This bit sets the Timeout for CMD_RES bit in the UHS-II
Error Interrupt Status register.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

15 ADMA_ERR R/W ADMA Error

This bit sets the ADMA Error bit in the UHS-II Error Interrupt
Status register.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

14:9 RESERVED_14_9 R These bits (RESERVED_14_9) of

UHS_II_ERR_INTR_STATUS_EN_R register are reserved.
They always return 0.
Value After Reset: 0x0
Exists: Always

8 EBSY_ERR R/W EBSY Error

This bit sets the EBSY Error bit in the UHS-II Error Interrupt
Status register.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

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Table 5-75 Fields for Register: UHS_II_ERR_INTR_STATUS_EN_R (Continued)

Memory
Bits Name Access Description

7 UNRECOVERABLE_ERR R/W Unrecoverable Error

This bit sets the Unrecoverable Error bit in the UHS-II Error
Interrupt Status register.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

6 RESERVED_6 R This bit (RESERVED_6) of the

UHS_II_ERR_INTR_STATUS_EN_R register is reserved. It
always returns 0.
Value After Reset: 0x0
Exists: Always

5 TID_ERR R/W TID Error

This bit sets the TID Error bit in the UHS-II Error Interrupt
Status register.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

4 FRAMING_ERR R/W Framing Error

This bit sets the Framing Error bit in the UHS-II Error
Interrupt Status register.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

3 CRC_ERR R/W CRC Error

This bit sets the CRC Error bit in the UHS-II Error Interrupt
Status register.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

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Table 5-75 Fields for Register: UHS_II_ERR_INTR_STATUS_EN_R (Continued)

Memory
Bits Name Access Description

2 RETRY_EXPIRED R/W Retry Expired Error

This bit sets the Retry Expired Error bit in the UHS-II Error
Interrupt Status register.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

1 RES_PKT_ERR R/W RES Packet Error

This bit sets the RES Packet Error bit in the UHS-II Error
Interrupt Status register.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

0 HEADER_ERR R/W Header Error

This bit sets the Header Error bit in the UHS-II Error Interrupt
Status register.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

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5.1.71 UHS_II_ERR_INTR_SIGNAL_EN_R
■ Name: UHS-II Error Interrupt Signal Enable Register
■ Description: This register is used to enable the generation of interrupt signals. This register is
applicable for UHS-II mode only.
■ Size: 32 bits
■ Offset: 0xcc
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

26:18

14:9
VENDOR_SPECIFIC_ERR4 31
VENDOR_SPECIFIC_ERR3 30
VENDOR_SPECIFIC_ERR2 29
VENDOR_SPECIFIC_ERR1 28
VENDOR_SPECIFIC_ERR0 27

17
16
15

8
7
6
5
4
3
2
1
0
UNRECOVERABLE_ERR
TIMEOUT_DEADLOCK
TIMEOUT_CMD_RES
RESERVED_26_18

RETRY_EXPIRED
RESERVED_14_9

FRAMING_ERR

RES_PKT_ERR
HEADER_ERR
RESERVED_6
ADMA_ERR

EBSY_ERR

CRC_ERR
TID_ERR

Table 5-76 Fields for Register: UHS_II_ERR_INTR_SIGNAL_EN_R

Memory
Bits Name Access Description

31 VENDOR_SPECIFIC_ERR4 R/W This bit (VENDOR_SPECIFIC_ERR4) of the

UHS_II_ERR_INTR_SIGNAL_EN_R register is reserved. It
always returns 0.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

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Table 5-76 Fields for Register: UHS_II_ERR_INTR_SIGNAL_EN_R (Continued)

Memory
Bits Name Access Description

30 VENDOR_SPECIFIC_ERR3 R/W This bit (VENDOR_SPECIFIC_ERR3) of the

UHS_II_ERR_INTR_SIGNAL_EN_R register is reserved. It
always returns 0.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

29 VENDOR_SPECIFIC_ERR2 R/W This bit (VENDOR_SPECIFIC_ERR2) of the

UHS_II_ERR_INTR_SIGNAL_EN_R register is reserved. It
always returns 0.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

28 VENDOR_SPECIFIC_ERR1 R/W This bit (VENDOR_SPECIFIC_ERR1) of the

UHS_II_ERR_INTR_SIGNAL_EN_R register is reserved. It
always returns 0.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

27 VENDOR_SPECIFIC_ERR0 R/W This bit (VENDOR_SPECIFIC_ERR0) of the

UHS_II_ERR_INTR_SIGNAL_EN_R register is reserved. It
always returns 0.
Values:
■ 0x0 (DISABLE): Status is disabled
■ 0x1 (ENABLE): Status is enabled
Value After Reset: 0x0
Exists: Always

26:18 RESERVED_26_18 R These bits (RESERVED_26_18) of the

UHS_II_ERR_INTR_SIGNAL_EN_R register are reserved
bits. They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-76 Fields for Register: UHS_II_ERR_INTR_SIGNAL_EN_R (Continued)

Memory
Bits Name Access Description

17 TIMEOUT_DEADLOCK R/W Timeout for Deadlock

This bit generates the interrupt signal when Timeout for
Deadlock bit is set in the UHS-II Error Interrupt Status
register.
Values:
■ 0x0 (DISABLE): Interrupt signal is disabled
■ 0x1 (ENABLE): Interrupt signal is enabled
Value After Reset: 0x0
Exists: Always

16 TIMEOUT_CMD_RES R/W Timeout for CMD_RES

This bit generates the interrupt signal when Timeout for
CMD_RES bit is set in the UHS-II Error Interrupt Status
register.
Values:
■ 0x0 (DISABLE): Interrupt signal is disabled
■ 0x1 (ENABLE): Interrupt signal is enabled
Value After Reset: 0x0
Exists: Always

15 ADMA_ERR R/W ADMA Error

This bit generates the interrupt signal when ADMA Error bit
is set in the UHS-II Error Interrupt Status register.
Values:
■ 0x0 (DISABLE): Interrupt signal is disabled
■ 0x1 (ENABLE): Interrupt signal is enabled
Value After Reset: 0x0
Exists: Always

14:9 RESERVED_14_9 R These bits (RESERVED_14_9) of the

UHS_II_ERR_INTR_SIGNAL_EN_R register are reserved.
They always return 0.
Value After Reset: 0x0
Exists: Always

8 EBSY_ERR R/W EBSY Error

This bit generates the interrupt signal when EBSY Error bit is
set in the UHS-II Error Interrupt Status register.
Values:
■ 0x0 (DISABLE): Interrupt signal is disabled
■ 0x1 (ENABLE): Interrupt signal is enabled
Value After Reset: 0x0
Exists: Always

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Table 5-76 Fields for Register: UHS_II_ERR_INTR_SIGNAL_EN_R (Continued)

Memory
Bits Name Access Description

7 UNRECOVERABLE_ERR R/W Unrecoverable Error

This bit generates the interrupt signal when the
Unrecoverable Error bit is set in the UHS-II Error Interrupt
Status register.
Values:
■ 0x0 (DISABLE): Interrupt signal is disabled
■ 0x1 (ENABLE): Interrupt signal is enabled
Value After Reset: 0x0
Exists: Always

6 RESERVED_6 R This bit (RESERVED_6) of the

UHS_II_ERR_INTR_SIGNAL_EN_R register is reserved. It
always returns 0.
Value After Reset: 0x0
Exists: Always

5 TID_ERR R/W TID Error

This bit generates the interrupt signal when TID Error bit is
set in the UHS-II Error Interrupt Status register.
Values:
■ 0x0 (DISABLE): Interrupt signal is disabled
■ 0x1 (ENABLE): Interrupt signal is enabled
Value After Reset: 0x0
Exists: Always

4 FRAMING_ERR R/W Framing Error

This bit generates the interrupt signal when Framing Error bit
is set in the UHS-II Error Interrupt Status register.
Values:
■ 0x0 (DISABLE): Interrupt signal is disabled
■ 0x1 (ENABLE): Interrupt signal is enabled
Value After Reset: 0x0
Exists: Always

3 CRC_ERR R/W CRC Error

This bit generates the interrupt signal when the CRC Error
bit is set in the UHS-II Error Interrupt Status register.
Values:
■ 0x0 (DISABLE): Interrupt signal is disabled
■ 0x1 (ENABLE): Interrupt signal is enabled
Value After Reset: 0x0
Exists: Always

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Table 5-76 Fields for Register: UHS_II_ERR_INTR_SIGNAL_EN_R (Continued)

Memory
Bits Name Access Description

2 RETRY_EXPIRED R/W Retry Expired Error

This bit generates the interrupt signal when the Retry
Expired Error bit is set in the UHS-II Error Interrupt Status
register.
Values:
■ 0x0 (DISABLE): Interrupt signal is disabled
■ 0x1 (ENABLE): Interrupt signal is enabled
Value After Reset: 0x0
Exists: Always

1 RES_PKT_ERR R/W RES Packet Error

This bit generates the interrupt signal when the RES Packet
Error bit is set in the UHS-II Error Interrupt Status register.
Values:
■ 0x0 (DISABLE): Interrupt signal is disabled
■ 0x1 (ENABLE): Interrupt signal is enabled
Value After Reset: 0x0
Exists: Always

0 HEADER_ERR R/W Header Error

This bit generates the interrupt signal when the Header Error
bit is set in the UHS-II Error Interrupt Status register.
Values:
■ 0x0 (DISABLE): Interrupt signal is disabled
■ 0x1 (ENABLE): Interrupt signal is enabled
Value After Reset: 0x0
Exists: Always

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5.1.72 P_UHS_II_SETTINGS_R
■ Name: Pointer for UHS-II Settings
■ Description: This register points to the location of UHS-II Settings register. There are three types of
UHS-II Settings registers, namely UHS-II General Settings register, UHS-II PHY Settings register, and
UHS-II LINK/TRAN Settings register. The start address of the General Settings register is pointed by
the pointer for the UHS-II Setting register. This register is applicable for UHS-II mode only.
■ Size: 16 bits
■ Offset: 0xe0
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

15:12
REG_OFFSET_ADDR 11:0
RESERVED_15_12

Table 5-77 Fields for Register: P_UHS_II_SETTINGS_R

Memory
Bits Name Access Description

15:12 RESERVED_15_12 R These bits of the P_UHS_II_SETTINGS_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

11:0 REG_OFFSET_ADDR R Offset Address of UHS-II Host Settings register.

Value After Reset: DWC_MSHC_PTR_UHS2_SETTING
Exists: Always

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5.1.73 P_UHS_II_HOST_CAPAB
■ Name: Pointer for UHS-II Host Capabilities
■ Description: This register points to the location of the UHS-II Host Capabilities register. There are
three types of UHS-II Host Capabilities registers, namely UHS-II General Capabilities register, UHS-
II Capabilities Setting register, and UHS-II LINK/TRAN Capabilities register. The start address of
the General Capabilities register is pointed by the pointer for the UHS-II Host Capabilities register.
This register is applicable for UHS-II mode only.
■ Size: 16 bits
■ Offset: 0xe2
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

15:12
REG_OFFSET_ADDR 11:0
RESERVED_15_12

Table 5-78 Fields for Register: P_UHS_II_HOST_CAPAB

Memory
Bits Name Access Description

15:12 RESERVED_15_12 R These bits of the P_UHS_II_HOST_CAPAB register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

11:0 REG_OFFSET_ADDR R Offset Address for UHS-II Host Capabilities register.

Value After Reset: DWC_MSHC_PTR_UHS2_CAPABILITY
Exists: Always

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5.1.74 P_UHS_II_TEST
■ Name: Pointer for UHS-II Test
■ Description: This register points to the location of UHS-II test registers.
■ Size: 16 bits
■ Offset: 0xe4
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

15:12
REG_OFFSET_ADDR 11:0
RESERVED_15_12

Table 5-79 Fields for Register: P_UHS_II_TEST

Memory
Bits Name Access Description

15:12 RESERVED_15_12 R These bits of the P_UHS_II_TEST register are reserved.

They always return 0.
Value After Reset: 0x0
Exists: Always

11:0 REG_OFFSET_ADDR R Offset Address of UHS-II Test register.

Value After Reset: DWC_MSHC_PTR_UHS2_TEST
Exists: Always

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5.1.75 P_EMBEDDED_CNTRL
■ Name: Pointer for Embedded Control
■ Description: This register points to the location of UHS-II embedded control registers.
■ Size: 16 bits
■ Offset: 0xe6
■ Exists: Always

15:12
REG_OFFSET_ADDR 11:0
RESERVED_15_12

Table 5-80 Fields for Register: P_EMBEDDED_CNTRL

Memory
Bits Name Access Description

15:12 RESERVED_15_12 R These bits of the P_EMBEDDED_CNTRL register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

11:0 REG_OFFSET_ADDR R Offset Address of Embedded Control register.

Value After Reset: DWC_MSHC_PTR_EMBDCTL
Exists: Always

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5.1.76 P_VENDOR_SPECIFIC_AREA
■ Name: Pointer for Vendor Specific Area 1
■ Description: This register used as a pointer for the Vendor Specific Area 1.
■ Size: 16 bits
■ Offset: 0xe8
■ Exists: Always

15:12
REG_OFFSET_ADDR 11:0
RESERVED_15_12

Table 5-81 Fields for Register: P_VENDOR_SPECIFIC_AREA

Memory
Bits Name Access Description

15:12 RESERVED_15_12 R These bits of the P_VENDOR_SPECIFIC_AREA register

are reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

11:0 REG_OFFSET_ADDR R Base offset Address for Vendor-Specific registers.

Value After Reset: DWC_MSHC_PTR_VENDOR1
Exists: Always

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5.1.77 P_VENDOR2_SPECIFIC_AREA
■ Name: Pointer for Vendor Specific Area 2
■ Description: This register is used as a pointer for the Vendor Specific Area 2.
■ Size: 16 bits
■ Offset: 0xea
■ Exists: Always

REG_OFFSET_ADDR 15:0

Table 5-82 Fields for Register: P_VENDOR2_SPECIFIC_AREA

Memory
Bits Name Access Description

15:0 REG_OFFSET_ADDR R Base offset Address for Command Queuing registers.

Value After Reset: DWC_MSHC_PTR_VENDOR2
Exists: Always

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5.1.78 SLOT_INTR_STATUS_R
■ Name: Slot Interrupt Status Register
■ Description: This register indicates the Interrupt status of each slot.
■ Size: 16 bits
■ Offset: 0xfc
■ Exists: Always

RESERVED_15_8 15:8
7:0
INTR_SLOT

Table 5-83 Fields for Register: SLOT_INTR_STATUS_R

Memory
Bits Name Access Description

15:8 RESERVED_15_8 R These bits of the SLOT_INTR_STATUS_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-83 Fields for Register: SLOT_INTR_STATUS_R (Continued)

Memory
Bits Name Access Description

7:0 INTR_SLOT R Interrupt signal for each Slot

These status bits indicate the logical OR of Interrupt signal
and Wakeup signal for each slot. A maximum of 8 slots can
be defined. If one interrupt signal is associated with multiple
slots, the Host Driver can identify the interrupt that is
generated by reading these bits. By a power on reset or by
setting Software Reset For All bit, the interrupt signals are
de-asserted and this status reads 00h.
■ Bit 00: Slot 1
■ Bit 01: Slot 2
■ Bit 02: Slot 3
■ ..........
■ ..........
■ Bit 07: Slot 8

Note: MSHC Host Controller support single card slot. This

register shall always return 0.

Value After Reset: 0x0

Exists: Always
Volatile: true

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5.1.79 HOST_CNTRL_VERS_R
■ Name: Host Controller Version
■ Description: This register is used to indicate the Host Controller Version number.
■ Size: 16 bits
■ Offset: 0xfe
■ Exists: Always

VENDOR_VERSION_NUM 15:8
7:0
SPEC_VERSION_NUM

Table 5-84 Fields for Register: HOST_CNTRL_VERS_R

Memory
Bits Name Access Description

15:8 VENDOR_VERSION_NUM R Vendor Version Number

This field is reserved for the vendor version number. Host
Driver must not use this status.
Value After Reset: DWC_MSHC_VENDOR_VER
Exists: Always

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Table 5-84 Fields for Register: HOST_CNTRL_VERS_R (Continued)

Memory
Bits Name Access Description

7:0 SPEC_VERSION_NUM R Specification Version Number

These bits indicate the Host controller specification version.
The upper and lower 4-bits indicate the version. Values
0x06-0xFF are reserved.
Values:
■ 0x0 (VER_1_00): SD Host Controller Specification
Version 1.00
■ 0x1 (VER_2_00): SD Host Controller Specification
Version 2.00
■ 0x2 (VER_3_00): SD Host Controller Specification
Version 3.00
■ 0x3 (VER_4_00): SD Host Controller Specification
Version 4.00
■ 0x4 (VER_4_10): SD Host Controller Specification
Version 4.10
■ 0x5 (VER_4_20): SD Host Controller Specification
Version 4.20
Value After Reset: DWC_MSHC_SD_SPEC_VER
Exists: Always

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5.2 DWC_mshc_map/DWC_mshc_UHS_II_setting_block Registers

This register block has UHS-II related setting registers. Follow the link for the register to see a detailed
description of the register.

Table 5-85 Registers for Address Block: DWC_mshc_map/DWC_mshc_UHS_II_setting_block

Register Offset Description

UHS2_GEN_SET_R on page 426 P_UHS_I UHS-II General Setting register

I_SETTIN
GS_R[11:
0]

UHS2_PHY_SET_R on page 428 P_UHS_I UHS-II Phy Setting register

I_SETTIN
GS_R[11:
0] + 0x4

UHS2_LNK_TRAN_SET_1_R on P_UHS_I UHS-II LINK/TRAN Setting register

page 431 I_SETTIN
GS_R[11:
0] + 0x8

UHS2_LNK_TRAN_SET_2_R on P_UHS_I UHS-II LINK/TRAN Setting 2 register

page 433 I_SETTIN
GS_R[11:
0] + 0xc

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5.2.1 UHS2_GEN_SET_R
■ Name: UHS-II General Setting register
■ Description: This register is used to configure general settings of UHS-II. This register is applicable
for UHS-II mode only.
■ Size: 32 bits
■ Offset: P_UHS_II_SETTINGS_R[11:0]
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

RSVD_31_12 31:12
11:8
7:1
0
PWR_MODE
NUM_LANE
RSVD_7_1

Table 5-86 Fields for Register: UHS2_GEN_SET_R

Memory
Bits Name Access Description

31:12 RSVD_31_12 R These bits of the UHS2_GEN_SET_R register are reserved.

They always return 0.
Value After Reset: 0x0
Exists: Always

11:8 NUM_LANE R/W Number of Lanes and Functionalities

These bits set the lane configuration of a Host System and
the value depends on the capability between the Host
Controller and the connected devices. A 2-lane FD mode is
mandatory and other modes are optional. Values 0x5-0xF
are reserved.
Values:
■ 0x0 (II_LANES): 2 Lanes FD or 2L-HD
■ 0x1 (NOT_USED): Not used
■ 0x2 (LANES_2D1U): 3 Lanes 2D1U-FD (Embedded)
■ 0x3 (LANES_1D2U): 3 Lanes 1D2U-FD (Embedded)
■ 0x4 (LANES_2D2U): 4 Lanes 2D2U-FD (Embedded)
Value After Reset: 0x0
Exists: Always

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Table 5-86 Fields for Register: UHS2_GEN_SET_R (Continued)

Memory
Bits Name Access Description

7:1 RSVD_7_1 R These bits of the UHS2_GEN_SET_R register are reserved

bits. They always return 0.
Value After Reset: 0x0
Exists: Always

0 PWR_MODE R/W Power mode

This bit determines either Fast Mode or Low Power Mode.
The Host and all the devices connected to the host are set to
the same mode.
Values:
■ 0x0 (FAST_MODE): Fast Mode
■ 0x1 (LOW_PWR_MODE): Low Power Mode
Value After Reset: 0x0
Exists: Always

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5.2.2 UHS2_PHY_SET_R
■ Name: UHS-II Phy Setting register
■ Description: This register is used to configure PHY settings of UHS-II. This register is applicable for
UHS-II mode only.
■ Size: 32 bits
■ Offset: P_UHS_II_SETTINGS_R[11:0] + 0x4
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

RSVD_31_24 31:24
23:20
19:16

14:8
SPD_RANGE 7:6
5:0
15
HBNATE_EN
N_LSS_SYN

RSVD_14_8
N_LSS_DIR

RSVD_5_0
Table 5-87 Fields for Register: UHS2_PHY_SET_R

Memory
Bits Name Access Description

31:24 RSVD_31_24 R These bits (RSVD_31_24) of the UHS2_PHY_SET_R

register are reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

23:20 N_LSS_DIR R/W Host N_LSS_DIR

This bit is set to the largest value of N_LSS_DIR capabilities
among the Host Controller and the connected devices.
■ 0x0 : 8x16 LSS
■ 0x1 : 8x1 LSS
■ 0x2 : 8x2 LSS
■ .......
■ .......
■ .......
■ 0xF : 8x15 LSS
Value After Reset: 0x0
Exists: Always

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Table 5-87 Fields for Register: UHS2_PHY_SET_R (Continued)

Memory
Bits Name Access Description

19:16 N_LSS_SYN R/W Host N_LSS_SYN

These bits are set to the largest value of N_LSS_SYN
capabilities among the Host Controller and the connected
devices.
■ 0x0 : 4x16 LSS
■ 0x1 : 4x1 LSS
■ 0x2 : 4x2 LSS
■ .......
■ .......
■ .......
■ 0xF : 4x15 LSS
Value After Reset: 0x0
Exists: Always

15 HBNATE_EN R/W Hibernate Enable

This bit is set if all devices support Hibernate mode after
checking the card capabilities of the Hibernate mode. This bit
determines whether Host remains in Dormant state or goes
to Hibernate state. In Hibernate mode, VDD1 Power of the
card can be cut off.
Note: Hibernate functionality will be supported in a future
release of DWC_mshc.
Values:
■ 0x0 (DISABLED): Hibernate Disabled
■ 0x1 (ENABLED): Hibernate Enabled
Value After Reset: 0x0
Exists: Always

14:8 RSVD_14_8 R These bits (RSVD_14_8) of the UHS2_PHY_SET_R register

are reserved bits. They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-87 Fields for Register: UHS2_PHY_SET_R (Continued)

Memory
Bits Name Access Description

7:6 SPD_RANGE R/W Speed Range

These bits select the PLL multiplier. Change of PLL Multiplier
is not effective immediately and is applied after exiting from
Dormant State.
Values:
■ 0x0 (RANGE_A): Range A (default)
■ 0x1 (RANGE_B): Range B
■ 0x2 (RSVD1): Reserved
■ 0x3 (RSVD2): Reserved
Value After Reset: 0x0
Exists: Always

5:0 RSVD_5_0 R These bits (RSVD_5_0) of the UHS2_PHY_SET_R register

are reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

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5.2.3 UHS2_LNK_TRAN_SET_1_R
■ Name: UHS-II LINK/TRAN Setting register
■ Description: This register is used to configure LINK/TRAN settings of UHS-II. LINK/TRAN
settings register is segregated into two 32-bit registers UHS2_LNK_TRAN_SET_1_R and
UHS2_LNK_TRAN_SET_2_R. This register UHS2_LNK_TRAN_SET_1_R represents lower 32 bits.
This register is applicable for UHS-II mode only.
■ Size: 32 bits
■ Offset: P_UHS_II_SETTINGS_R[11:0] + 0x8
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

RSVD_31_18 31:18
17:16
15:8
7:0
RTRY_CNT

RSVD_7_0
N_FCU

Table 5-88 Fields for Register: UHS2_LNK_TRAN_SET_1_R

Memory
Bits Name Access Description

31:18 RSVD_31_18 R These bits (RSVD_31_18) of the

UHS2_LNK_TRAN_SET_1_R register are reserved. They
always return 0.
Value After Reset: 0x0
Exists: Always

17:16 RTRY_CNT R/W Retry Count

DATA Burst retry count is set to this field.
Values:
■ 0x0 (DISABLED): Retry Disabled
■ 0x1 (ONE): 1 time
■ 0x2 (TWO): 2 times
■ 0x3 (THREE): 3 times
Value After Reset: 0x0
Exists: Always

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Table 5-88 Fields for Register: UHS2_LNK_TRAN_SET_1_R (Continued)

Memory
Bits Name Access Description

15:8 N_FCU R/W Host N_FCU

The Host Driver sets the number of blocks in the Data Burst
(Flow Control) to this field. The value is smaller than or equal
to N_FCU capabilities among the Host Controller and
connected devices. Setting 1 to 4 blocks is recommended,
considering the buffer size.
■ 0x00: 256 Blocks
■ 0x01: 1 Block
■ 0x02: 2 Blocks
■ 0x03: 3 Blocks
■ ........
■ ........
■ ........
■ 0xFF: 255 Blocks

Note: The N_FCU capability of the Host Controller is

determined based on the packet buffer depth and maximum
block size supported. If smaller block size is used, the Host
driver can still program higher value of N_FCU setting
(compared to N_FCU capability of host controller) as long as
the device supports this higher N_FCU settings and following
relation is satisfied in Host controller.
N_FCU <= DWC_MSHC_PKT_BUFFER_DEPTH /
(2*((Desired block size) / (DWC_MSHC_MBIU_DW/8))
where,
DWC_MSHC_PKT_BUFFER_DEPTH - Packet buffer depth
DWC_MSHC_MBIU_DW - AXI data width
Desired block size - Size of data packet for data transfer
Value After Reset: 0x0
Exists: Always

7:0 RSVD_7_0 R These bits (RSVD_7_0) of the

UHS2_LNK_TRAN_SET_1_R register are reserved. They
always return 0.
Value After Reset: 0x0
Exists: Always

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5.2.4 UHS2_LNK_TRAN_SET_2_R
■ Name: UHS-II LINK/TRAN Setting 2 register
■ Description: This register is used to configure LINK/TRAN settings of UHS-II. LINK/TRAN
settings register is segregated into two 32-bit registers, namely UHS2_LNK_TRAN_SET_1_R and
UHS2_LNK_TRAN_SET_2_R. This register UHS2_LNK_TRAN_SET_2_R represents upper 32 bits.
This register is applicable for UHS-II mode only.
■ Size: 32 bits
■ Offset: P_UHS_II_SETTINGS_R[11:0] + 0xc
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

31:8
N_DATA_GAP 7:0
RSVD_31_8

Table 5-89 Fields for Register: UHS2_LNK_TRAN_SET_2_R

Memory
Bits Name Access Description

31:8 RSVD_31_8 R These bits of the UHS2_LNK_TRAN_SET_2_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

7:0 N_DATA_GAP R/W Host N_DATA_GAP

These bits set the largest value of N_DATA_GAP capabilities
among the Host Controller and connected devices.
■ 0x00: No Gap
■ 0x01: 1 LSS
■ 0x02: 2 LSS
■ 0x03: 3 LSS
■ .......
■ .......
■ .......
■ 0xFF: 255 LSS
Value After Reset: 0x0
Exists: Always

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5.3 DWC_mshc_map/DWC_mshc_UHS_II_capability_block Registers

This register block defines UHS-II related capability registers. Follow the link for the register to see a
detailed description of the register.

Table 5-90 Registers for Address Block: DWC_mshc_map/DWC_mshc_UHS_II_capability_block

Register Offset Description

UHS2_GEN_CAP_R on page 435 P_UHS_I UHS2 General Capabilities register

I_HOST_
CAPAB[1
1:0]

UHS2_PHY_CAP_R on page 439 P_UHS_I UHS2 PHY Capabilities register

I_HOST_
CAPAB[1
1:0] + 0x4

UHS2_LNK_TRAN_CAP_1_R on P_UHS_I UHS2 Link Tran Capabilities register (0 to 31)

page 441 I_HOST_
CAPAB[1
1:0] + 0x8

UHS2_LNK_TRAN_CAP_2_R on P_UHS_I UHS2 Link Tran Capabilities register (32 to 63)

page 444 I_HOST_
CAPAB[1
1:0] + 0xc

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5.3.1 UHS2_GEN_CAP_R
■ Name: UHS2 General Capabilities register
■ Description: This register reflects the General capabilities of UHS-II based on configuration. This
register is applicable for UHS-II mode only.
■ Size: 32 bits
■ Offset: P_UHS_II_HOST_CAPAB[11:0]
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

31:24
23:22
21:18
RMV_EMBEDDED 17:16

13:8
7:4
3:0
15
14
RSVD_31_24

BOOT_LOAD
BUS_TOPO

NUM_LANE
NUM_DEV

ADDR64

GAP
DAP
Table 5-91 Fields for Register: UHS2_GEN_CAP_R

Memory
Bits Name Access Description

31:24 RSVD_31_24 R These bits of the UHS2_GEN_CAP_R register are reserved.

They always return 0.
Value After Reset: 0x0
Exists: Always

23:22 BUS_TOPO R Bus Topology

This field indicates one of the bus topologies configured by a
Host System. This configuration is done by using parameter
DWC_MSHC_UHS2_BUS_TOPOLOGY.
Values:
■ 0x0 (P2P): P2P Connection
■ 0x1 (RING): Ring Connection
■ 0x2 (HUB): HUB Connection
■ 0x3 (HUB_IN_RING): HUB is connected in Ring
Value After Reset: DWC_MSHC_UHS2_BUS_TOPOLOGY
Exists: Always

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Table 5-91 Fields for Register: UHS2_GEN_CAP_R (Continued)

Memory
Bits Name Access Description

21:18 NUM_DEV R Number of devices supported

This field indicates the maximum number of devices
supported by the Host Controller.
■ 0x0: Not used
■ 0x1: 1 Device
■ 0x2: 2 Devices
■ .......
■ .......
■ .......
■ 0xF: 15 Devices
Value After Reset: DWC_MSHC_UHS2_NUM_DEVICES
Exists: Always

17:16 RMV_EMBEDDED R Removable/ Embedded

This field indicates device type configured by a Host System.
Values:
■ 0x0 (RMV_CARD): Removable card
■ 0x1 (EMB_CARD): Embedded Devices
■ 0x2 (RMV_EMB_CARD): Embedded Devices and
Removable card
■ 0x3 (RSVD): Reserved
Value After Reset:
DWC_MSHC_UHS2_EMBEDDED_TYPE
Exists: Always

15 BOOT_LOAD R Boot Code Loading

This field indicates whether the Host Controller tries to boot
the system in the UHS-II mode. If this bit is set to 1, the
Synchronization for Boot Code Loading (BSYN) Link Symbol
Set (LSS) is sent during the PHY Initialization.
Values:
■ 0x1 (TRUE): Execute Boot Code Loading
■ 0x0 (FALSE): No Boot Code Loading
Value After Reset:
DWC_MSHC_UHS2_BOOTCODE_LOAD
Exists: Always

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Table 5-91 Fields for Register: UHS2_GEN_CAP_R (Continued)

Memory
Bits Name Access Description

14 ADDR64 R 64-bit Addressing

This field indicates support of 64-bit addressing by the Host
Controller.
Values:
■ 0x1 (TRUE): 32-bit and 64-bit Addressing is supported
■ 0x0 (FALSE): 32-bit Addressing is supported
Value After Reset: DWC_MSHC_UHS2_64BIT_ADDR
Exists: Always

13:8 NUM_LANE R Number of Lanes and Functionalities

This field indicates support for lanes by the Host Controller.
The value 1 indicates the support while 0 means, it is not
supported.
■ D08: 2L-HD
■ D09: 2D1U-FD
■ D10: 1D2U-FD
■ D11: 2D2U-FD
■ D12: Reserved
■ D13: Reserved
Value After Reset:
=::DWC_mshc::mshc_uhs2_num_lane_reset_val
Exists: Always

7:4 GAP R GAP (Group Allocation Power)

This field indicates the maximum capability of host power
supply for a group configured by a Host System. This field is
used to set the argument of the DEVICE_INIT CCMD. This
configuration is done by using the DWC_MSHC_UHS2_GAP
parameter.
■ 0x0: Not used
■ 0x1: 360 mW
■ 0x2: 720 mW
■ ......
■ ......
■ ......
■ 0xF: 360x15 mW
Value After Reset: DWC_MSHC_UHS2_GAP
Exists: Always

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Table 5-91 Fields for Register: UHS2_GEN_CAP_R (Continued)

Memory
Bits Name Access Description

3:0 DAP R DAP (Device Allocation Power)

This field indicates the maximum capability of host power
supply for a device configured by a Host System. This field is
used to set the argument of the DEVICE_INIT CCMD. This
configuration is done by using the DWC_MSHC_UHS2_DAP
parameter.
■ 0x0: 360 mW (Default)
■ 0x1: 360 mW
■ 0x2: 720 mW
■ ......
■ ......
■ ......
■ 0xF: 360x15 mW
Value After Reset: DWC_MSHC_UHS2_DAP
Exists: Always

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5.3.2 UHS2_PHY_CAP_R
■ Name: UHS2 PHY Capabilities register
■ Description: This register reflects the PHY capabilities of UHS-II based on the configuration. This
register is applicable for UHS-II mode only.
■ Size: 32 bits
■ Offset: P_UHS_II_HOST_CAPAB[11:0] + 0x4
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

RSVD_31_24 31:24
23:20
19:16
15:8
SPD_RANGE 7:6
5:0
N_LSS_SYN
RSVD_15_8
N_LSS_DIR

PHY_REV

Table 5-92 Fields for Register: UHS2_PHY_CAP_R

Memory
Bits Name Access Description

31:24 RSVD_31_24 R These bits of the UHS2_PHY_CAP_R register are reserved.

They always return 0.
Value After Reset: 0x0
Exists: Always

23:20 N_LSS_DIR R Host N_LSS_DIR

This field indicates the minimum N_LSS_DIR required by the
Host Controller. This is configured by using the
DWC_MSHC_PHY_N_LSS_DIR parameter.
■ 0x0: 8x16 LSS
■ 0x1: 8x1 LSS
■ 0x2: 8x2 LSS
■ ......
■ ......
■ ......
■ 0xF: 8x15 LSS
Value After Reset: DWC_MSHC_PHY_N_LSS_DIR
Exists: Always

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Table 5-92 Fields for Register: UHS2_PHY_CAP_R (Continued)

Memory
Bits Name Access Description

19:16 N_LSS_SYN R Host N_LSS_SYN

This field indicates the minimum N_LSS_SYN required by
the Host Controller. This is configured by using the
DWC_MSHC_PHY_N_LSS_SYN parameter.
■ 0x0: 4x16 LSS
■ 0x1: 4x1 LSS
■ 0x2: 4x2 LSS
■ .......
■ .......
■ .......
■ 0xF: 4x15 LSS
Value After Reset: DWC_MSHC_PHY_N_LSS_SYN
Exists: Always

15:8 RSVD_15_8 R These bits of the UHS2_PHY_CAP_R register are reserved

bits. They always return 0.
Value After Reset: 0x0
Exists: Always

7:6 SPD_RANGE R Speed Range

This field indicates supported Speed Range by the Host
Controller. This is configured using the
DWC_MSHC_PHY_SPD_RANGE parameter.
Values:
■ 0x0 (RANGE_A): Range A (default)
■ 0x1 (RANGE_B): Range A and Range B
■ 0x2 (RSVD1): Reserved
■ 0x3 (RSVD2): Reserved
Value After Reset: DWC_MSHC_PHY_SPD_RANGE
Exists: Always

5:0 PHY_REV R PHY Revision

These bits indicate the supported PHY Revision number.
■ 0x0 : First Revision
■ others : Reserved
Value After Reset: DWC_MSHC_PHY_REV
Exists: Always

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5.3.3 UHS2_LNK_TRAN_CAP_1_R
■ Name: UHS2 Link Tran Capabilities register (0 to 31)
■ Description: This register reflects LINK/TRAN capabilities of UHS-II based on configuration.
LINK/TRAN capabilities register is segregated into two 32-bit registers
UHS2_LNK_TRAN_SET_1_R and UHS2_LNK_TRAN_SET_2_R. This register
UHS2_LNK_TRAN_SET_1_R represents lower 32 bits. This register is applicable for UHS-II mode
only.
■ Size: 32 bits
■ Offset: P_UHS_II_HOST_CAPAB[11:0] + 0x8
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

MAX_BLK_LEN 31:20

18:16
15:8
7:6
5:0
19
DEV_TYPE

RSVD_7_6
LNK_REV
RSVD_19

N_FCU

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Table 5-93 Fields for Register: UHS2_LNK_TRAN_CAP_1_R

Memory
Bits Name Access Description

31:20 MAX_BLK_LEN R Host Maximum Block Length

These bits indicate the maximum block length supported by
the Host Controller for UHS-II mode.
■ 0x000: Not used
■ 0x001: 1 byte
■ 0x002: 2 bytes
■ .......
■ .......
■ .......
■ 0x200: 512 bytes
■ .......
■ .......
■ .......
■ 0x800: 2048 bytes
■ 0x801-0xFFF: Not used
Value After Reset: DWC_MSHC_LINK_MAX_BLK_SIZE
Exists: Always

19 RSVD_19 R This bit of the UHS2_LINK_TRAN_CAP_1_R register is

reserved. It always returns 0.
Value After Reset: 0x0
Exists: Always

18:16 DEV_TYPE R Host Device Type

This field is fixed to 0h.
0x0: Host Controller
Others: Not Used
Value After Reset: DWC_MSHC_LINK_DEVICE_TYPE
Exists: Always

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Table 5-93 Fields for Register: UHS2_LNK_TRAN_CAP_1_R (Continued)

Memory
Bits Name Access Description

15:8 N_FCU R Host N_FCU

These bits indicate the maximum number of blocks
supported in a flow control unit by the Host Controller. This
value is determined by the supported packet buffer depth
(DWC_MSHC_PKT_BUFFER_DEPTH), the AXI data width
(DWC_MSHC_MBIU_DW) and the maximum block size
(DWC_MSHC_LINK_MAX_BLK_SIZE).
■ 0x00: 256 Blocks
■ 0x01: 1 Block
■ 0x02: 2 Blocks
■ .......
■ .......
■ .......
■ 0xFF: 255 Blocks

Note: The value of this field is calculated by following

formula:
DWC_MSHC_PKT_BUFFER_DEPTH /
(2*(DWC_MSHC_LINK_MAX_BLK_SIZE /
(DWC_MSHC_MBIU_DW/8)))
Value After Reset: DWC_MSHC_LINK_N_FCU
Exists: Always

7:6 RSVD_7_6 R These bits of the UHS2_LINK_TRAN_CAP_1_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

5:0 LNK_REV R Link Revision

This field indicates the LINK Revision number.
■ 0x0: First revision
■ others: Reserved
Value After Reset: DWC_MSHC_LINK_REV
Exists: Always

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5.3.4 UHS2_LNK_TRAN_CAP_2_R
■ Name: UHS2 Link Tran Capabilities register (32 to 63)
■ Description: This register reflects the LINK/TRAN capabilities of UHS-II based on the configuration.
The LINK/TRAN capabilities register is segregated into two 32-bit registers, namely
UHS2_LNK_TRAN_SET_1_R and UHS2_LNK_TRAN_SET_2_R. The UHS2_LNK_TRAN_SET_2_R
register represents the upper 32 bits. This register is applicable for UHS-II mode only.
■ Size: 32 bits
■ Offset: P_UHS_II_HOST_CAPAB[11:0] + 0xc
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

31:8
N_DATA_GAP 7:0
RSVD_31_8

Table 5-94 Fields for Register: UHS2_LNK_TRAN_CAP_2_R

Memory
Bits Name Access Description

31:8 RSVD_31_8 R These bits of the UHS2_LNK_TRAN_CAP_2_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

7:0 N_DATA_GAP R Host N_DATA_GAP

These bits indicate the minimum number of data gap (DIDL)
supported by the Host Controller. This is configured by using
the DWC_MSHC_LINK_N_DATA_GAP parameter.
■ 0x00 : No Gap
■ 0x01 : 1 LSS
■ 0x02 : 2 LSS
■ .......
■ .......
■ .......
■ 0xFF : 255 LSS
Value After Reset: DWC_MSHC_LINK_N_DATA_GAP
Exists: Always

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5.4 DWC_mshc_map/DWC_mshc_UHS_II_test_block Registers

This register block defines UHS-II test related registers. Follow the link for the register to see a detailed
description of the register.

Table 5-95 Registers for Address Block: DWC_mshc_map/DWC_mshc_UHS_II_test_block

Register Offset Description

FORCE_UHS_II_ERR_INTR_STATUS_R P_UHS_I Force Event for UHS-II Error Interrupt Status Register
on page 446 I_TEST[1
1:0]

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5.4.1 FORCE_UHS_II_ERR_INTR_STATUS_R
■ Name: Force Event for UHS-II Error Interrupt Status Register
■ Description: This register is used to force the Host Controller to set Error Interrupt Status register.
This register is applicable for UHS-II mode only.
■ Size: 32 bits
■ Offset: P_UHS_II_TEST[11:0]
■ Exists: (DWC_MSHC_UHS2_SUPPORT==1)

26:18

14:9
VENDOR_SPECIFIC_ERR4 31
VENDOR_SPECIFIC_ERR3 30
VENDOR_SPECIFIC_ERR2 29
VENDOR_SPECIFIC_ERR1 28
VENDOR_SPECIFIC_ERR0 27

17
16
15

8
7
6
5
4
3
2
1
0
UNRECOVERABLE_ERR
TIMEOUT_DEADLOCK
TIMEOUT_CMD_RES
RESERVED_26_18

RETRY_EXPIRED
RESERVED_14_9

FRAMING_ERR

RES_PKT_ERR
HEADER_ERR
RESERVED_6
AMDA_ERR

EBSY_ERR

CRC_ERR
TID_ERR

Table 5-96 Fields for Register: FORCE_UHS_II_ERR_INTR_STATUS_R

Memory
Bits Name Access Description

31 VENDOR_SPECIFIC_ERR4 W This bit (VENDOR_SPECIFIC_ERR4) of the

FORCE_UHS_II_ERR_INTR_STATUS_R register is
reserved. It always returns 0.
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Vendor Specific Error status is set
Value After Reset: 0x0
Exists: Always

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Table 5-96 Fields for Register: FORCE_UHS_II_ERR_INTR_STATUS_R (Continued)

Memory
Bits Name Access Description

30 VENDOR_SPECIFIC_ERR3 W This bit (VENDOR_SPECIFIC_ERR3) of the

FORCE_UHS_II_ERR_INTR_STATUS_R register is
reserved. It always returns 0.
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Vendor Specific Error status is set
Value After Reset: 0x0
Exists: Always

29 VENDOR_SPECIFIC_ERR2 W This bit (VENDOR_SPECIFIC_ERR2) of the

FORCE_UHS_II_ERR_INTR_STATUS_R register is
reserved. It always returns 0.
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Vendor Specific Error status is set
Value After Reset: 0x0
Exists: Always

28 VENDOR_SPECIFIC_ERR1 W This bit (VENDOR_SPECIFIC_ERR1) of the

FORCE_UHS_II_ERR_INTR_STATUS_R register is
reserved. It always returns 0.
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Vendor Specific Error status is set
Value After Reset: 0x0
Exists: Always

27 VENDOR_SPECIFIC_ERR0 W This bit (VENDOR_SPECIFIC_ERR0) of the

FORCE_UHS_II_ERR_INTR_STATUS_R register is
reserved. It always returns 0.
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Vendor Specific Error status is set
Value After Reset: 0x0
Exists: Always

26:18 RESERVED_26_18 R These bits (RESERVED_26_18) of the

FORCE_UHS_II_ERR_INTR_STATUS_R register are
reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-96 Fields for Register: FORCE_UHS_II_ERR_INTR_STATUS_R (Continued)

Memory
Bits Name Access Description

17 TIMEOUT_DEADLOCK W Force Event for Timeout for Deadlock

Thsi bit forces the Host Controller to set Timeout for
Deadlock in the UHS-II Error Interrupt Status register.
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Timeout for Deadlock Error status is set
Value After Reset: 0x0
Exists: Always

16 TIMEOUT_CMD_RES W Force Event for Timeout for CMD_RES

This bit forces the Host Controller to set Timeout for
CMD_RES in the UHS-II Error Interrupt Status register.
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Timeout for CMD_RES Error status is set
Value After Reset: 0x0
Exists: Always

15 AMDA_ERR W Force Event for ADMA Error

This bit forces the Host Controller to set ADMA Error in the
UHS-II Error Interrupt Status register.
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): ADMA Error status is set
Value After Reset: 0x0
Exists: Always

14:9 RESERVED_14_9 R These bits (RESERVED_14_9) of the

FORCE_UHS_II_ERR_INTR_STATUS_R register are
reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

8 EBSY_ERR W Force Event for EBSY Error

This bit forces the Host Controller to set EBSY Error in the
UHS-II Error Interrupt Status register.
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): EBSY Error status is set
Value After Reset: 0x0
Exists: Always

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Table 5-96 Fields for Register: FORCE_UHS_II_ERR_INTR_STATUS_R (Continued)

Memory
Bits Name Access Description

7 UNRECOVERABLE_ERR W Force Event for Unrecoverable Error

This bit forces the Host Controller to set Unrecoverable Error
in the UHS-II Error Interrupt Status register.
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Unrecoverable Error status is set
Value After Reset: 0x0
Exists: Always

6 RESERVED_6 R This bit (RESERVED_6) of the

FORCE_UHS_II_ERR_INTR_STATUS_R register is
reserved. It always returns 0.
Value After Reset: 0x0
Exists: Always

5 TID_ERR W Force Event for TID Error

This bit forces the Host Controller to set TID Error in the
UHS-II Error Interrupt Status register.
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): TID Error status is set
Value After Reset: 0x0
Exists: Always

4 FRAMING_ERR W Force Event for Framing Error

This bit forces the Host Controller to set Framing Error in the
UHS-II Error Interrupt Status register.
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Framing Error status is set
Value After Reset: 0x0
Exists: Always

3 CRC_ERR W Force Event for CRC Error

Thsi bit forces the Host Controller to set CRC Error in the
UHS-II Error Interrupt Status register.
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): CRC Error status is set
Value After Reset: 0x0
Exists: Always

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Table 5-96 Fields for Register: FORCE_UHS_II_ERR_INTR_STATUS_R (Continued)

Memory
Bits Name Access Description

2 RETRY_EXPIRED W Force Event for Retry Expired

This bit forces the Host Controller to set Retry Expired in the
UHS-II Error Interrupt Status register.
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Retry expired Error status is set
Value After Reset: 0x0
Exists: Always

1 RES_PKT_ERR W Force Event for RES Packet Error

This bit forces the Host Controller to set RES Packet Error in
the UHS-II Error Interrupt Status register.
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): RES Packet Error status is set
Value After Reset: 0x0
Exists: Always

0 HEADER_ERR W Force Event for Header Error

This bit forces the Host Controller to set Header Error in the
UHS-II Error Interrupt Status register.
Values:
■ 0x0 (FALSE): Not Affected
■ 0x1 (TRUE): Header Error status is set
Value After Reset: 0x0
Exists: Always

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5.5 DWC_mshc_map/DWC_mshc_embedded_control_block Registers

This register block defines embedded control registers. Follow the link for the register to see a detailed
description of the register.

Table 5-97 Registers for Address Block: DWC_mshc_map/DWC_mshc_embedded_control_block

Register Offset Description

EMBEDDED_CTRL_R on page 452 P_EMBE Embedded Control register

DDED_C
NTRL[11:
0]

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5.5.1 EMBEDDED_CTRL_R
■ Name: Embedded Control register
■ Description: This register controls the embedded device. When the Host Controller is connected to a
removable device, this register is not used.
■ Size: 32 bits
■ Offset: P_EMBEDDED_CNTRL[11:0]
■ Exists: Always

BACK_END_PWR_CTRL 30:24

22:20

18:16

14:8
7:6
5:4

2:0
31

23

19

15

3
BUS_WIDTH_PRESET

NUM_CLK_PIN
NUM_INT_PIN
CLK_PIN_SEL
INT_PIN_SEL

RSVD_7_6
RSVD_31

RSVD_23

RSVD_19

RSVD_15

RSVD_3

Table 5-98 Fields for Register: EMBEDDED_CTRL_R

Memory
Bits Name Access Description

31 RSVD_31 R This bit (RSVD_31) of the EMBEDDED_CTRL_R register is

reserved. It always returns 0.
Value After Reset: 0x0
Exists: Always

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Table 5-98 Fields for Register: EMBEDDED_CTRL_R (Continued)

Memory
Bits Name Access Description

30:24 BACK_END_PWR_CTRL R/W Back-End Power Control (SD Mode)

Each bit of this field controls back-end power supply for an
embedded device.
■ 0 : Back-End Power is off
■ 1 : Back-End Power is supplied

D24 : Back-End Power for Device 1

D25 : Back-End Power for Device 2
D26 : Back-End Power for Device 3
D27 : Back-End Power for Device 4
D28 : Back-End Power for Device 5
D29 : Back-End Power for Device 6
D30 : Back-End Power for Device 7
Value After Reset: 0x0
Exists: Always

23 RSVD_23 R This bit (RSVD_23) of the EMBEDDED_CTRL_R register is

reserved. It always returns 0.
Value After Reset: 0x0
Exists: Always

22:20 INT_PIN_SEL R/W Interrupt Pin Select

These bits enable the interrupt pin inputs.
■ 000 : Interrupts (INT_A,INT_B,INT_C) are disabled
■ xx1 : INT_A is enabled
■ x1x : INT_B is enabled
■ 1xx : INT_C is enabled
Value After Reset: 0x0
Exists: Always

19 RSVD_19 R This bit (RSVD_19) of the EMBEDDED_CTRL_R register is

reserved. It always returns 0.
Value After Reset: 0x0
Exists: Always

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Table 5-98 Fields for Register: EMBEDDED_CTRL_R (Continued)

Memory
Bits Name Access Description

18:16 CLK_PIN_SEL R/W Clock Pin Select (SD Mode)

This bit is selected by one of clock pin outputs.
■ 0x0 : Clock pins are disabled
■ 0x1 : CLK[1] is selected
■ 0x2 : CLK[2] is selected
■ ..
■ ..
■ ..
■ 0x7 : CLK[7] is selected
Value After Reset: 0x0
Exists: Always

15 RSVD_15 R This bit (RSVD_15) of the EMBEDDED_CTRL_R register is

reserved. It always returns 0.
Value After Reset: 0x0
Exists: Always

14:8 BUS_WIDTH_PRESET R Bus Width Preset (SD Mode)

Each bit of this field specifies the bus width for each
embedded device. The shared bus supports mixing of 4-bit
and 8-bit bus width devices.
■ D08 : Bus Width Preset for Device 1
■ D09 : Bus Width Preset for Device 2
■ D10 : Bus Width Preset for Device 3
■ D11 : Bus Width Preset for Device 4
■ D12 : Bus Width Preset for Device 5
■ D13 : Bus Width Preset for Device 6
■ D14 : Bus Width Preset for Device 7

Function of each bit is defined as follows:

■ 0 : 4-bit bus width mode
■ 1 : 8-bit bus width mode
Value After Reset: 0x0
Exists: Always

7:6 RSVD_7_6 R These bits (RSVD_7_6) of the EMBEDDED_CTRL_R

register are reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-98 Fields for Register: EMBEDDED_CTRL_R (Continued)

Memory
Bits Name Access Description

5:4 NUM_INT_PIN R Number of Interrupt Input Pins

This field indicates support of interrupt input pins for an
embedded system.
Value After Reset: 0x0
Exists: Always

3 RSVD_3 R This bit (RSVD_3) of the EMBEDDED_CTRL_R register is

reserved. It always returns 0.
Value After Reset: 0x0
Exists: Always

2:0 NUM_CLK_PIN R Number of Clock Pins (SD Mode)

This field indicates support of clock pins to select one of
devices for shared bus system. Up to 7 clock pins can be
supported.
■ 0x0 : Shared bus is not supported
■ 0x1 : 1 SDCLK is supported
■ 0x2 - 2 SDCLK is supported
■ ..
■ ..
■ ..
■ 0x7 : 7 SDCLK is supported
Value After Reset: 0x0
Exists: Always

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5.6 DWC_mshc_map/DWC_mshc_vendor2_block Registers

This register block defines Vendor-2 related registers. Follow the link for the register to see a detailed
description of the register.

Table 5-99 Registers for Address Block: DWC_mshc_map/DWC_mshc_vendor2_block

Register Offset Description

CQVER on page 459 P_VEND Command Queuing Version register

OR2_SP
ECIFIC_
AREA

CQCAP on page 460 P_VEND Command Queuing Capabilities register

OR2_SP
ECIFIC_
AREA +
0x4

CQCFG on page 462 P_VEND Command Queuing Configuration register

OR2_SP
ECIFIC_
AREA +
0x8

CQCTL on page 465 P_VEND Command Queuing Control register

OR2_SP
ECIFIC_
AREA +
0xc

CQIS on page 467 P_VEND Command Queuing Interrupt Status register

OR2_SP
ECIFIC_
AREA +
0x10

CQISE on page 471 P_VEND Command Queuing Interrupt Status Enable register
OR2_SP
ECIFIC_
AREA +
0x14

CQISGE on page 473 P_VEND Command Queuing Interrupt signal enable register
OR2_SP
ECIFIC_
AREA +
0x18

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Table 5-99 Registers for Address Block: DWC_mshc_map/DWC_mshc_vendor2_block (Continued)

Register Offset Description

CQIC on page 476 P_VEND Command Queuing Interrupt Coalescing register

OR2_SP
ECIFIC_
AREA +
0x1c

CQTDLBA on page 480 P_VEND Command Queuing Task Descriptor List Base Address
OR2_SP register
ECIFIC_
AREA +
0x20

CQTDLBAU on page 481 P_VEND Command Queuing Task Descriptor List Base Address
OR2_SP Upper register
ECIFIC_
AREA +
0x24

CQTDBR on page 482 P_VEND Command Queuing DoorBell register

OR2_SP
ECIFIC_
AREA +
0x28

CQTCN on page 484 P_VEND Command Queuing TaskClear Notification register

OR2_SP
ECIFIC_
AREA +
0x2c

CQDQS on page 485 P_VEND Device queue status register

OR2_SP
ECIFIC_
AREA +
0x30

CQDPT on page 486 P_VEND Device pending tasks register

OR2_SP
ECIFIC_
AREA +
0x34

CQTCLR on page 487 P_VEND Command Queuing DoorBell register

OR2_SP
ECIFIC_
AREA +
0x38

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Table 5-99 Registers for Address Block: DWC_mshc_map/DWC_mshc_vendor2_block (Continued)

Register Offset Description

CQSSC1 on page 488 P_VEND CQ Send Status Configuration 1 register

OR2_SP
ECIFIC_
AREA +
0x40

CQSSC2 on page 490 P_VEND CQ Send Status Configuration 2 register

OR2_SP
ECIFIC_
AREA +
0x44

CQCRDCT on page 491 P_VEND Command response for direct command register
OR2_SP
ECIFIC_
AREA +
0x48

CQRMEM on page 492 P_VEND Command response mode error mask register
OR2_SP
ECIFIC_
AREA +
0x50

CQTERRI on page 493 P_VEND CQ Task Error Information register

OR2_SP
ECIFIC_
AREA +
0x54

CQCRI on page 496 P_VEND CQ Command response index

OR2_SP
ECIFIC_
AREA +
0x58

CQCRA on page 497 P_VEND CQ Command response argument register

OR2_SP
ECIFIC_
AREA +
0x5c

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5.6.1 CQVER
■ Name: Command Queuing Version register
■ Description: This register provides information about the version of the eMMC Command Queueing
standard, which is implemented by the CQE in BCD format.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

EMMMC_VER_RSVD 31:12
EMMC_VER_MAJOR 11:8
7:4
EMMC_VER_SUFFIX 3:0
EMMC_VER_MINOR

Table 5-100 Fields for Register: CQVER

Memory
Bits Name Access Description

31:12 EMMMC_VER_RSVD R These bits of the CQVER register are reserved. They always
return 0.
Value After Reset: 0x0
Exists: Always

11:8 EMMC_VER_MAJOR R This bit indicates the eMMC major version (1st digit left of
decimal point) in BCD format.
Value After Reset: 0x5
Exists: Always

7:4 EMMC_VER_MINOR R This bit indicates the eMMC minor version (1st digit right of
decimal point) in BCD format.
Value After Reset: 0x1
Exists: Always

3:0 EMMC_VER_SUFFIX R This bit indicates the eMMC version suffix (2nd digit right of
decimal point) in BCD format.
Value After Reset: 0x0
Exists: Always

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5.6.2 CQCAP
■ Name: Command Queuing Capabilities register
■ Description: This register indicates the capabilities of the command queuing engine.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x4
■ Exists: DWC_MSHC_SD_EMMC_SUPPORT==1

31:29

27:16
15:12
11:10
9:0
CRYPTO_SUPPORT 28
CQCCAP_RSVD3

CQCCAP_RSVD2

CQCCAP_RSVD1
ITCFMUL

ITCFVAL

Table 5-101 Fields for Register: CQCAP

Memory
Bits Name Access Description

31:29 CQCCAP_RSVD3 R These bits [31:29] of the CQCAP register are reserved. They
always return 0.
Value After Reset: 0x0
Exists: Always

28 CRYPTO_SUPPORT R Crypto Support

This bit indicates whether the Host Controller supports
cryptographic operations.
Values:
■ 0x0 (FALSE): Crypto not Supported
■ 0x1 (TRUE): Crypto Supported
Value After Reset: DWC_MSHC_CRYPTO_SUPPORT
Exists: Always

27:16 CQCCAP_RSVD2 R These bits [27:16] of the CQCAP register are reserved. They
always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-101 Fields for Register: CQCAP (Continued)

Memory
Bits Name Access Description

15:12 ITCFMUL R Internal Timer Clock Frequency Multiplier (ITCFMUL)

This field indicates the frequency of the clock used for
interrupt coalescing timer and for determining the SQS
polling period. See ITCFVAL definition for details. Values 0x5
to 0xF are reserved.
Values:
■ 0x0 (CLK_1KHz): 1KHz clock
■ 0x1 (CLK_10KHz): 10KHz clock
■ 0x2 (CLK_100KHz): 100KHz clock
■ 0x3 (CLK_1MHz): 1MHz clock
■ 0x4 (CLK_10MHz): 10MHz clock
Value After Reset: DWC_MSHC_CQE_TIMER_CLK_FMUL
Exists: Always

11:10 CQCCAP_RSVD1 R These bits of the CQCAP register are reserved. They always
return 0.
Value After Reset: 0x0
Exists: Always

9:0 ITCFVAL R Internal Timer Clock Frequency Value (ITCFVAL)

This field scales the frequency of the timer clock provided by
ITCFMUL. The Final clock frequency of actual timer clock is
calculated as ITCFVAL* ITCFMUL.
Value After Reset: DWC_MSHC_CQE_TIMER_CLK_FVAL
Exists: Always

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5.6.3 CQCFG
■ Name: Command Queuing Configuration register
■ Description: This register controls CQE behavior affecting the general operation of command
queuing engine.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x8
■ Exists: (DWC_MSHC_EMMC_CQE_EN==1) || (DWC_MSHC_CRYPTO_SUPPORT==1)

31:13

11:9

7:2
12

TASK_DESC_SIZE 8

CR_GENERAL_EN 1
0
CQCCFG_RSVD3

CQCCFG_RSVD2

CQCCFG_RSVD1
DCMD_EN

CQ_EN

Table 5-102 Fields for Register: CQCFG

Memory
Bits Name Access Description

31:13 CQCCFG_RSVD3 R These bits (CQCCFG_RSVD3) of the CQCFG register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

12 DCMD_EN R/W This bit indicates to the hardware whether the Task
Descriptor in slot #31 of the TDL is a data transfer descriptor
or a direct-command descriptor. CQE uses this bit when a
task is issued in slot #31, to determine how to decode the
Task Descriptor.
Values:
■ 0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot
#31 is a DCMD Task Descriptor
■ 0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot
#31 is a data Transfer Task Descriptor
Value After Reset: 0x0
Exists: (DWC_MSHC_EMMC_CQE_EN == 1)

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Table 5-102 Fields for Register: CQCFG (Continued)

Memory
Bits Name Access Description

11:9 CQCCFG_RSVD2 R These bits (CQCCFG_RSVD2) of the CQCFG register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

8 TASK_DESC_SIZE R/W Bit Value Description

This bit indicates the size of task descriptor used in host
memory. This bit can only be configured when Command
Queuing Enable bit is 0 (command queuing is disabled).
Values:
■ 0x1 (TASK_DESC_128b): Task descriptor size is 128 bits
■ 0x0 (TASK_DESC_64b): Task descriptor size is 64 bits
Value After Reset: 0x0
Exists: (DWC_MSHC_EMMC_CQE_EN == 1)

7:2 CQCCFG_RSVD1 R These bits (CQCCFG_RSVD1) of the CQCFG register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

1 CR_GENERAL_EN R/W Crypto General Enable

Enable/Disable bit for Crypto Engine. If cryptographic
operations are not supported, this status bit is reserved.
Values:
■ 0x1 (ENABLE): Enable cryptographic operations for
transactions where TD.CE=1 or CRNQP.CE=1
■ 0x0 (DISABLE): Disable cryptographic operations for all
transactions
Value After Reset: 0x0
Exists: (DWC_MSHC_CRYPTO_SUPPORT == 1)
Testable: restore

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Table 5-102 Fields for Register: CQCFG (Continued)

Memory
Bits Name Access Description

0 CQ_EN R/W Enable command queuing engine (CQE).

When CQE is disable, the software controls the eMMC bus
using the registers between the addresses 0x000 to 0x1FF.
Before the software writes to this bit, the software verifies
that the eMMC host controller is in idle state and there are no
ongoing commands or data transfers. When software wants
to exit command queuing mode, it clears all previous tasks (if
any) before setting this bit to 0.
Values:
■ 0x1 (CQE_ENABLE): Enable command queuing
■ 0x0 (CQE_DISABLE): Disable command queuing
Value After Reset: 0x0
Exists: (DWC_MSHC_EMMC_CQE_EN == 1)
Testable: restore

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5.6.4 CQCTL
■ Name: Command Queuing Control register
■ Description: This register controls CQE behavior affecting the general operation of command
queuing module or simultaneous operation of multiple tasks.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0xc
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

31:9

7:1
CLR_ALL_TASKS 8

0
CQCTL_RSVD2

CQCTL_RSVD1
HALT

Table 5-103 Fields for Register: CQCTL

Memory
Bits Name Access Description

31:9 CQCTL_RSVD2 R These bits (CQCTL_RSVD2) of the CQCTL register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

8 CLR_ALL_TASKS R/W Clear all tasks

This bit can only be written when the controller is halted. This
bit does not clear tasks in the device. The software has to
use the CMDQ_TASK_MGMT command to clear device's
queue.
Values:
■ 0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the
controller
■ 0x0 (NO_EFFECT): Programming 0 has no effect
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-103 Fields for Register: CQCTL (Continued)

Memory
Bits Name Access Description

7:1 CQCTL_RSVD1 R These bits (CQCTL_RSVD1) of the CQCTL register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

0 HALT R/W Halt request and resume

Values:
■ 0x1 (HALT_CQE): Software writes 1 to this bit when it
wants to acquire software control over the eMMC bus and
to disable CQE from issuing command on the bus.
For example, issuing a Discard Task command
(CMDQ_TASK_MGMT). When the software writes 1, CQE
completes the ongoing task (if any in progress). After the
task is completed and the CQE is in idle state, CQE does not
issue new commands and indicates to the software by
setting this bit to 1. The software can poll on this bit until it is
set to 1 and only then send commands on the eMMC bus.
■ 0x0 (RESUME_CQE): Software writes 0 to this bit to exit
from the halt state and resume CQE activity.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.6.5 CQIS
■ Name: Command Queuing Interrupt Status register
■ Description: This register indicates pending interrupts that require service. Each bit in this register is
asserted in response to a specific event, only if the respective bit is set in the CQISE register.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x10
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

CQIS_RSVD1 31:6
5
4
3
2
1
0
ICCE
GCE

RED

HAC
TCC
TCL

Table 5-104 Fields for Register: CQIS

Memory
Bits Name Access Description

31:6 CQIS_RSVD1 R These bits of the CQIS register are reserved. They always
return 0.
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-104 Fields for Register: CQIS (Continued)

Memory
Bits Name Access Description

5 ICCE R/W1C Invalid Crypto Configuration Error

If cryptographic operations is supported by host controller
(CQCAP.CS=1) and (CQCFG.GCE=1); and
encryption/decryption is enabled (TD.CE=1), this status bit is
asserted (if CQISE.ICCE_STE=1) if either of the below
conditions are met.
■ CRYPTOCFG disabled
(CRYPTOCFG_i_16[TD.CCI].CFGE_i=0) OR nonexistent
(TD.CCI>=CRCAP.CFGC)
■ Capability index in Configuration
(CRYPTOCFG_i_16[TD.CCI].CAPIDX_i ) is greater than
maximum number of capabilities supported (CAPIDX_i >
CRCAP.CC)
■ Data unit size in Configuration
(CRYPTOCFG_i_16[TD.CCI].DUSIZE_i) is not supported
by selected capability
(CRYPTOCAP_x[CAPIDX_i].SDUSB)

If cryptographic operations are not supported, this status bit

is reserved.
Values:
■ 0x1 (SET): ICCE interrupt is set
■ 0x0 (UNSET): ICCE interrupt is not set
Value After Reset: 0x0
Exists: (DWC_MSHC_CRYPTO_SUPPORT == 1)
Volatile: true

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Table 5-104 Fields for Register: CQIS (Continued)

Memory
Bits Name Access Description

4 GCE R/W1C General Crypto Error

If cryptographic operations is supported by host controller
(CQCAP.CS=1) and (CQCFG.GCE=1); and
encryption/decryption is enabled (TD.CE=1), this status bit is
asserted (if CQISE.GCE_STE=1) when the crypto hardware
encounters any of the following error in the processing of a
transaction.
■ Block size is not multiple of 16 bytes
■ Total transfer length (Block size * Block count) is not an
integral multiple of DUSize
■ Device data block transfer starting address is not aligned
to DUSize
■ CQE task descriptor data transfer length is not multiple of
16 bytes

If cryptographic operations are not supported, this status bit

is reserved.
Values:
■ 0x1 (SET): GCE interrupt is set
■ 0x0 (UNSET): GCE interrupt is not set
Value After Reset: 0x0
Exists: (DWC_MSHC_CRYPTO_SUPPORT == 1)
Volatile: true

3 TCL R/W1C Task cleared interrupt

This status bit is asserted (if CQISE.TCL_STE=1) when a
task clear operation is completed by CQE. The completed
task clear operation is either an individual task clear (by
writing CQTCLR) or clearing of all tasks (by writing CQCTL).
A value of 1 clears this status bit.
Values:
■ 0x1 (SET): TCL Interrupt is set
■ 0x0 (NOTSET): TCL Interrupt is not set
Value After Reset: 0x0
Exists: Always
Volatile: true

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Table 5-104 Fields for Register: CQIS (Continued)

Memory
Bits Name Access Description

2 RED R/W1C Response error detected interrupt

This status bit is asserted (if CQISE.RED_STE=1) when a
response is received with an error bit set in the device status
field. Configure the CQRMEM register to identify device
status bit fields that may trigger an interrupt and that are
masked. A value of 1 clears this status bit.
Values:
■ 0x1 (SET): RED Interrupt is set
■ 0x0 (NOTSET): RED Interrupt is not set
Value After Reset: 0x0
Exists: Always
Volatile: true

1 TCC R/W1C Task complete interrupt

This status bit is asserted (if CQISE.TCC_STE=1) when at
least one of the following conditions are met:
■ A task is completed and the INT bit is set in its Task
Descriptor
■ Interrupt caused by Interrupt Coalescing logic due to
timeout
■ Interrupt Coalescing logic reached the configured
threshold
A value of 1 clears this status bit
Values:
■ 0x1 (SET): TCC Interrupt is set
■ 0x0 (NOTSET): TCC Interrupt is not set
Value After Reset: 0x0
Exists: Always
Volatile: true

0 HAC R/W1C Halt complete interrupt

This status bit is asserted (only if CQISE.HAC_STE=1) when
halt bit in the CQCTL register transitions from 0 to 1
indicating that the host controller has completed its current
ongoing task and has entered halt state. A value of 1 clears
this status bit.
Values:
■ 0x1 (SET): HAC Interrupt is set
■ 0x0 (NOTSET): HAC Interrupt is not set
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.6.6 CQISE
■ Name: Command Queuing Interrupt Status Enable register
■ Description: This register enables and disables the reporting of the corresponding interrupt to host
software in the CQIS register. When a bit is set (1) and the corresponding interrupt condition is
active, then the bit in CQIS is asserted. Interrupt sources that are disabled (when '0') are not indicated
in the CQIS register. This register is bit-index matched to the CQIS register.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x14
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

CQISTE_RSVD1 31:6
5
4
3
2
1
0
ICCE_STE
GCE_STE

RED_STE

HAC_STE
TCC_STE
TCL_STE

Table 5-105 Fields for Register: CQISE

Memory
Bits Name Access Description

31:6 CQISTE_RSVD1 R These bits of the CQISE register are reserved. They always
return 0.
Value After Reset: 0x0
Exists: Always

5 ICCE_STE R/W Invalid Crypto Configuration Error interrupt status enable

Values:
■ 0x1 (INT_STS_ENABLE): CQIS.ICCE is set when its
interrupt condition is active
■ 0x0 (INT_STS_DISABLE): CQIS.ICCE is disabled
Value After Reset: 0x0
Exists: (DWC_MSHC_CRYPTO_SUPPORT == 1)

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Table 5-105 Fields for Register: CQISE (Continued)

Memory
Bits Name Access Description

4 GCE_STE R/W General Crypto Error interrupt status enable

Values:
■ 0x1 (INT_STS_ENABLE): CQIS.GCE is set when its
interrupt condition is active
■ 0x0 (INT_STS_DISABLE): CQIS.GCE is disabled
Value After Reset: 0x0
Exists: (DWC_MSHC_CRYPTO_SUPPORT == 1)

3 TCL_STE R/W Task cleared interrupt status enable

Values:
■ 0x1 (INT_STS_ENABLE): CQIS.TCL is set when its
interrupt condition is active
■ 0x0 (INT_STS_DISABLE): CQIS.TCL is disabled
Value After Reset: 0x0
Exists: Always

2 RED_STE R/W Response error detected interrupt status enable

Values:
■ 0x1 (INT_STS_ENABLE): CQIS.RED is set when its
interrupt condition is active
■ 0x0 (INT_STS_DISABLE): CQIS.RED is disabled
Value After Reset: 0x0
Exists: Always

1 TCC_STE R/W Task complete interrupt status enable

Values:
■ 0x1 (INT_STS_ENABLE): CQIS.TCC is set when its
interrupt condition is active
■ 0x0 (INT_STS_DISABLE): CQIS.TCC is disabled
Value After Reset: 0x0
Exists: Always

0 HAC_STE R/W Halt complete interrupt status enable

Values:
■ 0x1 (INT_STS_ENABLE): CQIS.HAC is set when its
interrupt condition is active
■ 0x0 (INT_STS_DISABLE): CQIS.HAC is disabled
Value After Reset: 0x0
Exists: Always

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5.6.7 CQISGE
■ Name: Command Queuing Interrupt signal enable register
■ Description: This register enables and disables the generation of interrupts to host software. When a
bit is set and the corresponding bit in CQIS is set, then an interrupt is generated. Interrupt sources
that are disabled are still indicated in the CQIS register. This register is bit-index matched to the CQIS
register.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x18
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

CQISGE_RSVD1 31:6
5
4
3
2
1
0
ICCE_SGE
GCE_SGE

RED_SGE

HAC_SGE
TCC_SGE
TCL_SGE

Table 5-106 Fields for Register: CQISGE

Memory
Bits Name Access Description

31:6 CQISGE_RSVD1 R These bits of the CQISGE register are reserved. They
always return 0.
Value After Reset: 0x0
Exists: Always

5 ICCE_SGE R/W Invalid Crypto Configuration Error interrupt signal enable

Values:
■ 0x1 (INT_SIG_ENABLE): CQIS.ICCE interrupt signal
generation is active
■ 0x0 (INT_SIG_DISABLE): CQIS.ICCE interrupt signal
generation is disabled
Value After Reset: 0x0
Exists: (DWC_MSHC_CRYPTO_SUPPORT == 1)

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Table 5-106 Fields for Register: CQISGE (Continued)

Memory
Bits Name Access Description

4 GCE_SGE R/W General Crypto Error interrupt signal enable

Values:
■ 0x1 (INT_SIG_ENABLE): CQIS.GCE interrupt signal
generation is active
■ 0x0 (INT_SIG_DISABLE): CQIS.GCE interrupt signal
generation is disabled
Value After Reset: 0x0
Exists: (DWC_MSHC_CRYPTO_SUPPORT == 1)

3 TCL_SGE R/W Task cleared interrupt signal enable

Values:
■ 0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal
generation is active
■ 0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal
generation is disabled
Value After Reset: 0x0
Exists: Always

2 RED_SGE R/W Response error detected interrupt signal enable

Values:
■ 0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal
generation is active
■ 0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal
generation is disabled
Value After Reset: 0x0
Exists: Always

1 TCC_SGE R/W Task complete interrupt signal enable

Values:
■ 0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal
generation is active
■ 0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal
generation is disabled
Value After Reset: 0x0
Exists: Always

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Table 5-106 Fields for Register: CQISGE (Continued)

Memory
Bits Name Access Description

0 HAC_SGE R/W Halt complete interrupt signal enable

Values:
■ 0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal
generation is active
■ 0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal
generation is disabled
Value After Reset: 0x0
Exists: Always

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5.6.8 CQIC
■ Name: Command Queuing Interrupt Coalescing register
■ Description: This register controls and configures interrupt coalescing feature.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x1c
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

30:21

19:17

14:13
12:8

6:0
31

20

16
15

TOUT_VAL_WEN 7
INTC_TH_WEN
CQIC_RSVD3

CQIC_RSVD2

CQIC_RSVD1
INTC_STAT

TOUT_VAL
INTC_RST
INTC_EN

INTC_TH

Table 5-107 Fields for Register: CQIC

Memory
Bits Name Access Description

31 INTC_EN R/W Interrupt Coalescing Enable Bit

Values:
■ 0x1 (ENABLE_INT_COALESCING): Interrupt coalescing
mechanism is active. Interrupts are counted and timed,
and coalesced interrupts are generated
■ 0x0 (DISABLE_INT_COALESCING): Interrupt coalescing
mechanism is disabled (Default).
Value After Reset: 0x0
Exists: Always

30:21 CQIC_RSVD3 R These bits (CQIC_RSVD3) of the CQIC register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-107 Fields for Register: CQIC (Continued)

Memory
Bits Name Access Description

20 INTC_STAT R Interrupt Coalescing Status Bit

This bit indicates to the software whether any tasks (with
INT=0) have completed and counted towards interrupt
coalescing (that is, this is set if and only if INTC counter > 0).
Values:
■ 0x1 (INTC_ATLEAST1_COMP): At least one INT0 task
completion has been counted (INTC counter > 0)
■ 0x0 (INTC_NO_TASK_COMP): INT0 Task completions
have not occurred since last counter reset (INTC counter
== 0)
Value After Reset: 0x0
Exists: Always

19:17 CQIC_RSVD2 R These bits (CQIC_RSVD2) of the CQIC register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

16 INTC_RST W Counter and Timer Reset

When host driver writes 1, the interrupt coalescing timer and
counter are reset.
Values:
■ 0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer
and counter are reset
■ 0x0 (NO_EFFECT): No Effect
Value After Reset: 0x0
Exists: Always

15 INTC_TH_WEN W Interrupt Coalescing Counter Threshold Write Enable

When software writes 1 to this bit, the value INTC_TH is
updated with the contents written on the same cycle.
Values:
■ 0x1 (WEN_SET): Sets INTC_TH_WEN
■ 0x0 (WEN_CLR): Clears INTC_TH_WEN
Value After Reset: 0x0
Exists: Always

14:13 CQIC_RSVD1 R These bits (CQIC_RSVD1) of the CQIC register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-107 Fields for Register: CQIC (Continued)

Memory
Bits Name Access Description

12:8 INTC_TH W Interrupt Coalescing Counter Threshold filed

Software uses this field to configure the number of task
completions (only tasks with INT=0 in the Task Descriptor),
which are required in order to generate an interrupt.
Counter Operation: As data transfer tasks with INT=0
complete, they are counted by CQE. The counter is reset by
software during the interrupt service routine. The counter
stops counting when it reaches the value configured in
INTC_TH, and generates interrupt.
■ 0x0: Interrupt coalescing feature disabled
■ 0x1: Interrupt coalescing interrupt generated after 1 task
when INT=0 completes
■ 0x2: Interrupt coalescing interrupt generated after 2 tasks
when INT=0 completes
■ ........
■ 0x1f: Interrupt coalescing interrupt generated after 31
tasks when INT=0 completes
To write to this field, the INTC_TH_WEN bit must be set
during the same write operation.
Value After Reset: 0x0
Exists: Always
Testable: untestable

7 TOUT_VAL_WEN W When software writes 1 to this bit, the value TOUT_VAL is

updated with the contents written on the same cycle.
Values:
■ 0x1 (WEN_SET): Sets TOUT_VAL_WEN
■ 0x0 (WEN_CLR): clears TOUT_VAL_WEN
Value After Reset: 0x0
Exists: Always

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Table 5-107 Fields for Register: CQIC (Continued)

Memory
Bits Name Access Description

6:0 TOUT_VAL R/W Interrupt Coalescing Timeout Value

Software uses this field to configure the maximum time
allowed between the completion of a task on the bus and the
generation of an interrupt.
Timer Operation: The timer is reset by software during the
interrupt service routine. It starts running when the first data
transfer task with INT=0 is completed, after the timer was
reset. When the timer reaches the value configured in
ICTOVAL field, it generates an interrupt and stops.
The timer's unit is equal to 1024 clock periods of the clock
whose frequency is specified in the Internal Timer Clock
Frequency field CQCAP register.
■ 0x0: Timer is disabled. Timeout-based interrupt is not
generated
■ 0x1: Timeout on 01x1024 cycles of timer clock frequency
■ 0x2: Timeout on 02x1024 cycles of timer clock frequency
■ ........
■ 0x7f: Timeout on 127x1024 cycles of timer clock
frequency
In order to write to this field, the TOUT_VAL_WEN bit must
be set at the same write operation.
Value After Reset: 0x0
Exists: Always
Testable: untestable

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5.6.9 CQTDLBA
■ Name: Command Queuing Task Descriptor List Base Address register
■ Description: This register is used for configuring the lower 32 bits of the byte address of the head of
the Task Descriptor List in the host memory.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x20
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

TDLBA 31:0

Table 5-108 Fields for Register: CQTDLBA

Memory
Bits Name Access Description

31:0 TDLBA R/W This register stores the LSB bits (31:0) of the byte address of
the head of the Task Descriptor List in system memory.
The size of the task descriptor list is 32 * (Task Descriptor
size + Transfer Descriptor size) as configured by the host
driver. This address is set on 1 KB boundary. The lower 10
bits of this register are set to 0 by the software and are
ignored by CQE.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.6.10 CQTDLBAU
■ Name: Command Queuing Task Descriptor List Base Address Upper register
■ Description: This register is used for configuring the upper 32 bits of the byte address of the head of
the Task Descriptor List in the host memory.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x24
■ Exists: DWC_MSHC_EMMC_CQE_EN==1 && DWC_MSHC_MBIU_AW==64

TDLBAU 31:0

Table 5-109 Fields for Register: CQTDLBAU

Memory
Bits Name Access Description

31:0 TDLBAU R/W This register stores the MSB bits (63:32) of the byte address
of the head of the Task Descriptor List in system memory.
The size of the task descriptor list is 32 * (Task Descriptor
size + Transfer Descriptor size) as configured by Host driver.
This address is set on 1 KB boundary. The lower 10 bits of
this register are set to 0 by the software and are ignored by
CQE. This register is reserved when using 32-bit addressing
mode.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.6.11 CQTDBR
■ Name: Command Queuing DoorBell register
■ Description: Using this register, software triggers CQE to process a new task.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x28
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

DBR 31:0

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Table 5-110 Fields for Register: CQTDBR

Memory
Bits Name Access Description

31:0 DBR R/W The software configures TDLBA and TDLBAU, and enable
CQE in CQCFG before using this register.
Writing 1 to bit n of this register triggers CQE to start
processing the task encoded in slot n of the TDL. Writing 0
by the software does not have any impact on the hardware,
and does not change the value of the register bit.
CQE always processes tasks according to the order
submitted to the list by CQTDBR write transactions. CQE
processes Data Transfer tasks by reading the Task
Descriptor and sending QUEUED_TASK_PARAMS (CMD44)
and QUEUED_TASK_ADDRESS (CMD45) commands to
the device. CQE processes DCMD tasks (in slot #31, when
enabled) by reading the Task Descriptor, and generating the
command encoded by its index and argument.
The corresponding bit is cleared to 0 by CQE in one of the
following events:
■ A task execution is completed (with success or error).
■ The task is cleared using CQTCLR register.
■ All tasks are cleared using CQCTL register.
■ CQE is disabled using CQCFG register.
Software may initiate multiple tasks at the same time (batch
submission) by writing 1 to multiple bits of this register in the
same transaction. In the case of batch submission, CQE
processes the tasks in order of the task index, starting with
the lowest index. If one or more tasks in the batch are
marked with QBR, the ordering of execution is based on said
processing order.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.6.12 CQTCN
■ Name: Command Queuing TaskClear Notification register
■ Description: This register is used by CQE to notify software about completed tasks.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x2c
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

TCN 31:0
Table 5-111 Fields for Register: CQTCN

Memory
Bits Name Access Description

31:0 TCN R/W1C Task Completion Notification

Each of the 32 bits are bit mapped to the 32 tasks.
■ Bit-N(1): Task-N has completed execution (with success
or errors)
■ Bit-N(0): Task-N has not completed, could be pending or
not submitted.
On task completion, software may read this register to know
tasks that have completed. After reading this register,
software may clear the relevant bit fields by writing 1 to the
corresponding bits.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.6.13 CQDQS
■ Name: Device queue status register
■ Description: This register stores the most recent value of the device's queue status.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x30
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

DQS 31:0
Table 5-112 Fields for Register: CQDQS

Memory
Bits Name Access Description

31:0 DQS R Device Queue Status

Each of the 32 bits are bit mapped to the 32 tasks.
■ Bit-N(1): Device has marked task N as ready for
execution
■ Bit-N(0): Task-N is not ready for execution. This task
could be pending in device or not submitted.
Host controller updates this register with response of the
Device Queue Status command.
Value After Reset: 0x0
Exists: Always

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5.6.14 CQDPT
■ Name: Device pending tasks register
■ Description: This register maintains the list of tasks that are queued into device and are awaiting
execution completion.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x34
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

DPT 31:0

Table 5-113 Fields for Register: CQDPT

Memory
Bits Name Access Description

31:0 DPT R Device-Pending Tasks

Each of the 32 bits are bit mapped to the 32 tasks.
■ Bit-N(1): Task-N has been successfully queued into the
device and is awaiting execution
■ Bit-N(0): Task-N is not yet queued.
Bit n of this register is set if and only if
QUEUED_TASK_PARAMS (CMD44) and
QUEUED_TASK_ADDRESS (CMD45) were sent for this
specific task and if this task has not been executed.
The controller sets this bit after receiving a successful
response for CMD45. CQE clears this bit after the task has
completed execution.
Software reads this register in the task-discard procedure to
determine if the task is queued in the device.
Value After Reset: 0x0
Exists: Always

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5.6.15 CQTCLR
■ Name: Command Queuing DoorBell register
■ Description: This register is used for removing an outstanding task in the CQE. The register must be
used only when CQE is in Halt state.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x38
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

TCLR 31:0

Table 5-114 Fields for Register: CQTCLR

Memory
Bits Name Access Description

31:0 TCLR R/W Writing 1 to bit n of this register orders CQE to clear a task
that the software has previously issued.
This bit can only be written when CQE is in Halt state as
indicated in CQCFG register Halt bit. When software writes 1
to a bit in this register, CQE updates the value to 1, and
starts clearing the data structures related to the task. CQE
clears the bit fields (sets a value of 0) in CQTCLR and in
CQTDBR once the clear operation is complete. Software
must poll on the CQTCLR until it is cleared to verify that a
clear operation was done.
Value After Reset: 0x0
Exists: Always
Volatile: true

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5.6.16 CQSSC1
■ Name: CQ Send Status Configuration 1 register
■ Description: This register is used for removing an outstanding task in the CQE. The register controls
when SEND_QUEUE_STATUS commands are sent.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x40
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

31:20
19:16
SQSCMD_IDLE_TMR 15:0
SQSCMD_BLK_CNT
RSVD_20_31

Table 5-115 Fields for Register: CQSSC1

Memory
Bits Name Access Description

31:20 RSVD_20_31 R These bits of the CQSSC1 register are reserved. They
always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-115 Fields for Register: CQSSC1 (Continued)

Memory
Bits Name Access Description

19:16 SQSCMD_BLK_CNT R/W This field indicates when SQS CMD is sent while data
transfer is in progress.
A value of 'n' indicates that CQE sends status command on
the CMD line, during the transfer of data block BLOCK_CNT-
n, on the data lines, where BLOCK_CNT is the number of
blocks in the current transaction.
■ 0x0: SEND_QUEUE_STATUS (CMD13) command is not
sent during the transaction. Instead, it is sent only when
the data lines are idle.
■ 0x1: SEND_QUEUE_STATUS command is to be sent
during the last block of the transaction.
■ 0x2: SEND_QUEUE_STATUS command when last 2
blocks are pending.
■ 0x3: SEND_QUEUE_STATUS command when last 3
blocks are pending.
■ ........
■ 0xf: SEND_QUEUE_STATUS command when last 15
blocks are pending.

Should be programmed only when CQCFG.CQ_EN is '0'

Value After Reset: 0x1
Exists: Always

15:0 SQSCMD_IDLE_TMR R/W This field configures the polling period to be used when
using periodic SEND_QUEUE_STATUS (CMD13) polling.
Periodic polling is used when tasks are pending in the
device, but no data transfer is in progress. When a
SEND_QUEUE_STATUS response indicates that no task is
ready for execution, CQE counts the configured time until it
issues the next SEND_QUEUE_STATUS.
Timer units are clock periods of the clock whose frequency is
specified in the Internal Timer Clock Frequency field CQCAP
register. The minimum value is 0001h (1 clock period) and
the maximum value is FFFFh (65535 clock periods).
For example, a CQCAP field value of 0 indicates a 19.2 MHz
clock frequency (period = 52.08 ns). If the setting in
CQSSC1.CIT is 1000h, the calculated polling period is
4096*52.08 ns= 213.33 ns.
Should be programmed only when CQCFG.CQ_EN is '0'.
Value After Reset: 0x1000
Exists: Always

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5.6.17 CQSSC2
■ Name: CQ Send Status Configuration 2 register
■ Description: The register is used for configuring the RCA field in SEND_QUEUE_STATUS
command argument.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x44
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

31:16
SQSCMD_RCA 15:0
RSVD_16_31

Table 5-116 Fields for Register: CQSSC2

Memory
Bits Name Access Description

31:16 RSVD_16_31 R These bits of the CQSSC2 register are reserved. They
always return 0.
Value After Reset: 0x0
Exists: Always

15:0 SQSCMD_RCA R/W This field provides CQE with the contents of the 16-bit RCA
field in SEND_QUEUE_STATUS (CMD13) command
argument.
CQE copies this field to bits 31:16 of the argument when
transmitting SEND_ QUEUE_STATUS (CMD13) command.
Value After Reset: 0x0
Exists: Always

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5.6.18 CQCRDCT
■ Name: Command response for direct command register
■ Description: This register stores the response of last executed DCMD.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x48
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

DCMD_RESP 31:0

Table 5-117 Fields for Register: CQCRDCT

Memory
Bits Name Access Description

31:0 DCMD_RESP R This register contains the response of the command

generated by the last direct command (DCMD) task that was
sent.
Contents of this register are valid only after bit 31 of
CQTDBR register is cleared by the controller.
Value After Reset: 0x0
Exists: Always

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5.6.19 CQRMEM
■ Name: Command response mode error mask register
■ Description: This register controls the generation of response error detect (RED) interrupt. Only the
bits enabled here can contribute to RED.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x50
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

RESP_ERR_MASK 31:0

Table 5-118 Fields for Register: CQRMEM

Memory
Bits Name Access Description

31:0 RESP_ERR_MASK R/W The bits of this field are bit mapped to the device response.
This bit is used as an interrupt mask on the device status
filed that is received in R1/R1b responses.
■ 1: When a R1/R1b response is received, with a bit i in the
device status set, a RED interrupt is generated.
■ 0: When a R1/R1b response is received, bit i in the device
status is ignored.
The reset value of this register is set to trigger an interrupt on
all "Error" type bits in the device status.
Note: Responses to CMD13 (SQS) encode the QSR so that
they are ignored by this logic.
Value After Reset: 0xfdf9a080
Exists: Always

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5.6.20 CQTERRI
■ Name: CQ Task Error Information register
■ Description: This register is updated by CQE when an error occurs on data or command related to a
task activity. When such an error is detected by CQE or indicated by the eMMC controller, CQE
stores the following in the CQTERRI register: task IDs and indices of commands that were executed
on the command line and data lines when the error occurred.
Software must use this information in the error recovery procedure.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x54
■ Exists: DWC_MSHC_EMMC_CQE_EN==1 30:29
28:24
23:22
21:16

14:13
12:8
7:6
5:0
TRANS_ERR_FIELDS_VALID 31

15
RESP_ERR_FIELDS_VALID
TRANS_ERR_CMD_INDX

RESP_ERR_CMD_INDX
TRANS_ERR_TASKID

RESP_ERR_TASKID
RSVD_30_29

RSVD_23_22

RSVD_13_14

RSVD_6_7

Table 5-119 Fields for Register: CQTERRI

Memory
Bits Name Access Description

31 TRANS_ERR_FIELDS_VALID R This bit is updated when an error is detected while a data

transfer transaction was in progress.
Values:
■ 0x1 (SET): data transfer related error detected. Check
contents of TRANS_ERR_TASKID and
TRANS_ERR_CMD_INDX fields
■ 0x0 (NOT_SET): Ignore contents of
TRANS_ERR_TASKID and TRANS_ERR_CMD_INDX
Value After Reset: 0x0
Exists: Always

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Table 5-119 Fields for Register: CQTERRI (Continued)

Memory
Bits Name Access Description

30:29 RSVD_30_29 R These bits (RSVD_30_29) of the CQTERRI register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

28:24 TRANS_ERR_TASKID R This field captures the ID of the task that was executed and
whose data transfer has errors.
Value After Reset: 0x0
Exists: Always

23:22 RSVD_23_22 R These bits (RSVD_23_22) of the CQTERRI register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

21:16 TRANS_ERR_CMD_INDX R This field captures the index of the command that was
executed and whose data transfer has errors.
Value After Reset: 0x0
Exists: Always

15 RESP_ERR_FIELDS_VALID R This bit is updated when an error is detected while a

command transaction was in progress.
Values:
■ 0x1 (SET): Response-related error is detected. Check
contents of RESP_ERR_TASKID and
RESP_ERR_CMD_INDX fields
■ 0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID
and RESP_ERR_CMD_INDX
Value After Reset: 0x0
Exists: Always

14:13 RSVD_13_14 R These bits (RSVD_13_14) of the CQTERRI register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

12:8 RESP_ERR_TASKID R This field captures the ID of the task which was executed on
the command line when the error occurred.
Value After Reset: 0x0
Exists: Always

7:6 RSVD_6_7 R These bits (RSVD_6_7) of the CQTERRI register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-119 Fields for Register: CQTERRI (Continued)

Memory
Bits Name Access Description

5:0 RESP_ERR_CMD_INDX R This field captures the index of the command that was
executed on the command line when the error occurred.
Value After Reset: 0x0
Exists: Always

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5.6.21 CQCRI
■ Name: CQ Command response index
■ Description: This register stores the index of the last received command response.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x58
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

31:6
CMD_RESP_INDX 5:0
RSVD_31_6

Table 5-120 Fields for Register: CQCRI

Memory
Bits Name Access Description

31:6 RSVD_31_6 R These bits of the CQCRI register are reserved. They always
return 0.
Value After Reset: 0x0
Exists: Always

5:0 CMD_RESP_INDX R Last Command Response index

This field stores the index of the last received command
response. Controller updates the value every time a
command response is received.
Value After Reset: 0x0
Exists: Always

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5.6.22 CQCRA
■ Name: CQ Command response argument register
■ Description: This register stores the argument of the last received command response.
■ Size: 32 bits
■ Offset: P_VENDOR2_SPECIFIC_AREA + 0x5c
■ Exists: DWC_MSHC_EMMC_CQE_EN==1

CMD_RESP_ARG 31:0

Table 5-121 Fields for Register: CQCRA

Memory
Bits Name Access Description

31:0 CMD_RESP_ARG R Last Command Response argument

This field stores the argument of the last received command
response. Controller updates the value every time a
command response is received.
Value After Reset: 0x0
Exists: Always

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5.7 DWC_mshc_map/DWC_mshc_phy_block Registers

This register block has PHY related registers. Follow the link for the register to see a detailed description of
the register.

Table 5-122 Registers for Address Block: DWC_mshc_map/DWC_mshc_phy_block

Register Offset Description

PHY_CNFG on page 502 DWC_MS SD/eMMC PHY General Configuration

HC_PTR
_PHY_R
EGS +
0x0

CMDPAD_CNFG on page 504 DWC_MS SD/eMMC PHY CMD/RESP PAD Setting

HC_PTR
_PHY_R
EGS +
0x4

DATPAD_CNFG on page 506 DWC_MS SD/eMMC PHY Data PAD Setting

HC_PTR
_PHY_R
EGS +
0x6

CLKPAD_CNFG on page 508 DWC_MS SD/eMMC PHY Clock PAD Setting

HC_PTR
_PHY_R
EGS +
0x8

STBPAD_CNFG on page 510 DWC_MS SD/eMMC PHY Strobe PAD Setting

HC_PTR
_PHY_R
EGS +
0xA

RSTNPAD_CNFG on page 512 DWC_MS SD/eMMC PHY RSTN PAD Setting

HC_PTR
_PHY_R
EGS +
0xC

PADTEST_CNFG on page 514 DWC_MS SD/eMMC PHY PAD TEST interface Setting
HC_PTR
_PHY_R
EGS +
0xE

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Table 5-122 Registers for Address Block: DWC_mshc_map/DWC_mshc_phy_block (Continued)

Register Offset Description

PADTEST_OUT on page 515 DWC_MS SD/eMMC PHY PAD TEST Data out value
HC_PTR
_PHY_R
EGS +
0x10

PADTEST_IN on page 516 DWC_MS SD/eMMC PHY PAD TEST Data in value
HC_PTR
_PHY_R
EGS +
0x12

PRBS_CNFG on page 517 DWC_MS Controller PRBS Config register

HC_PTR
_PHY_R
EGS +
0x18

PHYLPBK_CNFG on page 518 DWC_MS Loopback Config register

HC_PTR
_PHY_R
EGS +
0x1A

COMMDL_CNFG on page 520 DWC_MS Common DelayLine config settings register

HC_PTR
_PHY_R
EGS +
0x1C

SDCLKDL_CNFG on page 521 DWC_MS SD/eMMC DelayLine settings

HC_PTR
_PHY_R
EGS +
0x1D

SDCLKDL_DC on page 523 DWC_MS SD/eMMC DelayLine Delay code setting

HC_PTR
_PHY_R
EGS +
0x1E

SMPLDL_CNFG on page 524 DWC_MS SD/eMMC cclk_rx DelayLine settings

HC_PTR
_PHY_R
EGS +
0x20

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Table 5-122 Registers for Address Block: DWC_mshc_map/DWC_mshc_phy_block (Continued)

Register Offset Description

ATDL_CNFG on page 526 DWC_MS SD/eMMC drift_cclk_rx DelayLine configuration settings

HC_PTR
_PHY_R
EGS +
0x21

DLL_CTRL on page 527 DWC_MS SD/eMMC PHY DLL control setting

HC_PTR
_PHY_R
EGS +
0x24

DLL_CNFG1 on page 529 DWC_MS DLL Config register 1

HC_PTR
_PHY_R
EGS +
0x25

DLL_CNFG2 on page 530 DWC_MS DLL Config register 2

HC_PTR
_PHY_R
EGS +
0x26

DLLDL_CNFG on page 531 DWC_MS DLL Config register 2

HC_PTR
_PHY_R
EGS +
0x28

DLL_OFFST on page 533 DWC_MS DLL Offset setting register

HC_PTR
_PHY_R
EGS +
0x29

DLLMST_TSTDC on page 534 DWC_MS DLL Master test code setting register
HC_PTR
_PHY_R
EGS +
0x2A

DLLLBT_CNFG on page 535 DWC_MS DLL LBT setting register

HC_PTR
_PHY_R
EGS +
0x2C

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Table 5-122 Registers for Address Block: DWC_mshc_map/DWC_mshc_phy_block (Continued)

Register Offset Description

DLL_STATUS on page 536 DWC_MS DLL Status register

HC_PTR
_PHY_R
EGS +
0x2E

DLLDBG_MLKDC on page 538 DWC_MS DLL Master lock code debug register
HC_PTR
_PHY_R
EGS +
0x30

DLLDBG_SLKDC on page 539 DWC_MS DLL Master Slave code debug register
HC_PTR
_PHY_R
EGS +
0x32

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5.7.1 PHY_CNFG
■ Name: SD/eMMC PHY General Configuration
■ Description: SD/eMMC PHY general configuration register
■ Size: 32 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x0
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1)

31:24
23:20
19:16
15:2
PHY_PWRGOOD 1
0
PHY_RSTN
PAD_SN
PAD_SP
Rsvd

Rsvd

Table 5-123 Fields for Register: PHY_CNFG

Memory
Bits Name Access Description

31:24 Reserved Field: Yes

23:20 PAD_SN R/W NMOS TX drive strength control. Common config for all for
SD/eMMC Pads.
Value After Reset: 0x0
Exists: Always

19:16 PAD_SP R/W PMOS TX drive strength control. Common config for all for
SD/eMMC Pads.
Value After Reset: 0x0
Exists: Always

15:2 Reserved Field: Yes

1 PHY_PWRGOOD R Phy's Power Good status is captured here. Ensure this is '1'
before stating transactions.
Value After Reset: 0x0
Exists: Always
Reset Mask: 0x0

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Table 5-123 Fields for Register: PHY_CNFG (Continued)

Memory
Bits Name Access Description

0 PHY_RSTN R/W Active-Low reset control for PHY, write '0' to reset PHY, Write
'1' to deassert reset.
Value After Reset: 0x0
Exists: Always

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5.7.2 CMDPAD_CNFG
■ Name: SD/eMMC PHY CMD/RESP PAD Setting
■ Description: SD/eMMC PHY's Command/Response PAD settings are controlled here
■ Size: 16 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x4
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1)

15:13
TXSLEW_CTRL_N 12:9
TXSLEW_CTRL_P 8:5
4:3
2:0
WEAKPULL_EN
RXSEL
Rsvd

Table 5-124 Fields for Register: CMDPAD_CNFG

Memory
Bits Name Access Description

15:13 Reserved Field: Yes

12:9 TXSLEW_CTRL_N R/W Slew control for N-Type CMD Pad's TX

Value After Reset: 0x2
Exists: Always

8:5 TXSLEW_CTRL_P R/W Slew control for P-Type CMD Pad's TX

Value After Reset: 0x2
Exists: Always

4:3 WEAKPULL_EN R/W Pull-up/Pul-down enable control for CMD PAD

Values:
■ 0x0 (DISABLED): Pull-up and pull-down functionality
disabled
■ 0x1 (PULLUP): Weak pull up enabled
■ 0x2 (PULLDOWN): Weak pull down enabled
■ 0x3 (ILLEGAL): Should not be used
Value After Reset: 0x0
Exists: Always

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Table 5-124 Fields for Register: CMDPAD_CNFG (Continued)

Memory
Bits Name Access Description

2:0 RXSEL R/W Reciver type select for PAD. Controls the RXSEL value of
SD/eMMC PHY CMD PAD
Value After Reset: 0x0
Exists: Always

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5.7.3 DATPAD_CNFG
■ Name: SD/eMMC PHY Data PAD Setting
■ Description: SD/eMMC PHY's Data PAD settings are controlled here. common settings for all data
pads
■ Size: 16 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x6
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1)

15:13
TXSLEW_CTRL_N 12:9
TXSLEW_CTRL_P 8:5
4:3
2:0
WEAKPULL_EN
RXSEL
Rsvd

Table 5-125 Fields for Register: DATPAD_CNFG

Memory
Bits Name Access Description

15:13 Reserved Field: Yes

12:9 TXSLEW_CTRL_N R/W Slew control for N-Type DATA Pad's TX

Value After Reset: 0x2
Exists: Always

8:5 TXSLEW_CTRL_P R/W Slew control for P-Type DATA Pad's TX

Value After Reset: 0x2
Exists: Always

4:3 WEAKPULL_EN R/W Pull-up/Pull-down enable control for DATA PADs

Values:
■ 0x0 (DISABLED): Pull-up and pull-down functionality
disabled
■ 0x1 (PULLUP): Weak pull up enabled
■ 0x2 (PULLDOWN): Weak pull down enabled
■ 0x3 (ILLEGAL): Should not be used
Value After Reset: 0x0
Exists: Always

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Table 5-125 Fields for Register: DATPAD_CNFG (Continued)

Memory
Bits Name Access Description

2:0 RXSEL R/W Reciver type select for PAD. Controls the RXSEL value of
SD/eMMC PHY DATA PADs
Value After Reset: 0x0
Exists: Always

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5.7.4 CLKPAD_CNFG
■ Name: SD/eMMC PHY Clock PAD Setting
■ Description: SD/eMMC PHY's CLK PAD settings are controlled here.
■ Size: 16 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x8
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1)

15:13
TXSLEW_CTRL_N 12:9
TXSLEW_CTRL_P 8:5
4:3
2:0
WEAKPULL_EN
RXSEL
Rsvd

Table 5-126 Fields for Register: CLKPAD_CNFG

Memory
Bits Name Access Description

15:13 Reserved Field: Yes

12:9 TXSLEW_CTRL_N R/W Slew control for N-Type CLK Pad's TX

Value After Reset: 0x2
Exists: Always

8:5 TXSLEW_CTRL_P R/W Slew control for P-Type CLK Pad's TX

Value After Reset: 0x2
Exists: Always

4:3 WEAKPULL_EN R/W Pull-up/Pul-down enable control for CLK PAD

Values:
■ 0x0 (DISABLED): Pull-up and pull-down functionality
disabled
■ 0x1 (PULLUP): Weak pull up enabled
■ 0x2 (PULLDOWN): Weak pull down enabled
■ 0x3 (ILLEGAL): Should not be used
Value After Reset: 0x0
Exists: Always

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Table 5-126 Fields for Register: CLKPAD_CNFG (Continued)

Memory
Bits Name Access Description

2:0 RXSEL R/W Reciver type select for PAD. Controls the RXSEL value of
SD/eMMC PHY CLK PAD
Value After Reset: 0x0
Exists: Always

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5.7.5 STBPAD_CNFG
■ Name: SD/eMMC PHY Strobe PAD Setting
■ Description: SD/eMMC PHY's Strobe PAD settings are controlled here.
■ Size: 16 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0xA
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1)

15:13
TXSLEW_CTRL_N 12:9
TXSLEW_CTRL_P 8:5
4:3
2:0
WEAKPULL_EN
RXSEL
Rsvd

Table 5-127 Fields for Register: STBPAD_CNFG

Memory
Bits Name Access Description

15:13 Reserved Field: Yes

12:9 TXSLEW_CTRL_N R/W Slew control for N-Type Strobe Pad's TX

Value After Reset: 0x2
Exists: Always

8:5 TXSLEW_CTRL_P R/W Slew control for P-Type Strobe Pad's TX

Value After Reset: 0x2
Exists: Always

4:3 WEAKPULL_EN R/W Pull-up/Pul-down enable control for STROBE PAD

Values:
■ 0x0 (DISABLED): Pull-up and pull-down functionality
disabled
■ 0x1 (PULLUP): Weak pull up enabled
■ 0x2 (PULLDOWN): Weak pull down enabled
■ 0x3 (ILLEGAL): Should not be used
Value After Reset: 0x0
Exists: Always

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Table 5-127 Fields for Register: STBPAD_CNFG (Continued)

Memory
Bits Name Access Description

2:0 RXSEL R/W Reciver type select for PAD. Controls the RXSEL value of
SD/eMMC PHY STROBE PAD
Value After Reset: 0x0
Exists: Always

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5.7.6 RSTNPAD_CNFG
■ Name: SD/eMMC PHY RSTN PAD Setting
■ Description: SD/eMMC PHY's RSTN PAD settings are controlled here.
■ Size: 16 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0xC
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1)

15:13
TXSLEW_CTRL_N 12:9
TXSLEW_CTRL_P 8:5
4:3
2:0
WEAKPULL_EN
RXSEL
Rsvd

Table 5-128 Fields for Register: RSTNPAD_CNFG

Memory
Bits Name Access Description

15:13 Reserved Field: Yes

12:9 TXSLEW_CTRL_N R/W Slew control for N-Type RST_N Pad's TX

Value After Reset: 0x2
Exists: Always

8:5 TXSLEW_CTRL_P R/W Slew control for P-Type RST_N Pad's TX

Value After Reset: 0x2
Exists: Always

4:3 WEAKPULL_EN R/W Pull-up/Pul-down enable control for RST_N PAD(s)

Values:
■ 0x0 (DISABLED): Pull-up and pull-down functionality
disabled
■ 0x1 (PULLUP): Weak pull up enabled
■ 0x2 (PULLDOWN): Weak pull down enabled
■ 0x3 (ILLEGAL): Should not be used
Value After Reset: 0x0
Exists: Always

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Table 5-128 Fields for Register: RSTNPAD_CNFG (Continued)

Memory
Bits Name Access Description

2:0 RXSEL R/W Reciver type select for PAD. Controls the RXSEL value of
SD/eMMC PHY RST_N PAD(s)
Value After Reset: 0x0
Exists: Always

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5.7.7 PADTEST_CNFG
■ Name: SD/eMMC PHY PAD TEST interface Setting
■ Description: PAD TEST Path and direction control
■ Size: 16 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0xE
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1)

15:10
9:4
3:1
TESTMODE_EN 0
TEST_OE
RSVD_1
Rsvd

Table 5-129 Fields for Register: PADTEST_CNFG

Memory
Bits Name Access Description

15:10 Reserved Field: Yes

9:4 TEST_OE R/W test interface OE control. Drive's PHY's itest_oe inputs.
Value After Reset: 0x0
Exists: Always

3:1 RSVD_1 R RSVD1 field is reserved

Reserved Field: Yes
Value After Reset: 0x0
Exists: Always

0 TESTMODE_EN R/W enables test mode interface for all PADS. Functional
interface is disabled.
Values:
■ 0x0 (PAD_FUNCMODE): PAD's functional mode I/F is
active
■ 0x1 (PAD_TESTMODE): PAD's test mode interface is
active
Value After Reset: 0x0
Exists: Always

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5.7.8 PADTEST_OUT
■ Name: SD/eMMC PHY PAD TEST Data out value
■ Description: PAD TEST Path Data out, Drives itest_a input of SD/eMMC PHY
■ Size: 16 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x10
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1)

15:6
TESTDATA_OUT 5:0
Rsvd

Table 5-130 Fields for Register: PADTEST_OUT

Memory
Bits Name Access Description

15:6 Reserved Field: Yes

5:0 TESTDATA_OUT R/W Data written here is reflected on corresponding itest_a.

Indivitual bits are mapped to corresponding itest_a inputs of
the PHY
Value After Reset: 0x0
Exists: Always

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5.7.9 PADTEST_IN
■ Name: SD/eMMC PHY PAD TEST Data in value
■ Description: PAD TEST Path Data in, reflects value of otest_y output of SD/eMMC PHY
■ Size: 16 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x12
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1)

15:6
TESTDATA_IN 5:0
Rsvd

Table 5-131 Fields for Register: PADTEST_IN

Memory
Bits Name Access Description

15:6 Reserved Field: Yes

5:0 TESTDATA_IN R individual bits here capture data avaliable on corresponding

otest_y output. should be used for DC test and low freq data
patterns.
Value After Reset: 0x0
Exists: Always

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5.7.10 PRBS_CNFG
■ Name: Controller PRBS Config register
■ Description: Register to configure PRBS engine
■ Size: 16 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x18
■ Exists: (DWC_MSHC_SDEMMC_PHY_DFT== 1)

INIT_SEED 15:0

Table 5-132 Fields for Register: PRBS_CNFG

Memory
Bits Name Access Description

15:0 INIT_SEED R/W Value programmed here is used as SEED for PRBS engine
Value After Reset: 0xffff
Exists: Always

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5.7.11 PHYLPBK_CNFG
■ Name: Loopback Config register
■ Description: Register to setup loopback mode
■ Size: 8 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x1A
■ Exists: (DWC_MSHC_SDEMMC_PHY_DFT== 1)

7:2
OUT_EN_PHYLPBK_MODE 1
0
PHYLPBK_EN
Rsvd

Table 5-133 Fields for Register: PHYLPBK_CNFG

Memory
Bits Name Access Description

7:2 Reserved Field: Yes

1 OUT_EN_PHYLPBK_MODE R/W CMD/DATA output enable in PHY loopback mode

Values:
■ 0x1 (OUTPUT_EN): CMD/DATA output is enable PHY
Loopback mode
■ 0x0 (OUTPUT_DIS): CMD/DATA output is disable PHY
Loopback mode
Value After Reset: 0x0
Exists: Always

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Table 5-133 Fields for Register: PHYLPBK_CNFG (Continued)

Memory
Bits Name Access Description

0 PHYLPBK_EN R/W PHY Local loop back mode is enable

Values:
■ 0x1 (PHYLPBK_MODE_EN): Controller is now in PHY
Loopback mode
■ 0x0 (PHYLPBK_MODE_DIS): Controller is not in PHY
loopback mode
Value After Reset: 0x0
Exists: Always

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5.7.12 COMMDL_CNFG
■ Name: Common DelayLine config settings register
■ Description: Config register to settings common to all DelayLines used in PHY
■ Size: 8 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x1C
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1)

7:2
1
DLSTEP_SEL 0
DLOUT_EN
Rsvd

Table 5-134 Fields for Register: COMMDL_CNFG

Memory
Bits Name Access Description

7:2 Reserved Field: Yes

1 DLOUT_EN R/W When '1' DL outputs can be sampled on PADs. Drives

idlout_en for all PADs
Values:
■ 0x1 (DL_OUTEN): DelayLine outputs on PAD enabled
■ 0x0 (DL_OUTDIS): DelayLine outputs on PAD disabled
Value After Reset: 0x0
Exists: Always

0 DLSTEP_SEL R/W DelayLine's per step delay selection, Drives PHY's idl_step
input
Value After Reset: 0x0
Exists: Always

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5.7.13 SDCLKDL_CNFG
■ Name: SD/eMMC DelayLine settings
■ Description: Settings for SD/eMMC CLK DelayLine.
■ Size: 8 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x1D
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1)

7:5

INPSEL_CNFG 3:2
4

1
0
UPDATE_DC

BYPASS_EN
EXTDLY_EN
Rsvd

Table 5-135 Fields for Register: SDCLKDL_CNFG

Memory
Bits Name Access Description

7:5 Reserved Field: Yes

4 UPDATE_DC R/W Prepares DealyLine for code update when '1'. Its
recommended that this bit is 1 when SDCLKDL_DC is being
written. Ensure this is '0' when not updating code. Note:
Turn-off card clock using CLK_CTRL_R.SD_CLK_EN before
programing this field.
Values:
■ 0x1 (BYPASSMODE): output of DelayLine is DelayLine
output active
■ 0x0 (DLMODE): DelayLine output is enabled
Value After Reset: 0x0
Exists: Always

3:2 INPSEL_CNFG R/W Drives SD/eMMC CLK DelayLine's config input. Value here
selects the input source to DelayLine
Value After Reset: 0x0
Exists: Always

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Table 5-135 Fields for Register: SDCLKDL_CNFG (Continued)

Memory
Bits Name Access Description

1 BYPASS_EN R/W Drives SD/eMMC CLK DelayLine's bypassen input

Values:
■ 0x1 (BYPASSMODE): DelayLine is bypass mode
■ 0x0 (DLMODE): Delay line active mode
Value After Reset: 0x0
Exists: Always

0 EXTDLY_EN R/W Drives SD/eMMC CLK DelayLine's extdlyen input

Values:
■ 0x1 (EXTDL_MODE): DelayLine works with extended
delay range setting
■ 0x0 (DEF_MODE): Delay line defaut range setting
Value After Reset: 0x0
Exists: Always

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5.7.14 SDCLKDL_DC
■ Name: SD/eMMC DelayLine Delay code setting
■ Description: SD/eMMC CLK DelayLine Delay Code value
■ Size: 8 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x1E
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1)

CCKDL_DC 6:0
7
Rsvd

Table 5-136 Fields for Register: SDCLKDL_DC

Memory
Bits Name Access Description

7 Reserved Field: Yes

6:0 CCKDL_DC R/W Drives SD/eMMC CLK DelayLine's Delay Code input. Value
here Selects the number of active stages in the card clock
delay line.Note: Turn-off card clock using
CLK_CTRL_R.SD_CLK_EN before programing this field.
Value After Reset: 0x0
Exists: Always

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5.7.15 SMPLDL_CNFG
■ Name: SD/eMMC cclk_rx DelayLine settings
■ Description: SD/eMMC cclk_rx DelayLine configuration settings
■ Size: 8 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x20
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1)

7:5

3:2
INPSEL_OVERRIDE 4

1
0
INPSEL_CNFG
BYPASS_EN
EXTDLY_EN
Rsvd

Table 5-137 Fields for Register: SMPLDL_CNFG

Memory
Bits Name Access Description

7:5 Reserved Field: Yes

4 INPSEL_OVERRIDE R/W PHY's Sampling delay line config is controlled by controller

using sample_cclk_sel, this signal overides sample_cclk_sel
such that INPSEL_CFG field directly control's PHY's config
input.
■ 0x0 : Controller logic drive Sampling delay line config.
■ 0x1 : SMPLDL_CNFG.INPSEL_CNFG drives sampling
delay line config.
Value After Reset: 0x0
Exists: Always

3:2 INPSEL_CNFG R/W Drives CCLK_RX DelayLine's config input. Value here
selects the input source to DelayLine
Value After Reset: 0x3
Exists: Always

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Table 5-137 Fields for Register: SMPLDL_CNFG (Continued)

Memory
Bits Name Access Description

1 BYPASS_EN R/W Drives CCLK_RX DelayLine's bypassen input

Values:
■ 0x1 (BYPASSMODE): DelayLine is bypass mode
■ 0x0 (DLMODE): Delay line active mode
Value After Reset: 0x1
Exists: Always

0 EXTDLY_EN R/W Drives CCLK_RX DelayLine's extdlyen input

Values:
■ 0x1 (EXTDL_MODE): DelayLine works with extended
delay range setting
■ 0x0 (DEF_MODE): Delay line defaut range setting
Value After Reset: 0x0
Exists: Always

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5.7.16 ATDL_CNFG
■ Name: SD/eMMC drift_cclk_rx DelayLine configuration settings
■ Description: SD/eMMC drift_cclk_rx DelayLine configuration settings
■ Size: 8 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x21
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1)

7:4
INPSEL_CNFG 3:2
1
0
BYPASS_EN
EXTDLY_EN
Rsvd

Table 5-138 Fields for Register: ATDL_CNFG

Memory
Bits Name Access Description

7:4 Reserved Field: Yes

3:2 INPSEL_CNFG R/W Drives drift_cclk_rx DelayLine's config input. Value here
selects the input source to DelayLine
Value After Reset: 0x0
Exists: Always

1 BYPASS_EN R/W Drives drift_cclk_rx DelayLine's bypassen input

Values:
■ 0x1 (BYPASSMODE): DelayLine is bypass mode
■ 0x0 (DLMODE): Delay line active mode
Value After Reset: 0x0
Exists: Always

0 EXTDLY_EN R/W Drives drift_cclk_rx DelayLine's extdlyen input

Values:
■ 0x1 (EXTDL_MODE): DelayLine works with extended
delay range setting
■ 0x0 (DEF_MODE): Delay line defaut range setting
Value After Reset: 0x0
Exists: Always

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5.7.17 DLL_CTRL
■ Name: SD/eMMC PHY DLL control setting
■ Description: SD/eMMC PHY's DLL Control settings register
■ Size: 8 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x24
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1) &&
(DWC_MSHC_EMMC_DATASTROBE_EN==1)

7:3
SLV_SWDC_UPDATE 2
1
0
OFFST_EN
RSVD_3_7

DLL_EN

Table 5-139 Fields for Register: DLL_CTRL

Memory
Bits Name Access Description

7:3 RSVD_3_7 R These bits of the register are reserved.

Reserved Field: Yes
Value After Reset: 0x0
Exists: Always

2 SLV_SWDC_UPDATE R/W Corresponding output drives PHY's DLL Slave's dc update

input. This is used to turn-off Slave Delay line's output when
changing its delay code using DLL_OFFST register
Values:
■ 0x1 (DL_OUT_OFF): Update in progress
■ 0x0 (DL_OUT_ON): Update completed
Value After Reset: 0x0
Exists: Always

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Table 5-139 Fields for Register: DLL_CTRL (Continued)

Memory
Bits Name Access Description

1 OFFST_EN R/W Enables offset mode of PHY when DLL is enabled. when
DLL is disabled this allows direct control of delay generated
by DLL's Slave
Values:
■ 0x1 (OFFSTEN): Offset value is valid
■ 0x0 (OFFSTDIS): offset value is invalid
Value After Reset: 0x0
Exists: Always

0 DLL_EN R/W Enable's DLL when '1'

Values:
■ 0x1 (DLLENABLE): PHY DLL is enabled
■ 0x0 (DLLDISABLE): PHY DLL is disabled
Value After Reset: 0x0
Exists: Always

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5.7.18 DLL_CNFG1
■ Name: DLL Config register 1
■ Description: SD/eMMC PHY DLL configuration register 1
■ Size: 8 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x25
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1) &&
(DWC_MSHC_EMMC_DATASTROBE_EN==1)

7:6
5:4

WAITCYCLE 2:0
3
SLVDLY
Rsvd

Rsvd

Table 5-140 Fields for Register: DLL_CNFG1

Memory
Bits Name Access Description

7:6 Reserved Field: Yes

5:4 SLVDLY R/W Sets the value of DLL slave's update delay input
islv_update_dly
Value After Reset: 0x0
Exists: Always

3 Reserved Field: Yes

2:0 WAITCYCLE R/W Sets the value of DLL's wait cycle input
Value After Reset: 0x0
Exists: Always

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5.7.19 DLL_CNFG2
■ Name: DLL Config register 2
■ Description: SD/eMMC PHY DLL configuration register 2
■ Size: 8 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x26
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1) &&
(DWC_MSHC_EMMC_DATASTROBE_EN==1)

JUMPSTEP 6:0
7
Rsvd

Table 5-141 Fields for Register: DLL_CNFG2

Memory
Bits Name Access Description

7 Reserved Field: Yes

6:0 JUMPSTEP R/W Sets the value of DLL's jump step input
Value After Reset: 0x0
Exists: Always

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5.7.20 DLLDL_CNFG
■ Name: DLL Config register 2
■ Description: SD/eMMC PHY DLL MST & Slave DL configuration settings
■ Size: 8 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x28
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1) &&
(DWC_MSHC_EMMC_DATASTROBE_EN==1)

6:5

2:1
7

4
3

MST_EXTDLYEN 0
SLV_EXTDLYEN
MST_BYPASS
SLV_BYPASS

MST_INPSEL
SLV_INPSEL

Table 5-142 Fields for Register: DLLDL_CNFG

Memory
Bits Name Access Description

7 SLV_BYPASS R/W Bypass enable control for Slave DL

Value After Reset: 0x0
Exists: Always

6:5 SLV_INPSEL R/W Clock source select for Slave DL

Value After Reset: 0x0
Exists: Always

4 SLV_EXTDLYEN R/W Enable Extended delay mode for Slave

Value After Reset: 0x0
Exists: Always

3 MST_BYPASS R/W Bypass enable control for Master DL

Value After Reset: 0x0
Exists: Always

2:1 MST_INPSEL R/W Clock source select for Master DL

Value After Reset: 0x0
Exists: Always

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Table 5-142 Fields for Register: DLLDL_CNFG (Continued)

Memory
Bits Name Access Description

0 MST_EXTDLYEN R/W Enable Extended delay mode for master

Value After Reset: 0x0
Exists: Always

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5.7.21 DLL_OFFST
■ Name: DLL Offset setting register
■ Description: SD/eMMC PHY DLL Offset value settings
■ Size: 8 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x29
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1) &&
(DWC_MSHC_EMMC_DATASTROBE_EN==1)

OFFST 6:0
7
Rsvd

Table 5-143 Fields for Register: DLL_OFFST

Memory
Bits Name Access Description

7 Reserved Field: Yes

6:0 OFFST R/W Sets the value of DLL's offset input

Value After Reset: 0x0
Exists: Always

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5.7.22 DLLMST_TSTDC
■ Name: DLL Master test code setting register
■ Description: SD/eMMC PHY DLL Master testing Delay code register
■ Size: 8 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x2A
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1) &&
(DWC_MSHC_EMMC_DATASTROBE_EN==1)

MSTTST_DC 6:0
7
Rsvd

Table 5-144 Fields for Register: DLLMST_TSTDC

Memory
Bits Name Access Description

7 Reserved Field: Yes

6:0 MSTTST_DC R/W Sets the value of DLL's Master test code input when DLL is
disabled.
Value After Reset: 0x0
Exists: Always

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5.7.23 DLLLBT_CNFG
■ Name: DLL LBT setting register
■ Description: SD/eMMC PHY DLL Low Bandwidth Timer configuration register
■ Size: 16 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x2C
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1) &&
(DWC_MSHC_EMMC_DATASTROBE_EN==1)

LBT_LOADVAL 15:0

Table 5-145 Fields for Register: DLLLBT_CNFG

Memory
Bits Name Access Description

15:0 LBT_LOADVAL R/W Sets the value of DLL's olbt_loadval input. Controls the lbt
timer's timeout value at which DLL runs a revalidation cycle.
Value After Reset: 0x0
Exists: Always

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5.7.24 DLL_STATUS
■ Name: DLL Status register
■ Description: SD/eMMC PHY DLL Status register
■ Size: 8 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x2E
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1) &&
(DWC_MSHC_EMMC_DATASTROBE_EN==1)

7:2
ERROR_STS 1
0
LOCK_STS
Rsvd

Table 5-146 Fields for Register: DLL_STATUS

Memory
Bits Name Access Description

7:2 Reserved Field: Yes

1 ERROR_STS R Captures the value of DLL's lock error status information.

Value is valid only when LOCK_STS is set.
■ IF LOCK_STS =1 and ERR_STS = 0 then DLL is locked
and no errors are generated
■ IF LOCK_STS =1 and ERR_STS = 1 then DLL is locked
to default and has errors. Transactions at this phase can
fail

Values:
■ 0x1 (DLL_ERROR): DLL is locked and ready
■ 0x0 (DLL_LOCK_OKAY): DLL has not locked
Value After Reset: 0x0
Exists: Always

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Table 5-146 Fields for Register: DLL_STATUS (Continued)

Memory
Bits Name Access Description

0 LOCK_STS R Captures the value of DLL's lock status information

Values:
■ 0x1 (DLL_IS_LOCKED): DLL is locked and ready
■ 0x0 (DLL_NOT_LOCKED): DLL has not locked
Value After Reset: 0x0
Exists: Always

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5.7.25 DLLDBG_MLKDC
■ Name: DLL Master lock code debug register
■ Description: SD/eMMC PHY DLL's Master lock code status
■ Size: 8 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x30
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1) &&
(DWC_MSHC_EMMC_DATASTROBE_EN==1)

MSTLKDC 6:0
7
Rsvd

Table 5-147 Fields for Register: DLLDBG_MLKDC

Memory
Bits Name Access Description

7 Reserved Field: Yes

6:0 MSTLKDC R Captures the value Delay Code to which DLL's Master has
locked
Value After Reset: 0x0
Exists: Always

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5.7.26 DLLDBG_SLKDC
■ Name: DLL Master Slave code debug register
■ Description: SD/eMMC PHY DLL's Slave lock code status
■ Size: 8 bits
■ Offset: DWC_MSHC_PTR_PHY_REGS + 0x32
■ Exists: (DWC_MSHC_SDEMMC_PHY_REGS== 1) &&
(DWC_MSHC_EMMC_DATASTROBE_EN==1)

SLVLKDC 6:0
7
Rsvd

Table 5-148 Fields for Register: DLLDBG_SLKDC

Memory
Bits Name Access Description

7 Reserved Field: Yes

6:0 SLVLKDC R Captures the value Delay Code to which DLL's Slave has
locked
Value After Reset: 0x0
Exists: Always

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5.8 DWC_mshc_map/DWC_mshc_vendor1_block Registers

This register block defines Vendor-1 related registers. Follow the link for the register to see a detailed
description of the register.

Table 5-149 Registers for Address Block: DWC_mshc_map/DWC_mshc_vendor1_block

Register Offset Description

MSHC_VER_ID_R on page 542 P_VEND MSHC version

OR_SPE
CIFIC_A
REA[11:0
]

MSHC_VER_TYPE_R on page 543 P_VEND MSHC version type

OR_SPE
CIFIC_A
REA[11:0
] + 0x4

MSHC_CTRL_R on page 544 P_VEND MSHC Control register

OR_SPE
CIFIC_A
REA[11:0
] + 0x8

MBIU_CTRL_R on page 547 P_VEND MBIU Control register

OR_SPE
CIFIC_A
REA[11:0
] + 0x10

EMMC_CTRL_R on page 549 P_VEND eMMC Control register

OR_SPE
CIFIC_A
REA[11:0
] + 0x2c

BOOT_CTRL_R on page 552 P_VEND eMMC Boot Control register

OR_SPE
CIFIC_A
REA[11:0
] + 0x2e

GP_IN_R on page 554 P_VEND General Purpose Input register

OR_SPE
CIFIC_A
REA[11:0
] + 0x30

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Table 5-149 Registers for Address Block: DWC_mshc_map/DWC_mshc_vendor1_block (Continued)

Register Offset Description

GP_OUT_R on page 555 P_VEND General Purpose Output register

OR_SPE
CIFIC_A
REA[11:0
] + 0x34

AT_CTRL_R on page 556 P_VEND Tuning and Auto-tuning control register

OR_SPE
CIFIC_A
REA[11:0
] + 0x40

AT_STAT_R on page 561 P_VEND Tuning and Auto-tuning status register

OR_SPE
CIFIC_A
REA[11:0
] + 0x44

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5.8.1 MSHC_VER_ID_R
■ Name: MSHC version
■ Description: This register reflects the current release number of DWC_mshc/DWC_mshc_lite.
■ Size: 32 bits
■ Offset: P_VENDOR_SPECIFIC_AREA[11:0]
■ Exists: Always

MSHC_VER_ID 31:0

Table 5-150 Fields for Register: MSHC_VER_ID_R

Memory
Bits Name Access Description

31:0 MSHC_VER_ID R Current release number

This field indicates the Synopsys DesignWare Cores
DWC_mshc/DWC_mshc_lite current release number that is
read by an application.
An application reading this register in conjunction with the
MSHC_VER_TYPE_R register, gathers details of the current
release.
Value After Reset: MSHC_VERSION_ID
Exists: Always

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5.8.2 MSHC_VER_TYPE_R
■ Name: MSHC version type
■ Description: This register reflects the current release type of DWC_mshc/DWC_mshc_lite.
■ Size: 32 bits
■ Offset: P_VENDOR_SPECIFIC_AREA[11:0] + 0x4
■ Exists: Always

MSHC_VER_TYPE 31:0

Table 5-151 Fields for Register: MSHC_VER_TYPE_R

Memory
Bits Name Access Description

31:0 MSHC_VER_TYPE R Current release type

This field indicates the Synopsys DesignWare Cores
DWC_mshc/DWC_mshc_lite current release type that is
read by an application.
An application reading this register in conjunction with the
MSHC_VER_ID_R register, gathers details of the current
release.
Value After Reset: MSHC_VERSION_TYPE
Exists: Always

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5.8.3 MSHC_CTRL_R
■ Name: MSHC Control register
■ Description: This register is used to control the operation of MSHC Host Controller.
■ Size: 8 bits
■ Offset: P_VENDOR_SPECIFIC_AREA[11:0] + 0x8
■ Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!= 2) ||
(DWC_MSHC_INTERNAL_CLK_GATE==1) || (DWC_MSHC_MBIU_CLK_GATE==1) ||
(DWC_MSHC_DMA_CLK_GATE==1) || (DWC_MSHC_CQE_CLK_GATE==1) ||
(DWC_MSHC_TS_CLK_GATE==1) || (DWC_MSHC_ASYNC_CLK_GATE==1)

3:2
7
6
SLV_ERR_RESP_NONEXIS_REG 5
4

1
0
NEGEDGE_DATAOUT_EN
CMD_CONFLICT_CHECK
NEDGE_SMPL_EN
PEDGE_DRV_EN

SW_CG_DIS
RSVD1

Table 5-152 Fields for Register: MSHC_CTRL_R

Memory
Bits Name Access Description

7 NEDGE_SMPL_EN R/W Samples CMD/DATA with respect to negative edge of cclk_rx

for low speed SDR only support.
Note: Negedge sampling shall be enable only if the total
output delay is greater that (t_clockperiod ? t_setup ? t_diff)
and limited to (1.5*t_clockperiod ? t_setup ? t_diff).
Values:
■ 0x0 (PEDGE_SMPL): Samples CMD/DATA with respect
to positive edge of cclk_rx
■ 0x1 (NEDGE_SMPL): Samples CMD/DATA with respect
to negative edge of cclk_rx
Value After Reset: 0x0
Exists: (DWC_MSHC_LS_NO_PHY_MODE==1)

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Table 5-152 Fields for Register: MSHC_CTRL_R (Continued)

Memory
Bits Name Access Description

6 PEDGE_DRV_EN R/W Launches CMD/DATA with respect to positive edge of cclk_tx

for low speed SDR only support.
Values:
■ 0x0 (NEDGE_DRV): Launches CMD/DATA with respect
to negative edge of cclk_tx
■ 0x1 (PEDGE_DRV): Launches CMD/DATA with respect
to positive edge of cclk_tx
Value After Reset: 0x0
Exists: (DWC_MSHC_LS_NO_PHY_MODE==1)

5 SLV_ERR_RESP_NONEXIS_RE R When 0 this bit gives slave error response for non existent
G register access. Currently this is a read-ony bit with default
value 0.
Value After Reset: 0x0
Exists: (DWC_MSHC_SLV_RESPONSE_TYPE==1)

4 SW_CG_DIS R/W Internal clock gating disable control

This bit must be used to disable IP's internal clock gating
when required. when disabled clocks are not gated. Clocks
to the core (except hclk) must be stopped when
programming this bit.
Values:
■ 0x0 (ENABLE): Internal clock gates are active and clock
gating is controlled internally
■ 0x1 (DISABLE): Internal clock gating is disabled, clocks
are not gated internally
Value After Reset: 0x0
Exists: (DWC_MSHC_INTERNAL_CLK_GATE==1) ||
(DWC_MSHC_MBIU_CLK_GATE==1) ||
(DWC_MSHC_DMA_CLK_GATE==1) ||
(DWC_MSHC_CQE_CLK_GATE==1) ||
(DWC_MSHC_TS_CLK_GATE==1) ||
(DWC_MSHC_ASYNC_CLK_GATE==1)

3:2 RSVD1 R These bits (RSVD1) of the MSHC_CTRL_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-152 Fields for Register: MSHC_CTRL_R (Continued)

Memory
Bits Name Access Description

1 NEGEDGE_DATAOUT_EN R/W Negedge Data Out

This bit enables the data to be sent out on negedge of
cclk_tx. This is valid only for speed mode HS400.
Values:
■ 0x0 (DISABLED): Negedge data sent out disabled
■ 0x1 (ENABLED): Negedge data sent out enabled
Value After Reset: 0x0
Exists: (DWC_MSHC_NEG_DATA_HS400_MODE==1)

0 CMD_CONFLICT_CHECK R/W Command conflict check

This bit enables command conflict check.
Note: DWC_mshc controller monitors the CMD line
whenever a command is issued and checks whether the
value driven on sd_cmd_out matches the value on
sd_cmd_in at next subsequent edge of cclk_tx to determine
command conflict error. This bit is cleared only if the feed
back delay (including IO Pad delay) is more than
(t_card_clk_period - t_setup), where t_setup is the setup
time of a flop in DWC_mshc. The I/O pad delay is consistent
across CMD and DATA lines, and it is within the value:
(2*t_card_clk_period - t_setup)
Values:
■ 0x0 (DISABLE_CMD_CONFLICT_CHK): Disable
command conflict check
■ 0x1 (CMD_CONFLICT_CHK_LAT1): Check for command
conflict after 1 card clock cycle
Value After Reset: 0x1
Exists: (DWC_MSHC_SD_EMMC_SUPPORT==1)

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5.8.4 MBIU_CTRL_R
■ Name: MBIU Control register
■ Description: This register is used to select the valid burst types that the AHB Master bus interface can
generate. When more than one bit is set the master selects the burst it prefers among those that are
enabled in this register.
■ Size: 8 bits
■ Offset: P_VENDOR_SPECIFIC_AREA[11:0] + 0x10
■ Exists: (DWC_MSHC_MST_IF_PRESENT == 1)

7:4
BURST_INCR16_EN 3
2
1
0
UNDEFL_INCR_EN
BURST_INCR8_EN
BURST_INCR4_EN
RSVD

Table 5-153 Fields for Register: MBIU_CTRL_R

Memory
Bits Name Access Description

7:4 RSVD R Reserved field

Value After Reset: 0x0
Exists: Always

3 BURST_INCR16_EN R/W INCR16 Burst

Controls generation of INCR16 transfers on Master
interface.
Values:
■ 0x0 (FALSE): AHB INCR16 burst type is not generated on
Master I/F
■ 0x1 (TRUE): AHB INCR16 burst type can be generated
on Master I/F
Value After Reset: DWC_MSHC_MBIU_BURST16EN
Exists: (DWC_MSHC_MST_IF_PRESENT == 1)

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Table 5-153 Fields for Register: MBIU_CTRL_R (Continued)

Memory
Bits Name Access Description

2 BURST_INCR8_EN R/W INCR8 Burst

Controls generation of INCR8 transfers on Master interface.
Values:
■ 0x0 (FALSE): AHB INCR8 burst type is not generated on
Master I/F
■ 0x1 (TRUE): AHB INCR8 burst type can be generated on
Master I/F
Value After Reset: DWC_MSHC_MBIU_BURST8EN
Exists: (DWC_MSHC_MST_IF_PRESENT == 1)

1 BURST_INCR4_EN R/W INCR4 Burst

Controls generation of INCR4 transfers on Master interface.
Values:
■ 0x0 (FALSE): AHB INCR4 burst type is not generated on
Master I/F
■ 0x1 (TRUE): AHB INCR4 burst type can be generated on
Master I/F
Value After Reset: DWC_MSHC_MBIU_BURST4EN
Exists: (DWC_MSHC_MST_IF_PRESENT == 1)

0 UNDEFL_INCR_EN R/W Undefined INCR Burst

Controls generation of undefined length INCR transfer on
Master interface.
Values:
■ 0x0 (FALSE): Undefined INCR type burst is the least
preferred burst on AHB Master I/F
■ 0x1 (TRUE): Undefined INCR type burst is the most
preferred burst on AHB Master I/F
Value After Reset:
DWC_MSHC_MBIU_UNDEFLBURSTEN
Exists: (DWC_MSHC_MST_IF_PRESENT == 1)

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5.8.5 EMMC_CTRL_R
■ Name: eMMC Control register
■ Description: This register is used to control the eMMC operation.
■ Size: 16 bits
■ Offset: P_VENDOR_SPECIFIC_AREA[11:0] + 0x2c
■ Exists: (DWC_MSHC_SD_EMMC_SUPPORT== 1)

15:11

7:4
CQE_PREFETCH_DISABLE 10
9
8

3
2
DISABLE_DATA_CRC_CHK 1
0
ENH_STROBE_ENABLE

EMMC_RST_N_OE
CQE_ALGO_SEL

CARD_IS_EMMC
EMMC_RST_N
RSVD

Rsvd

Table 5-154 Fields for Register: EMMC_CTRL_R

Memory
Bits Name Access Description

15:11 RSVD R These bits (RSVD) of the EMMC_CTRL_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

10 CQE_PREFETCH_DISABLE R/W Enable or Disable CQE's PREFETCH feature

This field allows Software to disable CQE's data prefetch
feature when set to 1.
Values:
■ 0x0 (PREFETCH_ENABLE): CQE can Prefetch data for
sucessive WRITE transfers and pipeline sucessive READ
transfers
■ 0x1 (PREFETCH_DISABLE): Prefetch for WRITE and
Pipeline for READ are disabled
Value After Reset: 0x0
Exists: (DWC_MSHC_EMMC_CQE_EN == 1)

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Table 5-154 Fields for Register: EMMC_CTRL_R (Continued)

Memory
Bits Name Access Description

9 CQE_ALGO_SEL R/W Scheduler algorithm selected for execution

This bit selects the Algorithm used for selecting one of the
many ready tasks for execution.
Values:
■ 0x0 (PRI_REORDER_PLUS_FCFS): Priority based
reordering with FCFS to resolve equal priority tasks
■ 0x1 (FCFS_ONLY): First come First serve, in the order of
DBR rings
Value After Reset: 0x0
Exists: (DWC_MSHC_EMMC_CQE_EN == 1)

8 ENH_STROBE_ENABLE R/W Enhanced Strobe Enable

This bit instructs DWC_mshc to sample the CMD line using
data strobe for HS400 mode.
Values:
■ 0x1 (ENH_STB_FOR_CMD): CMD line is sampled using
data strobe for HS400 mode
■ 0x0 (NO_STB_FOR_CMD): CMD line is sampled using
cclk_rx for HS400 mode
Value After Reset: 0x0
Exists: (DWC_MSHC_EMMC_DATASTROBE_EN == 1)

7:4 Reserved Field: Yes

3 EMMC_RST_N_OE R/W Output Enable control for EMMC Device Reset signal PAD
control.
This field drived sd_rst_n_oe output of DWC_mshc
Values:
■ 0x1 (ENABLE): sd_rst_n_oe is 1
■ 0x0 (DISABLE): sd_rst_n_oe is 0
Value After Reset: 0x1
Exists: (DWC_MSHC_EMMC_SUPPORT == 1)

2 EMMC_RST_N R/W EMMC Device Reset signal control.

This register field controls the sd_rst_n output of DWC_mshc
Values:
■ 0x1 (RST_DEASSERT): Reset to eMMC device is
deasserted
■ 0x0 (RST_ASSERT): Reset to eMMC device asserted
(active low)
Value After Reset: 0x1
Exists: (DWC_MSHC_EMMC_SUPPORT == 1)

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Table 5-154 Fields for Register: EMMC_CTRL_R (Continued)

Memory
Bits Name Access Description

1 DISABLE_DATA_CRC_CHK R/W Disable Data CRC Check

This bit controls masking of CRC16 error for Card Write in
eMMC mode. This is useful in bus testing (CMD19) for an
eMMC device. In bus testing, an eMMC card does not send
CRC status for a block, which may generate CRC error. This
CRC error can be masked using this bit during bus testing.
Values:
■ 0x1 (DISABLE): DATA CRC check is disabled
■ 0x0 (ENABLE): DATA CRC check is enabled
Value After Reset: 0x0
Exists: (DWC_MSHC_EMMC_SUPPORT == 1)

0 CARD_IS_EMMC R/W eMMC Card present

This bit indicates the type of card connected. An application
program this bit based on the card connected to MSHC.
Values:
■ 0x1 (EMMC_CARD): Card connected to MSHC is an
eMMC card
■ 0x0 (NON_EMMC_CARD): Card connected to MSHC is
a non-eMMC card
Value After Reset: 0x0
Exists: (DWC_MSHC_EMMC_SUPPORT == 1)

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5.8.6 BOOT_CTRL_R
■ Name: eMMC Boot Control register
■ Description: This register is used to control the eMMC Boot operation.
■ Size: 16 bits
■ Offset: P_VENDOR_SPECIFIC_AREA[11:0] + 0x2e
■ Exists: (DWC_MSHC_EMMC_BOOT_EN == 1)

15:12
11:9

6:1
BOOT_ACK_ENABLE 8
7

0
BOOT_TOUT_CNT

VALIDATE_BOOT

MAN_BOOT_EN
RSVD_11_9

RSVD_6_1

Table 5-155 Fields for Register: BOOT_CTRL_R

Memory
Bits Name Access Description

15:12 BOOT_TOUT_CNT R/W Boot Ack Timeout Counter Value.

This value determines the interval by which boot ack timeout
(50 ms) is detected when boot ack is expected during boot
operation.
■ 0xF : Reserved
■ 0xE : TMCLK x 2^27
■ .. - ............
■ 0x1 : TMCLK x 2^14
■ 0x0 : TMCLK x 2^13
Value After Reset: 0x0
Exists: Always

11:9 RSVD_11_9 R These bits (RSVD_11_9) of the BOOT_CTRL_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-155 Fields for Register: BOOT_CTRL_R (Continued)

Memory
Bits Name Access Description

8 BOOT_ACK_ENABLE R/W Boot Acknowledge Enable

When this bit set, DWC_mshc checks for boot acknowledge
start pattern of 0-1-0 during boot operation. This bit is
applicable for both mandatory and alternate boot mode.
Values:
■ 0x1 (TRUE): Boot Ack enable
■ 0x0 (FALSE): Boot Ack disable
Value After Reset: 0x0
Exists: Always

7 VALIDATE_BOOT W Validate Mandatory Boot Enable bit

This bit is used to validate the MAN_BOOT_EN bit.
Values:
■ 0x1 (TRUE): Validate Mandatory boot enable bit
■ 0x0 (FALSE): Ignore Mandatory boot Enable bit
Value After Reset: 0x0
Exists: Always

6:1 RSVD_6_1 R These bits (RSVD _6_1) of the BOOT_CTRL_R register are
reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

0 MAN_BOOT_EN R/W Mandatory Boot Enable

This bit is used to initiate the mandatory boot operation. The
application sets this bit along with VALIDATE_BOOT bit.
Writing 0 is ignored. The DWC_mshc clears this bit after the
boot transfer is completed or terminated.
Values:
■ 0x1 (MAN_BOOT_EN): Mandatory boot enable
■ 0x0 (MAN_BOOT_DIS): Mandatory boot disable
Value After Reset: 0x0
Exists: Always
Testable: readOnly

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5.8.7 GP_IN_R
■ Name: General Purpose Input register
■ Description: This register is used as a general purpose input register. This register stores all the
inputs sampled from input port gp_in.
■ Size: 32 bits
■ Offset: P_VENDOR_SPECIFIC_AREA[11:0] + 0x30
■ Exists: (DWC_MSHC_GPIO_ENABLE == 1)

31:y
GP_IN x:0
RSVD

Table 5-156 Fields for Register: GP_IN_R

Memory
Bits Name Access Description

31:y RSVD R These bits of the GP_IN_R register are reserved. They
always return 0.
Value After Reset: 0x0
Exists: Always
Volatile: true
Range Variable[y]: DWC_MSHC_NUM_GP_IN

x:0 GP_IN R It reflects the value of gp_in ports.

Value After Reset: 0x0
Exists: Always
Volatile: true
Range Variable[x]: DWC_MSHC_NUM_GP_IN - 1

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5.8.8 GP_OUT_R
■ Name: General Purpose Output register
■ Description: This register is used as a general purpose output register. The contents of this register
are reflected on the output port gp_out.
■ Size: 32 bits
■ Offset: P_VENDOR_SPECIFIC_AREA[11:0] + 0x34
■ Exists: (DWC_MSHC_GPIO_ENABLE == 1)

31:y
GP_OUT x:0
RSVD

Table 5-157 Fields for Register: GP_OUT_R

Memory
Bits Name Access Description

31:y RSVD R These bits of the GP_OUT_R register are reserved. They
always return 0.
Value After Reset: 0x0
Exists: Always
Range Variable[y]: DWC_MSHC_NUM_GP_OUT

x:0 GP_OUT R/W The value of this register is reflected on gp_out ports.
Value After Reset: 0x0
Exists: Always
Range Variable[x]: DWC_MSHC_NUM_GP_OUT - 1

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5.8.9 AT_CTRL_R
■ Name: Tuning and Auto-tuning control register
■ Description: This register controls some aspects of tuning and auto-tuning features. Do not program
this register when HOST_CTRL2_R.SAMPLE_CLK_SEL is '1'
■ Size: 32 bits
■ Offset: P_VENDOR_SPECIFIC_AREA[11:0] + 0x40
■ Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!= 2)

23:21
20:19
18:17

15:12
11:8
x:24

7:5
TUNE_CLK_STOP_EN 16

4
3
2
1
0
POST_CHANGE_DLY
PRE_CHANGE_DLY

RPT_TUNE_ERR
WIN_EDGE_SEL
SWIN_TH_VAL

SW_TUNE_EN

SWIN_TH_EN
CI_SEL
RSDV3

RSDV2

AT_EN
Rsvd

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Table 5-158 Fields for Register: AT_CTRL_R

Memory
Bits Name Access Description

x:24 SWIN_TH_VAL R/W Sampling window threshold value setting

The maximum value that can be set here depends on the
length of delayline used for tuning. A delayLine with 128 taps
can use values from 0x0 to 0x7F.
This field is valid only when SWIN_TH_EN is '1'. Should be
programmed only when SAMPLE_CLK_SEL is '0'
■ 0x0 : Threshold values is 0x1, windows of length 1 tap
and above can be selected as sampling window.
■ 0x1 : Threshold values is 0x2, windows of length 2 taps
and above can be selected as sampling window.
■ 0x2 : Threshold values is 0x1, windows of length 3 taps
and above can be selected as sampling window.
■ ........
■ 0x7F : Threshold values is 0x1, windows of length 127
taps and above can be selected as sampling window.
Value After Reset: DWC_MSHC_TUNE_WINTH_VAL
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!= 2)
Range Variable[x]: DWC_MSHC_DL_CW + 23

23:21 Reserved Field: Yes

20:19 POST_CHANGE_DLY R/W Time taken for phase switching and stable clock output.
Specifies the maximum time (in terms of cclk cycles) that the
delay line can take to switch its output phase after a change
in tuning_cclk_sel or autotuning_cclk_sel.
Values:
■ 0x0 (LATENCY_LT_1): Less than 1-cycle latency
■ 0x1 (LATENCY_LT_2): Less than 2-cycle latency
■ 0x2 (LATENCY_LT_3): Less than 3-cycle latency
■ 0x3 (LATENCY_LT_4): Less than 4-cycle latency
Value After Reset: 0x0
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!= 2)

18:17 PRE_CHANGE_DLY R/W Maximum Latency specification between cclk_tx and cclk_rx.
Values:
■ 0x0 (LATENCY_LT_1): Less than 1-cycle latency
■ 0x1 (LATENCY_LT_2): Less than 2-cycle latency
■ 0x2 (LATENCY_LT_3): Less than 3-cycle latency
■ 0x3 (LATENCY_LT_4): Less than 4-cycle latency
Value After Reset: 0x0
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!= 2)

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Table 5-158 Fields for Register: AT_CTRL_R (Continued)

Memory
Bits Name Access Description

16 TUNE_CLK_STOP_EN R/W Clock stopping control for Tuning and auto-tuning circuit.
When enabled, clock gate control output of DWC_mshc
(clk2card_on) is pulled low before changing phase select
codes on tuning_cclk_sel and autotuning_cclk_sel. This
effectively stops the Device/Card clock, cclk_rx and also
drift_cclk_rx. Changing phase code when clocks are stopped
ensures glitch free phase switching. Set this bit to 0 if the
PHY or delayline can guarantee glitch free switching.
Values:
■ 0x1 (ENABLE_CLK_STOPPING): Clocks stopped during
phase code change
■ 0x0 (DISABLE_CLK_STOPPING): Clocks not stopped.
PHY ensures glitch free phase switching.
Value After Reset: 0x0
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!= 2)

15:12 RSDV3 R These bits (RSVD3) of the AT_CTRL_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

11:8 WIN_EDGE_SEL R/W This field sets the phase for Left and Right edges for drift
monitoring. [Left edge offset + Right edge offset] must not be
less than total taps of delayLine.
■ 0x0: User selection disabled. Tuning calculated edges are
used.
■ 0x1: Right edge Phase is center + 2 stages, Left edge
Phase is center - 2 stages.
■ 0x2: Right edge Phase is center + 3 stages, Left edge
Phase is center - 3 stages.
■ ...
■ 0xF: Right edge Phase is center + 16 stages, Left edge
Phase is center - 16 stages.
Value After Reset: 0x0
Exists: (DWC_MSHC_RETUNE_MODE== 1)

7:5 RSDV2 R These bits (RSVD2) of the AT_CTRL_R register are

reserved. They always return 0.
Value After Reset: 0x0
Exists: Always

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Table 5-158 Fields for Register: AT_CTRL_R (Continued)

Memory
Bits Name Access Description

4 SW_TUNE_EN R/W This fields enables software-managed tuning flow.

Values:
■ 0x1 (SW_TUNING_ENABLE): Software-managed tuning
enabled. AT_STAT_R.CENTER_PH_CODE Field is now
writable.
■ 0x0 (SW_TUNING_DISABLE): Software-managed tuning
disabled.
Value After Reset: 0x0
Exists: Always

3 RPT_TUNE_ERR R/W Framing errors are not generated when executing tuning.
This debug bit allows users to report these errors.
Values:
■ 0x1 (DEBUG_ERRORS): Debug mode for reporting
framing errors
■ 0x0 (ERRORS_DISABLED): Default mode where as per
SD-HCI no errors are reported.
Value After Reset: 0x0
Exists: Always

2 SWIN_TH_EN R/W Sampling window Threshold enable

Selects the tuning mode
Field should be programmed only when SAMPLE_CLK_SEL
is '0'
Values:
■ 0x1 (THRESHOLD_MODE): Tuning engine selects the
first complete sampling window that meets the threshold
set by SWIN_TH_VAL field
■ 0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all
taps and settles at the largest window
Value After Reset: DWC_MSHC_TUNE_WINTH_EN
Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!= 2)

1 CI_SEL R/W Selects the interval when the corrected center phase select
code can be driven on tuning_cclk_sel output.
Values:
■ 0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval
■ 0x1 (WHEN_IN_IDLE): Driven at the end of the transfer
Value After Reset: 0x0
Exists: (DWC_MSHC_RETUNE_MODE== 1)

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Table 5-158 Fields for Register: AT_CTRL_R (Continued)

Memory
Bits Name Access Description

0 AT_EN R/W Setting this bit enables Auto tuning engine. This bit is
enabled by default when core is configured with mode3
retuning support. Clear this bit to 0 when core is configured
to have Mode3 re-tuning but SW wishes to disable mode3 re-
tuning.
This field should be programmed only when
CLK_CTRL_R.SD_CLK_EN is 0.
Values:
■ 0x1 (AT_ENABLE): AutoTuning is enabled
■ 0x0 (AT_DISABLE): AutoTuning is disabled
Value After Reset: DWC_MSHC_RETUNE_MODE
Exists: (DWC_MSHC_RETUNE_MODE== 1)

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5.8.10 AT_STAT_R
■ Name: Tuning and Auto-tuning status register
■ Description: Register to read the Center, Left and Right codes used by tuning and auto-tuning
engines. Center code field is also used for software managed tuning.
■ Size: 32 bits
■ Offset: P_VENDOR_SPECIFIC_AREA[11:0] + 0x44
■ Exists: (DWC_MSHC_CARD_INTERFACE_TYPE!= 2)

31:24
L_EDGE_PH_CODE 23:16
R_EDGE_PH_CODE 15:8
CENTER_PH_CODE 7:0
RSDV1

Table 5-159 Fields for Register: AT_STAT_R

Memory
Bits Name Access Description

31:24 RSDV1 R These bits of the AT_STAT_R register are reserved. They
always return 0.
Value After Reset: 0x0
Exists: Always

23:16 L_EDGE_PH_CODE R Left Edge Phase code. Reading this field returns the phase
code value used by Auto-tuning engine to sample data on
Left edge of sampling window.
Value After Reset: 0x0
Exists: Always

15:8 R_EDGE_PH_CODE R Right Edge Phase code. Reading this field returns the phase
code value used by Auto-tuning engine to sample data on
Right edge of sampling window.
Value After Reset: 0x0
Exists: Always

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Table 5-159 Fields for Register: AT_STAT_R (Continued)

Memory
Bits Name Access Description

7:0 CENTER_PH_CODE R/W Centered Phase code. Reading this field returns the current
value on tuning_cclk_sel output. Setting
AT_CTRL_R.SW_TUNE_EN enables software to write to
this field and its contents are reflected on tuning_cclk_sel.
Value After Reset: DWC_MSHC_DEF_DL_CODE
Exists: Always
Testable: readOnly

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A
Protocol Overview

This appendix provides an overview of protocols that are supported in the SD and UHS-II mode of
operations in DWC_mshc. Additionally, this appendix provides information about important concepts of
the standard applicable to DWC_mshc. For detailed information about the protocols, refer to the applicable
standard documents. For a list of standards and specifications supported by DWC_mshc, see “Standards
Compliance” on page 25.
This appendix contains the following sections:
■ “Signals Between Host and Device” on page 564
■ “Bus Topology” on page 565
■ “Bus Protocol” on page 567
■ “Range Definition” on page 574
■ “Transaction Layer” on page 574
■ “Control and Data Transaction Sequence” on page 578
■ “UHS-II Interface Selection Process” on page 579
■ “Application Layer Data Flow” on page 580
■ “SDIO Read Wait” on page 592
■ “SDIO Card Interrupt” on page 592

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A.1 Signals Between Host and Device

In an SD/eMMC system, Figure A-1 summarizes the signals that connect the host controller and the device
card.

Table A-1 Bus Type and Signals Between a Host and a Device

Bus Type Signals

SD ■ CLK – Host to card clock signal

■ CMD – Bidirectional Command/Response signal
■ DAT0-DAT3 – 4 Bidirectional data signals
■ VDD, VSS1 – Power and Ground signals

UHS-II ■ RCLK – Reference clock from Host to Device (Differential output)

■ DO – Downstream data lane from Host to device for command, data/other packets
(Differential output)
■ D1 – Upstream data lane from Host to device for response, data/other packets
(Differential output)
■ VDD, VSS1 – Power and Ground signals

eMMC ■ CLK – Host to card clock signal

■ CMD – Bidirectional Command/Response signal
■ DAT0 to DAT8 – 8 Bidirectional data signals
- DS – Data Strobe signal
■ VDD and VSS1 – Power and Ground signals

The number of data lines can be dynamically configured in the SD bus. Power up by default is
Note only through DAT0 lines, but after power up, the host can change the bus width (number of
active lines) based on system performance requirements.

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A.2 Bus Topology

DWC_mshc supports only synchronous point to point topology for SD, eMMC and UHS-II cards. However,
UHS-II cards also support Ring and Hub topologies. The host controller can be connected to device (s) in
various connectivity modes known as a topology.
Table A-2 lists the bus topologies.

The term “Master” is interchangeably used with the term “Host”. Similarly, the term “Slave” is
Note used interchangeably with “Device”. Both these terms are consistent with the relevant
standards.

Table A-2 Types of Bus Topologies

Card Type Master Slave Topology

SD, eMMC, and UHS-II Singe Single Synchronous point to point

UHS-II Single Multiple Ring/hub

Figure A-1, Figure A-2, and Figure A-3 how the bus topologies in SD and UHS-II modes.

Figure A-1 Synchronous Point-to-Point Topology

CLK

VDD
VSS SD/eMMC
Host
Card

DO-D3, CMD(1)

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Figure A-2 UHS-II Ring Topology

Host

SD Interface

UHS-II
Interface
Ring

Device-1 Device-2 Removable

ID = 1 ID = 2 ID = 3

Figure A-3 UHS-II Hub Topology

Host

UHS-II Interface Ring HUB

SD
Interface

Device-1 Device-2 Removable

ID = 1 ID = 2 ID = 3

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A.3 Bus Protocol

This section discusses the bus protocol for SD, UHS-II and eMMC modes. It discusses the following
sections:
■ “SD Bus Protocol” on page 567
■ “UHS-II Bus Protocol” on page 567
■ “eMMC Bus Protocol” on page 573

A.3.1 SD Bus Protocol

The bus communication in SD mode is based on command and data bit streams each bounded by a start bit
and a stop bit. A command is a token that starts an operation and is sent by the Host to the card(s). The
command is transferred through the CMD line. Response is a token that is sent by the addressed card (s) to
the host as a reply to the previous command. The response is also transferred serially through the CMD line.
Data can be set either by the Host (Write operation) or by the card (Read operation) and can be transferred
through the data lines.
Data transfers in either direction are done in blocks. Each block has a CRC succeeding it. The transfers can
either happen as a single or multiple block. Multiple block transmissions are terminated by the issue of a
stop command on the command line.
Figure A-4 shows the command and data bit streams in the SD mode.

Figure A-4 SD Mode of Operation

Host to Card to Data from Card

Host to Host Stop CMD
Card

CMD cmd resp cmd resp

DAT data block 1 CRC data block 2 CRC data block 3 CRC

Block Read Data Stop

Multiple Block Read

A.3.2 UHS-II Bus Protocol

The UHS-II mode of operation was introduced in the SD standard in May 2011 through an addendum to the
specification to accomplish the Ultra-high-speed (UHS) requirement to handle HD contents. The main
features of the UHS-II mode are.
■ Interface speed
❑ Interface speed that various continuously
❑ Full Duplex mode (FD) with data rates from 39 MBps to 156 MBps

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❑ Half duplex mode (2L-HD) with data rates from 78 MBps to 312 MBps
❑ Provision for additional lanes for future expansion
■ Layered architecture
This section discusses the following topics:
■ “UHS-II Architecture” on page 568
■ “UHS-II Packets” on page 569
■ “UHS-II CCMD Packet Format” on page 570
■ “UHS-II DCMD Packet Format” on page 571
■ “UHS-II RES Packet Format” on page 572
■ “UHS-II DATA Packet Format” on page 572

A.3.2.1 UHS-II Architecture

The UHS-II follows a layered architecture with various layers. Table A-3 defines these layers with their
respective layer acronyms.
Table A-3 Layers in the UHS-II Mode

Layer Acronym Layer Name Function

None Mechanical Describes mechanical specification, such as card form factor, connector
pins.

PHY Physical Denotes electrical specifications, such as voltage levels (signaling), symbol
encoding/decoding.

LINK Link Responsible for link management functions, such as PHY initialization, data
integrity, power management, flow control

TRANS Transaction Protocol management that includes packet generation and analysis,
command-response handshake.

Figure A-5 depicts the layered architecture for UHS-II.

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Figure A-5 UHS-II Layered Architecture

Transaction
Application-Specific SD-TRAN
Layer

CM-TRAN
Link

Link Managament Link Flow Control

Power
Management
Physical

PHY

Mechanical

A.3.2.2 UHS-II Packets

Table A-4 lists different types of UHS-II packets defined at the transaction layer.

Table A-4 Types of UHS-II Packets

Acronym for
Packet Type Packet Type Description Initiator

CCMD Control Command Command without data. Host

Packet Following are different categories of CCMD:
■ P2P CCMD
■ Broadcast CCMD

DCMD Data Command Command accompanied with Data Host

Packet

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Table A-4 Types of UHS-II Packets

Acronym for
Packet Type Packet Type Description Initiator

RES Response Packet Response returned by Device to Host after Device

receiving DCMD or CCMD

DATA Data Packet Data payload between Host and device Host for Write,
Device for Read

MSG Message Packet Short information. Generated / analyzed in LINK Host/Device

Figure A-6 depicts the packet formats for each type of packet listed in Figure A-4.

Figure A-6 Packet Formats

Argument
Payload
CCMD Header (When Write CCMD)
R/W PLEN I/O ADDR

Argument Extended Argument

DCMD Header
R/W TMODE RSVD Data ADDR TLEN

Argument
RES Payload
Header (When Read CCMD)
NACK CMD_ECHO_BACK

DATA Header Payload

A.3.2.3 UHS-II CCMD Packet Format

Figure A-7 shows the detailed packet format for a CCMD packet.

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Figure A-7 CCMD Packet

BIT
7 6 5 4 3 2 1 0
BYTE

0 Header
(NP =1, Pkt type = CCMD)
1
2 R/W RSVD PLEN I/O ADDR (MSB)

3 I/O ADDR (LSB)

[4
Payload
...
]

A.3.2.4 UHS-II DCMD Packet Format

Figure A-8 shows the detailed packet format for a DCMD packet.

Figure A-8 Data Command Packet Format

BIT
7 6 5 4 3 2 1 0
BYTE

0 Header
(NP =1, Pkt type = DCMD)
1
2 R/W TMODE RSVD
Argumen
t
3 RSVD

(MSB)

[4..7] DADR

(LSB) Extended
Argumen
(MSB) t

[TLEN]
[8..11]

(LSB)

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A.3.2.5 UHS-II RES Packet Format

Figure A-9 shows the detailed packet format for a RES packet.

Figure A-9 Response Packet Format

BIT
7 6 5 4 3 2 1 0
BYTE

0 Header
(NP =1, Pkt type = RES)
1
NACK=0
2 Argumen
CMD_ECHO_BACK
t
3
(MSB)

Payload
[4..] Payload

(LSB)

A.3.2.6 UHS-II DATA Packet Format

Figure A-10 shows the detailed packet format for a DATA packet.

Figure A-10 UHS-II DATA Packet Format

BIT
7 6 5 4 3 2 1 0
BYTE

0 Header
(NP =1, Pkt Type = DATA)
1
[2 (MSB)

..
Block Length + 1 Payload Payload

or

TLEN + 1]
(LSB)

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A.3.2.7 Lane Definition

In UHS-II mode, the signals between the Host and the device are referred as Lanes. Table A-5 summarizes
information about these Lanes.

Table A-5 Lane Types

Lanes Description Usage in FD Mode Usage in HD Mode

DO high-speed data Used for downstream (from Host to In 2L-high-speed mode, can be
lane Device). Normally, WRITE Data and used upstream as well (Device to
(390Mbps to Command are transferred from Host Host)
1.56Gbps) to device.

D1 high-speed data Used for upstream (from Device to In 2L-high-speed mode, can be
lane Host). Normally, READ Data and used downstream as well (Host to
(390Mbps to response are transferred from Device Device)
1.56Gbps) to Host.

RCLK Reference clock Stable reference clock from Host to Same as in FD mode.
lane Device.
(26MHz to 52MHz)

A.3.3 eMMC Bus Protocol

An eMMC bus data transfer contains a command, response and data block tokens. Each data transfer is
considered as a bus operation that always contains a command and a response token. Additionally, certain
bus operations also contain a data token. Data sent on the data line can be transferred one bit (single data
rate) or two bits (dual data rate) per clock cycle. Similar to the SD bus protocol, command and data bit
streams are bound by a start bit and a stop bit. Data transfer occurs in the form of blocks that are followed
by CRC bits and data is transferred in single or multiple blocks. While a single/multiple read block is
terminated by a stop command on the CMD line, a single/multiple write block is terminated by a busy
signal on the data (DAT[0]) line.

Figure A-11 eMMC Block Read Operation

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Figure A-12 eMMC Block Write Operation

Device addressing is implemented using a session address, assigned during the initialization phase, by the
bus controller to the connected device. A device is identified by its CID number. This method requires the
device to have a unique CID number. To ensure uniqueness of CIDs, the CID register contains 24 bits (MID
and OID fields) that are defined by JEDEC/MMCA. Every device manufacturer is required to apply for an
unique MID (and optionally OID) number.

A.4 Range Definition

To facilitate the Phase Locked Loop (PLL) design, the data rates that are in the range of 390 MBps to
1.56 GBps are divided into two ranges as shown in Table A-6.
Table A-6 Division of Data Rates into Two Ranges

Range RCLK Data Range Ratio (Data Rate/ RCLK)

A 26 MHz to 52 MHz 390 Mbps to 780 Mbps X15

B 26 MHz to 52 MHz 780 Mbps to 1.56 Gbps X30

Initialization of UHS-II interface is always done in Range A and device PLL acquisition time is specified
with a maximum value of 2 ms.

A.5 Transaction Layer

The transaction layer handles packet format, configuration, state machine, initialization and flow control.
Figure A-13 depicts the substructure within the transaction layer.

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Figure A-13 UHS-II Transaction Layer Structure

Application-Specific
SD CMD/RES/DAT

SD-Tran
SD Card Register
Layer
SD State Machine
Protocol Bridge (SD <-->CM)
Transaction

Transaction CMD Queuing

Enumeration Relaxed Ordering

Tran
CM-Tran

Management Configuration ID-Based Mux/Demux

Common Packets
(DCMD, CCMD, RES, DATA)

The UHS-II transaction layer is split into two sub-layers:

■ Common layer (CM-TRAN)
■ Application-specific layer (SD-TRAN for UHS-II)
The CM-TRAN specifies the common protocol suitable for UHS-II PHY and LINK. The CM-TRAN is also
intended to be common between the Host and device. CM-TRAN generates UHS-II packets and transmits
according to the UHS-II I/O register, which is accessed by the application driver (Host or Backend
(Device)). CM-TRAN also analyses the received packets.
Figure A-14 show the function of the CM-TRAN.

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Figure A-14 CM-TRAN Functionality

Host
Application Driver

UHS-II I/O register

CM-TRAN CM-Tran

LINK
PHY

UHS-II Pkts
Device
PHY
LINK

UHS-II I/O register

CM-TRAN CM-Tran

Backend (Flash memory)

The SD-TRAN is used to bridge the CM-TRAN with legacy SD IPs or software. SD-TRAN analyses the
Host/device register and sets UHS-II I/O registers. When SD-TRAN is used, the CM-TRAN encapsulates
the legacy SD command/response/data and generate the UHS-II packet, on the transmit side and analyze
the received packet and notify SD-TRAN, on the receiving side.

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Figure A-15 shows the function of the SD-TRAN.

Figure A-15 SD-TRAN Functionality

Host

Application Driver

SD Host Register
CM-TRAN SD-Tran

UHS-II I/O register

CM-TRAN CM-Tran

LINK
PHY

Encapsulated
UHS-II Pkts
UHS-II Device
PHY
LINK

UHS-II CM-TRAN
I/O register CM-Tran

SD Card register
CM-TRAN SD-Tran

Backend (Flash memory)

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A.6 Control and Data Transaction Sequence

A control transaction consists of a CCMD (from Host) followed by an RESP (from Device) (applies to non-broadcast mode). It is typically performed
to access the UHS-II I/O registers (configuration, command).
A Data transaction consists of DCMD (Host) followed by RESP (from Device) and then DATA (from Host or Device). It is performed for transferring
data. Figure A-16 depicts this flow sequence.

Figure A-16 Control and Data Transactions

CCMD CCMD DCMD DCMD

DO (WR) (RD) (WR)
DATA
(RD) DO

D
E
V
Host I
C
E

DAT
D1 RES RES RES RES
A D1

Ctrl Trans(WR) Ctrl Trans(RD) DATA Trans(WR) DATA Trans(RD)

Time

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A.7 UHS-II Interface Selection Process

A host controller that supports a UHS-II interface also supports an SD interface. The removable UHS-II card
is connected to both interfaces (UHS-II and SD). The host tries to initialize in UHS-II mode first and if it does
not happen with a timeout period (200us), the host falls back to the SD mode initialization sequence.

Figure A-17 Process to Select a UHS-II Interface

VDD1

VDD2

RCLK
UHS-II
UHS-II Card
Host
D0 = STB.L

D1

EIDL to STB.L

Power Up;
Supply VDD1, VDD2

Host to supply RCLK;

Set STB.L on D0

Timeout =
200us Wait for D1 = D1 = STB.L
STB.L

SD I/F Init UHS-II Initialisation

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A.8 Application Layer Data Flow

The host controller communicates to the software driver using the system bus interface and to the card
using the SD Bus interface. Figure A-18 depicts the high level data flow through the Host controller.

Figure A-18 Host Controller Data Flow

Application Bus

DMA Interface

Registers Buffers

CMD Control DATA Control

CMD DAT [3:0]

SD Bus I/F

The host driver can transfer data using either a programmed I/O method or using any of the defined DMA
methods. In the Programmed Input/Output (PIO) method of data transfer, data is transferred to the system
memory by the host driver. It is done either on the basis of block (SD/eMMC) or bursts (UHS-II). In a card
write, the controller provides Buffer Write ready interrupt when it has space for one block. Based on this
interrupt, the host driver must transfer one block of data from system memory to the DWC_mshc buffer
through the Buffer data port. After that block is sent to card by controller, the same mechanism is used in
the reverse direction in the case of card read using the Buffer read ready interrupt. PIO mode is much
slower and burdens the processor. It is recommended not to use the PIO mode for large transfers.
Following are different DMA methods described in SD standards:
■ Single operation DMA (SDMA)
■ Advanced DMA-2 (ADMA2)
■ Advanced DMA-3 (ADMA3)
The capabilities register defined by the standard provides the information of type of DMA support
provided by the particular controller.
DMA supports both single block and multi-block transfers. The control bits in the Block Gap Control
register is used to Stop and Restart a DMA operation. SDMA mode is used for short data transfer as it
generates interrupts at page boundaries. ADMA2 and ADMA3 are used for long data transfers and use
scatter-gather algorithms. ADMA2 supports single READ/WRITE SD operation at a time while ADMA3
supports multiple READ/WRITE SD operation at a time.

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SD mode command generation is done by writing into the following registers:

■ System address
■ Block Size
■ Block count
■ Transfer mode
■ Command
UHS-II mode command packets are generated by writing into the CCMD and DCMD registers.

A.8.1 ADMA2 Operation

Figure A-19 shows the ADMA2 data transfer between the host controller and the system memory and it
shows the descriptor table that is created by the host driver. A 32-bit address descriptor table is used for a
system with 32-bit addressing and a 64-bit address descriptor table is used for a system with 64-bit
addressing. In the descriptor table, each line contains information about the address, its length and an
attributes that specifies the operation of the descriptor line. ADMA2 uses the 64-bit ADMA address register
for the descriptor pointer. An ADMA2 transfer is triggered by writing to the command register and
ADMA2 processes each line in the descriptor table.

Figure A-19 ADMA2 Block Diagram

System Memory
Advanced DMA
Descriptor Table
Descriptor Pointer Address Length Attributes
System Address Register
Address 1 Length 1 Tran
Address 2 Length 2 Tran
Data Length(internal)
Address - Link

Data Address (internal) Address Length Attributes

Address 3 Length 3 Tran
DMA Interrupt Address 4 Length 4 Tran, End
Flags
SDMA ADMA Error
State
Machine Transfer Complete
Data 4

Data 3
(Used as a descriptor pointer) Data 2

Data 1

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The descriptor table is created in the system memory by the Host driver. ADMA2 fetches one descriptor line
and executes it until the end of descriptor denoted by (End = 1 in attribute) is found.
Figure A-20 shows the ADMA2 descriptor format.

Figure A-20 ADMA2 Descriptor Table

128-bit ADMA2 Descriptor Line (64-bit Addressing Mode)

Reserved 64-Bit Address 16-Bit Length 10-Bit Length Attribute

127 96 95 32 31 16 15 06 05 04 03 02 01 00
0000_0000h xxxx_xxxx_xxxx_xxxxh xxxxh xxxxxxxxxxb Act2 Act1 Act0 Int End Valid

64-bit ADMA2 Descriptor Line (32-bit Addressing Mode)

32-Bit Address 16-Bit Length 10-Bit Length Attribute

63 32 31 16 15 06 05 04 03 02 01 00
xxxx_xxxxh xxxxh xxxxxxxxxxb Act2 Act1 Act0 Int End Valid
Lower Upper

Data Length is extended from Version 4.10 Valid Indicates Validity of a Descriptor Line
(1) 16-bit Data Length Mode End End of Descriptor
(2) 26-bit Data Length Mode
Int Force to generate ADMA Interrupt

Act2 Act1 Act0 Symbol Comment Operation

0 0 0 Nop No Operation Do not execute current line and go to next line
0 1 0 rsv Reserved Same as Nop. Do not execute current line and go to next line
1 0 0 Tran Transfer Data Transfer data of one descriptor line
1 1 0 Link Link Descriptor Link to another descriptor

All other combinations No Operation Same as Nop.

A.8.2 ADMA3 Operation

ADMA3 can be considered as multiple ADMA2 operations. This is achieved by using an integrated
descriptor structure which in turn consists of a pair of Command Descriptor and ADMA2 descriptor. This
pair is programmed for a multi-block data transfer from the system memory to the SD card. In ADMA2, the
host driver issues an SD command using the Host Control registers, whereas ADMA3 uses the Command
Descriptors to issue an SD command. The different command descriptor types available in DWC_mshc are
SD and UHS-II command descriptor types.
Figure A-20 shows a sample ADMA3 data transfer to write three data blocks (Data A, Data B, and Data C) to
different areas of an SD card.

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Figure A-21 ADMA3 Block Diagram

Descriptor Pair
Command Descriptor + ADMA2 Descriptor SD Memory Card
System Memory (Logical) Memory Allocation

Command Host Controller ADMA3

ADMA2
Data A
Command
ADMA2 Used Area

Command
Data B
ADMA2 ADMA3 Engine

Used Area
Data A
Data B

Data C ADMA3 Integrated

Descriptor Address

Data C

Data is scattered
physically by paging. If some data is pre-recorded,
ADMA2 descriptor data will be written by dividing
gathers scattered data into smaller data (Data A, B
and data is logically and C). A write command is
Integrated Descriptor seen continous. issued every time when data
List of Pointers to Command address is leaped by using
Descriptors. Command Descriptor.

Figure A-20 shows that the first integrated descriptor pair is programmed to transfer Data A from the
system memory to the SD memory card. Similarly, the second pair is programmed to transfer Data B, and
the third pair is programmed to transfer Data C. After processing all descriptors pointed by the integrated
descriptors are completed, ADMA3 generates the Transfer Complete interrupt to indicate completion of
data transfer to the host driver.
Figure A-22 shows the ADMA3 command descriptor format, which can be of type SD or UHS-II and the
type is identified by the Attribute. If the attribute indicates a command descriptor for SD mode, 32-bit
register fields are written to the host controller registers from 000h to 00Fh. An SD command is issued when
00Fh is written. If the attribute indicates command descriptor for UHS-II mode, 32-bit register fields are
written to host controller registers from 080h to 09Fh. A UHS-II command packet is issued, when 09Fh is
written.

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The host controller register contains a pointer to a descriptor line for the command descriptor and ADMA2
descriptor. This pointer is incremented after reading each descriptor line. When the last line in the
command descriptor is read, the pointer points to the top of the ADMA2 descriptor, which is placed after
the command descriptor.

Figure A-22 ADMA3 Command Descriptor Format

Command Descriptor (for 32-bit/64-bit Addressing Mode)

32-bit Register Reserved Reserved Attribute
63 32 31 16 15 06 05 04 03 02 01 00
xxxx_xxxxh 0000h 000000b Act2 Act1 Act0 Int End Valid

32-bit register fields are written to the Host Control

Registers from 000h to 00Fh to issue an SD command.
(1) Command Descriptor for SD Mode

32-Bit Address Reserved Attribute

32-bit Block Count All 0 001001b Set to 003h – 000h
(16-bit Block Count) + Block Size All 0 001001b Set to 007h – 004h
Argument All 0 001001b Set to 00Bh – 008h
Command + Transfer Mode All 0 001011b Set to 00Fh – 00Ch

32-bit register fields are written to the Host Control Registers

from 080h to 09Fh to issue a UHS-II Command Packet.

(2) Command Descriptor for UHS-II Mode

32-Bit Address Reserved Attribute

0000h + UHS-II Block Size All 0 011001b Set to 083h – 080h
UHS-II Block Count All 0 011001b Set to 087h – 084h
UHS-II Command Packet (5 lines) All 0 011001b Set to 09Bh – 088h
UHS-II Command + UHS-II Transfer Mode All 0 011011b Set to 09Fh – 09Ch

Figure A-22 shows the ADMA3 integrated descriptor format. Each row in the integrated descriptor table.
The 64-bit address pointer is set to 95-32 in the 128-bit integrated descriptor. The pointer of 32-bit address is
set to bit 63-32 in the 64-bit Integrated Descriptor and the controller ignores “Int” of attribute in this
descriptor.

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Figure A-23 ADMA3 Integrated Descriptor Format

128-bit Integrated Descriptor (64 -bit Addressing)

64-bit Pointer 64-bit Pointer Reserved Reserved Attribute
127 96 95 32 31 16 15 06 05 04 03 02 01 00
0000_0000h xxxx_xxxx_xxxx_xxxxh 0000h 000000b Act2 Act1 Act0 Int End Valid

64-bit Integrated Descriptor (32 -bit Addressing)

32-bit Pointer Reserved Reserved Attribute
63 32 31 16 15 06 05 04 03 02 01 00
xxxx_xxxxh 0000h 000000b Act2 Act1 Act0 Int End Valid

Descriptor Pairs
Command Descriptor 1
Integrated Descriptor

ADMA Descriptor 1 Pointer Field Reserved Attribute

Pointer to Command Descriptor 1 All 0 111001b
Pointer to Command Descriptor 2 All 0 111001b
Command Descriptor 2
ꞣ
ADMA Descriptor 2
Pointer to Command Descriptor n All 0 111011b

Command Descriptor n End = 1 indicates the last line

ADMA Descriptor n

For more information about these descriptor formats, see SD Specifications Part A2 SD Host Controller
Standard Specification Version 4.10, Sep 2013.

A.8.3 Command Queueing Task Descriptor

The Command Queueing Engine (CQE) denotes the hardware unit executing the Command Queueing (CQ)
activities. The CEQ manages the interface between the host software and the eMMC device, and the data
transfers. CQE receives tasks from the software though a Task Descriptor List (TDL) in the host memory
and the doorbell register. The CQE issues CQ commands, CMD44 and CMD45, to the eMMC device and
also stores the task information. CQE also reads the queue status register of the device and decides the task
to execute, and issues the EXECUTE commands.
To implement queuing of tasks in the eMMC device, the host asynchronously issues tasks using the TDL,
which is located in a memory location known to the CQE, and contains up to 32 fixed-size slots. Each slot
contains one Task Descriptor and one Transfer Descriptor. To issue a task, the software selects an available
TDL slot and constructs the following two descriptors in it:
■ Task Descriptor – This encodes all information that defines the Task. For instance, the Address, Block
Count, and Priority. This information is later passed to the device. The Task Descriptor can
alternatively encode any arbitrary command that is sent directly to the device.

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■ Transfer Descriptor – This points either to one continuous data buffer to/from which data is
transferred (TRAN Descriptor) or to a scatter/gather list of any length (LINK Descriptor).
Figure A-24 shows the structure of the TDL in the host memory and the slot numbers in the TDL. The slot
numbers in Figure A-24 store the following information:
0 – Stores a Data Transfer Task with a TRAN descriptor.
1 – Stores a Data Transfer Task with a LINK descriptor, pointing to a scatter/gather list.
31 – Stores a DCMD descriptor.

Figure A-24 Command Queuing Host Controller Interface (HCI) Structure

A.8.4 eMMC Data Structures

This section describes the descriptor structures used in eMMC Command Queuing. As mentioned in
“Command Queueing Task Descriptor” on page 585, the host writes a pair of descriptors namely Task
Descriptor and Transfer Descriptor, which are organized in the host memory in the Task Descriptor List.
This section discusses the following structures:
■ “Task Descriptor Structure” on page 586
■ “Transfer Descriptor Structure” on page 589
■ “Task Descriptor for Direct-Command (DCMD) Tasks” on page 590

A.8.4.1 Task Descriptor Structure

Table A-7 and Table A-8 summarize the Task Descriptor structure for lower and upper 64 bits, and
Table A-9 describes task descriptor fields.

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Table A-7 Task Descriptor Structure; Lower 64 bits (Data Transfer tasks)

Block Block
Address Count Task Parameters Field Attribute

63:32 31:16 15 14 13 12 11 10:7 6 5:3 2 1 0

xxxx_xxxxh xxxxh Reliable QBR Priority Data Tag Context Forced Act=101 Int End= Valid
Write Direction request progra 1 =1
mming

Table A-8 Task Descriptor Structure Upper 64 bits

Crypto Data Unit

Vendor Specific Crypto Parameters Field Number

127:112 111 110:106 105:104 103:96 96:64

Implementation Specific CE 00000 Transaction Crypto Cfg Index X

Type (CCI)

Table A-9 Task Descriptor Fields

Field Bit Encoded in

Name Location Description CMD

Valid 0 1 – The descriptor is effective and must be processed by hardware.

0 – The descriptor line must not be used.

End 1 Must always be set to 1. Every Task Descriptor is standalone.

Int 2 Indicates the interrupt generation policy required for this task.
1 – Hardware generates an interrupt upon the task completion.
0 – Hardware counts task completion for interrupt coalescing.

Act 5:3 Must be set to b101 to indicate that this is a Task Descriptor.

Forced 6 If 1, FP is enabled. Data is forcefully programmed to a non-volatile CMD44

Programmi storage instead of volatile cache while cache is turned ON.
ng (FP)

Context ID 10:7 A context is an active session, configured for a specific read/write CMD44
pattern. A device may support one or more concurrent contexts,
defined by a Context ID. Each context ID (besides #0) has a
configuration field in EXT_CSD to control its behavior.

Tag 11 Indicates request to receive information (about specific data types) CMD44
Request from the host.

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Table A-9 Task Descriptor Fields

Field Bit Encoded in

Name Location Description CMD

Data 12 Indicates the direction of data transfer. CMD44

Direction 1 – Device to Host (Read)
0 – Host to Device (Write)

Priority 13 1 – high CMD44

0 – simple

Queue 14 Indicates the control of the host on the ordering between tasks.
Barrier
(QBR)

Reliable 15 Indicates multiple block write with pre-defined block count and Reliable CMD44
Write Write parameters.

Block 31:16 Number of blocks to be read/written. CMD44

Count

Block 63:32 Data block address CMD45

Address

Data Unit 95:64 A 32-bit cryptographic parameter which is used by some algorithms for N/A
Number key generation (see section B.9 for details)
(DUN) NOTE: This field is valid only in controllers supporting cryptographic
operations (CQCAP.CS=1). If CQCAP.CS=0, this field is reserved.

Crypto 103:96 The index of CRYPTOCFG to be used with this transaction. The values N/A
Configurati allowed are between 0 and CRCAP.CFGC
on Index When TD.CE is 0, this field is reserved.
(CCI) NOTE: This field is valid only in controllers supporting cryptographic
operations (CQCAP.CS=1). If CQCAP.CS=0, this field is reserved.

Transaction 105:104 Transaction Type (TT) CMD44

Type Field value description:
00b - Simple Data Task
01b - Data Task w/ Immediate Partition Access
10b - Device Management Sequence (DMS)
11b - reserved
NOTE: When 64 b descriptors are used, the implied value of this field is
0b

Reserved 110:106 N/A

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Table A-9 Task Descriptor Fields

Field Bit Encoded in

Name Location Description CMD

Crypto 111 1= Enable cryptographic operations for this task. Payload is decrypted N/A
Enable in Read tasts(DD=1). Payload is encrypted in Write tasks (DD=0).
(CE) Host controller takes no action for all other tasks.
0=Disable cryptographic operations for this task.
NOTE: When 64b descriptors are used, the implied value of this field is
0.
NOTE: This field is valid only in controllers supporting cryptographic
operations (CQCAP.CS=1). If CQCAP.CS=0, this field is reserved.

Reserved 127:112 N/A

A.8.4.2 Transfer Descriptor Structure

Table A-10 and summarize the Transfer Descriptor structure for 32-bit and 64-bit addressing. Table A-12
describes transfer descriptor fields.

Table A-10 Transfer Descriptor Structure (32-Bit Addressing)

Address Length Reserved Attribute

63:32 31:16 15 16 5:3 2 1 0

xxxx_xxxxh xxxxh 0000000000 Act Int End Valid

Table A-11 Transfer Descriptor Structure (64-Bit Addressing)

Reserved Address Length Reserved Attribute

127:96 95:32 31:16 15 16 5:3 2 1 0

0 xxxx_xxxxh xxxxh 0000000000 Act Int End Valid

Table A-12 Transfer Descriptor Fields

Bit
Field Name Location Description

Valid 0 1 – The descriptor is effective and must be processed by hardware.

0 – The descriptor line must not be used.

End 1 1 – The descriptor is the last descriptor in a descriptor list.

0 – Additional descriptors follow this descriptor.
In the case of a TRAN descriptor, the value of this bit is 1.

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Table A-12 Transfer Descriptor Fields

Bit
Field Name Location Description

Int 2 The value of this bit is set to 0 in command queuing.

Act 5:3 100: TRAN – Address field of descriptor points to a data buffer.
110: LINK – Address field of descriptor points to a another descriptor.
000: NOP – no operation.
Others: Reserved

Reserved 15:6 Reserved

Length 31:16 Length of data buffer in bytes. A value of 0000 means 64 KB.

Address (32- 63:32 Data buffer address in host memory, in 32-bit addressing mode.
bit) Address must be set on 32-bit boundary (Lower 2 bits set to 0)

Address (64- 95:32 Data buffer address in host memory, in 64-bit addressing mode.
bit) Address must be set on 64-bit boundary (Lower 3 bits set to 0)

Reserved 127:96 Reserved (64-bit addressing mode only).

A.8.4.3 Task Descriptor for Direct-Command (DCMD) Tasks

summarizes the Transfer Descriptor structure for the lower 64 bits for DCMD tasks and Table A-14
describes transfer descriptor fields.

Table A-13 Task Descriptor Structure: Lower 64 bits (for Direct-Command (DCMD) tasks)

Command
Argument Command Parameters Task Parameters Field Attribute

63:32 31 25 24 23 22 21 16 15 14 13 6 5 3 2 1 0

xxxx_xxxxh Reserved Response CMD CMD Rsvd QBR Reserved Act=101 Int End=1 Valid =1
(0000000) Type timing Index (0) (0000000)

Table A-14 Transfer Descriptor Fields

Bit
Field Name Location Description

Valid 0 1 – The descriptor is effective and must be processed by hardware.

0 – The descriptor line must not be used.

End 1 Must always be set to 1. Every Task Descriptor is standalone.

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Table A-14 Transfer Descriptor Fields

Bit
Field Name Location Description

Int 2 Indicates the interrupt generation policy required for this task.
1 – Hardware generates an interrupt upon the task completion.
0 – Hardware does not generate an interrupt upon the task completion.
Interrupt coalescing is not used with DCMD.

Act 5:3 Is set to b101 to indicate that this is a Task Descriptor.

Reserved 13:6 Reserved

Queue Barrier 14 Indicates the control of the host on the ordering between tasks.
(QBR)

Reserved 15

CMD Index 21:16 The index of the command to be sent to the device.

CMD Timing 22 1 – Command may be sent to device during data activity or busy time.
0 – Command may not be sent to device during data activity or busy
time.
NOTE: Software is 0 if response type is b11 (R1b).

Response 24:23 This field indicates to the host controller the response expected to be
Type received from the device.
b00 – No Response Expected
b01 – Reserved
b10 – R1, R4, R5
b11 – R1b
NOTE: R2 and R3 are not supported in DCMD.

Reserved 31:25

CMD 63:32 The argument of the command to be sent to the device.

Argument

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A.9 SDIO Read Wait

A host device controls the SDCLK (card clock) to stop the read data block output from a card executing a
multiple read commands when the host cannot accept more data. The duration of time when the host has
stopped the SDCLK, a CMD52 cannot be issued. This limitation causes a problem in that a host device
cannot perform the I/O command during a multiple read cycle.
To overcome this limitation, DWC_mshc supports the read wait feature to signal a card that is executing
multiple read (CMD53) operations to temporarily pause data transfer while allowing the host to send
commands to any other function within the card. The read wait function is optional for SDIO cards.
If the card supports read wait, then the DWC_mshc controller can stall the read data from the card by
issuing read wait using the sd_dat_out[2] line at the block boundary instead of stopping the card clock. The
DWC_mshc controller asserts read wait during the NAC period of the data block if:
■ The controller is configured to stop at block gap and read wait is enabled.
■ If the packet buffer of the controller does not have sufficient space to contain the next block of data
and if read wait is enabled.
While the read wait feature is optional for SDIO cards, this feature is not supported in UHS-II cards. This
feature is defined only for the SD 1 and 4-bit modes, and it does not apply to SPI transfers.

A.10 SDIO Card Interrupt

An SD interface supports the interrupt function to allow an SDIO card to interrupt the host. An SDIO card
provides level-sensitive interrupt to DWC_mshc using the sd_dat_in[1] Interrupt Input in SD mode. This
interrupt is used to inform the host about error status and also about normal information, such as function
ready. This interrupt is also used as a source of wakeup event to inform the host to resume from standby
mode. The card interrupt is cleared when the card/device stops asserting the interrupt, that is, when the
application services the interrupt condition.
For SD 1-bit mode, there are no timing constraints for interrupt.
For 4-bit mode, the DWC_mshc samples the card interrupt only during the interrupt period that is defined
as follows:
■ Interrupt period ends from the end bit of a command that transfers the data block (1 to 3 clocks for
SDR50, SDR104, and DDR50 modes).
■ Resume two clocks after the completion of last data block transfer (2 to 4 for SDR50, SDR104, and
DDR50 modes).
■ Within the data block gap, 2-clock Interrupt period begins 2 clocks after the end bit of data blocks
(Block Gap card interrupt is disabled in SDR50, SDR104, and DDR 50 as recommended by the device
specification)
■ While the specification defines that the asynchronous interrupt period starts 4 clocks from the start of
synchronous interrupt period and ends 1 to 3 clocks from the beginning of end bit of data command,
the DWC_mshc does not distinguish between synchronous and asynchronous interrupt periods.
■ In case of abort CMD, the interrupt period ends 2 clocks after the end bit of abort CMD and resumes
2 clocks after the end bit of the response

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An asynchronous interrupt is effective in SD 4-bit mode. The asynchronous interrupt generated from the
device while the card clock is stopped to save the power is delivered to the host system.

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B
Synchronizer and Technology Specific Cells

This appendix describes the synchronizer methods (blocks of synchronizer functionality) that are used in
the DWC_mshc to cross clock boundaries.
This appendix contains the following sections:
■ “Synchronizers Used in DWC_mshc” on page 596
■ “Technology-Specific Cells in DWC_mshc DWC_mshc” on page 603

The DesignWare Building Blocks (DWBB) contain several synchronizer components with
Note
functionality similar to methods documented in this appendix. For more information about the
DWBB synchronizer components, go to:
http://www.synopsys.com/dw/buildingblock.php

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B.1 Synchronizers Used in DWC_mshc

Each of the synchronizers and synchronizer sub-modules are comprised of verified DesignWare Basic
controller (BCM) RTL designs. The BCM synchronizer designs are identified by the synchronizer type. The
corresponding RTL files comprising the BCM synchronizers used in the DWC_mshc are listed and cross-
referenced to the synchronizer type in Table B-1. Table B-1 also lists the equivalent Designware Building
Block component.

■ It is not recommended to replace the RTL BCM with corresponding DWBB.

Note
■ Certain BCM modules are contained in other BCM modules, as they are used in a building
block fashion.

Table B-1 Synchronizers used in DWC_mshc

Synchronizer module
file Sub module file Synchronizer Type and Number DWBB Equivalent

DWC_mshc_bcm21.v Synchronizer 1: Simple Multiple DW_sync

Register Synchronizer

DWC_mshc_bcm22.v DWC_mshc_bcm21.v Synchronizer 2: Pulse DW_pulse_sync

Synchronizer

DWC_mshc_bcm41.v DWC_mshc_bcm21.v Synchronizer 3: Simple Multiple

Register Synchronizer with
Configurable Polarity Reset

DWC_mshc_bcm74.v DWC_mshc_bcm08.v Synchronizer 4: Dual Independent DW_fifo_2c_df

DWC_mshc_bcm09.v Clock FIFO Controller
DWC_mshc_bcm21.v
DWC_mshc_bcm22.v
DWC_mshc_bcm24.v
DWC_mshc_bcm37.v
DWC_mshc_bcm38.v
DWC_mshc_bcm58.v
DWC_mshc_bcm23.v DWC_mshc_bcm21.v Synchronizer 5: Pulse DW_pulseack_sync
Synchronizer with Acknowledge

B.1.1 Synchronizer 1: Simple Double Register Synchronizer (DWC_mshc_bcm21.v)

This is a single clock data bus synchronizer for synchronizing data that crosses asynchronous clock
boundaries. The parameters allow you to configure for the number of synchronizing stages (2 or 3), the style
of first-stage capturing flip-flop needed (negative or positive edge-triggered), and insertion of 'hold latches'
to facilitate scan testing.

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Figure B-1 Synchronizer 1: Synchronization Type 1

D Q width D Q
data_s data_d

Configured as : f_sync_type = 1, ‘DW_MODEL_MISSAMPLES not defined

(tst_mode parameter and test input port are not used when f _sync_type = 1)

Missampling Disabled

Missampling width D Q width D Q

data_s Delay Block data_d
(per-bit basis)

Configured as : f_sync_type = 1, ‘DW_MODEL_MISSAMPLES is defined

(tst_mode parameter and test input port are not used when f _sync_type = 1)

Missampling Enabled

Figure B-2 Synchronizer 1: Synchronization Type 2

test

width width width

data_s D Q D Q data_d

D Q width

Configured as : f_sync_type = 2, tst_mode = 1

‘DW_MODEL_MISSAMPLES not defined

Missampling Disabled

test
Missampling width width width
data_s Delay Block D Q D Q data_d
(per-bit basis)

D Q width

Configured as : f_sync_type = 2, tst_mode = 1

‘DW_MODEL_MISSAMPLES is defined

Missampling Enabled

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Figure B-3 Synchronizer 1: Synchronization Type 3

test

width width width width

data_s D Q D Q D Q data_d

width
D Q width

Configured as : f_sync_type = 3, tst_mode = 1

‘DW_MODEL_MISSAMPLES not defined

Missampling Disabled

test
Missampling
width width width width
data_s Delay Block D Q D Q
D Q data_d
(per-bit basis)
width
width
D Q

Configured as : f_sync_type = 3, tst_mode = 1

‘DW_MODEL_MISSAMPLES is defined

Missampling Enabled

Figure B-4 Synchronizer 1: Missampling Model Type 0

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Figure B-5 Synchronizer 1: Missampling Model Type 1

width width To first-stage

data_s synchronizing
flip-flops

BIT# 0 D Q

Random
Number
Generator

BIT# ( width-1) D Q

Random Missampling Delay Block configured with verif _en =1

Number
Generator

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Figure B-6 Synchronizer 1: Missampling Model Type 2

width width To first-stage

data_s synchronizing
flip-flops

BIT# 0 D Q D Q D Q

Random
Number 2
Generator

BIT# ( width-1) D Q D Q D Q

Missampling Delay Block

configured with verif _en =2
Random
Number 2
Generator

B.1.2 Synchronizer 2: Pulse Synchronizer (DWC_mshc_bcm22.v)

This is a dual clock pulse synchronizer for transmitting the single clock cycle pulses between two different
clock domains. This method uses clock domain crossing techniques to safely transfer pulses between logic
operating on different clocks.

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Figure B-7 Synchronizer 2 Block Diagram

clk_s clk_d

double register
synchronizer

D Q Synchronizer 1 D Q event _d
event_s toggle signal
crosses domains

Configured without an output register

(parameter reg _event =0)

clk_s clk_d

double register
synchronizer
D Q
D Q
Synchronizer 1 event _d
event _s D Q toggle signal
crosses domains

Configured with an output register

(parameter reg _event =1)

B.1.3 Synchronizer 3: Simple Multiple Register Synchronizer with Configurable Polarity

Reset
This is a single clock data bus synchronizer for synchronizing data that crosses asynchronous clock
boundaries with configurable reset value. This synchronizer module is same as DWC_mshc_bcm21 with
configurable reset value. This module is used where reset value of 1 is required.

B.1.4 Synchronizer 4: Dual Independent clock FIFO (DWC_mshc_bcm74.v)

This module implements the functions required to implement a FIFO once connected to a RAM. The push
and pop interfaces are in different clock domains. Gray coded pointers are used to pass information
between domains.
Figure B-8 shows a simple block diagram of the Synchronizer 4.

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Figure B-8 Synchronizer 4 block diagram

clk_s clk_d

data_s data_d

push_s_n Control Dual port RAM

Logic wr_en
(Push
Interface) wr_addr
rd_addr full_d
empty_d

Pointer
en
Synchronizer 1
Arithemtic
almost_full_d
Dual Mode
Counter Gray
Binary almost_empty_d
full_s

empty_s en Control Logic pop_d_n

(Pop
Dual Mode
Interface)
Pointer Binary Counter
Gray
Arithemtic
almost_full_s

almost_empty_s Synchronizer 1

B.1.5 Synchronizer 5: Pulse Synchronizer with Acknowledge (DWC_mshc_bcm23.v)

Dual-clock pulse synchronizer with acknowledge. bcm23 provides a low-risk method for transmitting
single-clock cycle pulses between two different clock domains using acknowledge.

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B.2 Technology-Specific Cells in DWC_mshc DWC_mshc

DWC_mshc facilitates certain modules to be replaced by technology-specific cells. Following sections
discuss the modules that can be replaced:
■ “The DWC_mshc_clk_mux_2x1.v Module” on page 603
■ “The DWC_mshc_ddr_mux_2x1.v Module” on page 604
■ “The DWC_mshc_clk_gate.v Module” on page 604
■ “The DWC_mshc_bcm21.v Module” on page 606
■ “The DWC_mshc_ddr_mux_sel Module” on page 607

B.2.1 The DWC_mshc_clk_mux_2x1.v Module

The DWC_mshc_clk_mux_2x1.v module implements a clock multiplexer and is used to muxtiplex
sd_dat_stb or cclk_rx to sample the data/command response from the eMMC device based on the speed of
operation. This module is also used to muxtiplex the clock during scan mode for negative-edge-triggered
flops such that these flops can be connected in a positive edge scan chain. It is recommended to replace this
module with a balanced muxtiplexor from the technology library.
Figure B-9 shows the multiplexor implemented in the DWC_mshc_clk_mux2x1 module.

Figure B-9 DWC_mshc_clk_mux2x1

DWC_mshc_clk_mux_2x1

in0_clk
0
out_clk

in1_clk 1

clk_sel

Figure B-10 Functional Timing Diagram for DWC_mshc_clk_mux2x1

in0_clk .

in1_clk

clk_sel

out_clk

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B.2.2 The DWC_mshc_ddr_mux_2x1.v Module

The DWC_mshc_ddr_mux_2x1 module implements the data multiplexor that generates the DDR output. To
support dual-data rate for an SD/eMMC device, the final output data is combinatorially multiplexed in the
DWC_mshc_ddr_mux_2x1 module. It is recommended to replace this module with a technology-specific
balanced muxtiplexor.
Figure B-11 shows the multiplexor implemented in the DWC_mshc_ddr_mux_2x1 module.

Figure B-11 DWC_mshc_ddr_mux_2x1

DWC_mshc_ddr_mux_2x1

data_in0
0
data_out

data_in1 1

mux_sel

Figure B-12 Timing Diagram for DWC_mshc_ddr_mux_2x1

data_in0 00 ED0 ED1 ED2

data_in1 00 OD0 OD1 OD2

mux_sel

data_out 00 OD0 ED0 OD1 ED1 OD2 ED2

B.2.3 The DWC_mshc_clk_gate.v Module

This DWC_mshc_clk_gate.v module implements an integrated clock gate. When gated, the clock output is
low. This module is a flip-flop based clock gating logic. This cell is used by DWC_mshc to stop clocks under
certain functional contexts when a module, which is connected to DWC_mshc, is determined as idle. It is
recommended to replace this cell with an Integrated Clock Gating Cell (ICGC), which is library-specific and
is a negative edge flop based with an AND Gate. Figure B-13 shows integrated clock gate implemented in
the DWC_mshc_clk_gate module.

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Figure B-13 DWC_mshc_clk_gate

Controller_clk_gate
test_scan_mode
enable_scan
enable enable_r
DWC_mshc_clk_mux_2x1

0
clk_inv

R clk_gated
clk
1

test_posedge_clk_sel

resetn

Figure B-14 Timing Diagram for DWC_mshc_clk_gate

clk .

enable

enable_r

clk_gated

B.2.4 The DWC_mshc_clkgate_cell.v Module

The DWC_mshc_clkgate_cell.v module implements a latch based clock gating module. When gated the
clock output is low. DWC_mshc uses this cell to stop clocks under certain functional contexts when the
module is idle.
The parameter DWC_MSHC_CLKGATE_TYPE determines if the clock gate present in DWC_MSHC is latch
based or flip-flop based. By default, latch based clock gating is enabled in DWC_mshc.
The I/O signals to both the flip-flop based and latch based clock gates are same.
Figure B-15 shows the latch based clock gate implemented in the module.

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Figure B-15 DWC_mshc_clkgate_cell

B.2.5 The DWC_mshc_bcm21.v Module

This is a 2-stage synchronizer for signal crossing the clock domains. It can be replaced with a library-specific
cell when available. For more information on a 2-stage synchronizer, see “Synchronizer 1: Simple Double
Register Synchronizer (DWC_mshc_bcm21.v)” on page 596. Figure B-16 shows the implementation of a 2-
stage synchronizer in the DWC_mshc_bcm21 module.

Figure B-16 DWC_mshc_bcm21

Controller_bcm21

data_s data_d

clk_d
R R

rst_d_n

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Figure B-17 Timing Diagram for DWC_mshc_bcm21.v Module

clk_d

rst_d_n Synchronized to clk_d

data_s

data_d

B.2.6 The DWC_mshc_ddr_mux_sel Module

This module is used to generate the multiplex control to support Dual Data Rate. It is a running signal
matching the frequency of cclk_tx. The data window of odd and even DDR data are dependent on the pulse
width of this multiplex control. It is recommended to closely match the pulse width for level '0' and '1'. This
will ensure consistent and equivalent data window for odd and even DDR data. Figure B-18 shows the
implementation of DWC_mshc_ddr_mux_sel module

Figure B-18 DDR multiplex Control

ddr_mode_en Controller_ddr_mux_sel

toggle_ddr_gen
EN ddr_mux_sel

cclk_tx
toggle_ddr_neg_gen

EN

cclk_tx_neg_gen
R
cresetn

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Figure B-19 Timing Diagram for DWC_mshc_ddr_mux_sel Module

cclk_tx

cclk_tx_neg_gen

cresetn

ddr_mode_en

toggle_ddr_gen

toggle_ddr_neg_gen

ddr_mux_sel

Sync’d to Sync’d to Combinatorially

cclk_tx cclk_tx_neg_gen generated

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C
Power Consumption and Area

This appendix discusses power and area requirements for SD, UHS-II, and eMMC modes in DWC_mshc,
and also area requirement for various configurations in DWC_mshc. It also highlight the DFT numbers for
DWC_mshc controller.
This appendix discusses the following topics:
■ “Clock Gating Types Used for Generating Power and Area Numbers for Non-AXI Configuration
(AHB Master and AHB slave port)” on page 611
■ “Technology Libraries Used to Generate Power and Area Numbers” on page 611
■ “Power and Area for an SD Configuration”
❑ “SD Configuration When AXI Data Width = 32 and AXI Address Width = 32” on page 611
❑ “SD Configuration When AXI Data Width = 64 and AXI Address Width = 32” on page 612
❑ “SD Configuration When AXI Data Width = 64 and AXI Address Width = 64” on page 613
■ “Power and Area for a UHS-II Configuration”
❑ “UHS-II Configuration When AXI Data Width = 32 and AXI Address Width = 32” on page 614
❑ “UHS-II Configuration When AXI Data Width = 64 and AXI Address Width = 32” on page 615
❑ “UHS-II Configuration When AXI Data Width = 64 and AXI Address Width = 64” on page 616
■ “Power and Area for an eMMC Configuration”
❑ “eMMC Configuration When AXI Data Width = 32 and AXI Address Width = 32” on page 617
❑ “eMMC Configuration When AXI Data Width = 64 and AXI Address Width = 32” on page 618
❑ “eMMC Configuration When AXI Data Width = 64 and AXI Address Width = 64” on page 619
■ “Maximum Configuration”
❑ “Area for SD+UH-II+eMMC+CQE Configurations for AXI Master Bus Interface Unit” on
page 620
❑ “Area for SD+UH-II+eMMC+CQE Configurations for AHB Master Bus Interface Unit” on
page 621
■ “Area in Slave-Only Mode” on page 621

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■ “Area and Power With Context Sensitive Clock Gates” on page 622
■ “Area Savings Without ADMA3 Mode” on page 622
■ “Area Savings While Using Optimized Clocking Mode” on page 622

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C.1 Clock Gating Types Used for Generating Power and Area Numbers for
Non-AXI Configuration (AHB Master and AHB slave port)
Following are the clock gating types used for generating power and area numbers for SD, UHS-II, and
eMMC configurations in DWC_mshc:
■ No clock gating (NCG) – Clock gates not inserted in the design.
■ Clock Gating (CG) – Clock gate inserted by coreConsultant. The option to insert this clock gate is
available under the "Low Power Configuration" menu in coreConsultant.
■ Design Compiler (DC) Clock Gating (CG) – Automatic clock gates inserted by the design compiler for
power optimization.

C.2 Technology Libraries Used to Generate Power and Area Numbers

Table C-1 lists the technology libraries that are used to generate power and area numbers for SD, UHS-II
and eMMC configurations in DWC_mshc.

Table C-1 Technology Libraries in DWC_mshc

Technology Node Library Used

7 nm DesignWare Logic Library for Industry Standard 28 nm HPM High-K Metal Gate Standard
Vt Process.

16 nm Industry Standard 45 nm general-purpose Library.

C.2.1 Power and Area for an SD Configuration

C.2.1.1 SD Configuration When AXI Data Width = 32 and AXI Address Width = 32
Table C-2 provides information about the power consumption of the DWC_mshc for an SD default
configuration.

Table C-2 Configuration Settings for Default SD Configuration When AXI Data Width = 32 and AXI Address
Width = 32

Configuration Value

Card Interface Type - SD

AXI Data bus width 32

AXI Address bus width 32

Packet buffer size 1024 bytes

Number of tuning steps 8

AXI Clock frequency 300 MHz

AHB Clock frequency 150 MHz

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Table C-2 Configuration Settings for Default SD Configuration When AXI Data Width = 32 and AXI Address
Width = 32

Configuration Value

SD Card Clock 200 MHz

bclk 300 MHz

tmclk 1 MHz

Table C-3 provides information about the power and area numbers for DWC_mshc when AXI data and
address width are 32.

Table C-3 Power and Area for SD Configuration When AXI Data Width = 32 and AXI Address Width = 32

Power (in W)

Total Area (in

Technology Gating Type Leakage Switching Internal Average gates)

7 nm No Clock Gating (No CG) 2.09e-07 1.91e-05 1.52e-03 1.54e-03 82365

Design Compiler (DC) CG 1.89e-07 3.45e-05 3.83e-04 4.18e-04 72313

16 nm No CG 7.06e-08 2.52e-05 2.64e-03 2.66e-03 86997

DC CG 6.02e-08 5.43e-05 6.52e-04 7.06e-04 75606

C.2.1.2 SD Configuration When AXI Data Width = 64 and AXI Address Width = 32
Table C-4 provides information about the power consumption of the DWC_mshc for an SD default
configuration.

Table C-4 Configuration Settings for Default SD Configuration

Configuration Value

Card Interface Type - SD

AXI Data bus width 64

AXI Address bus width 32

Packet buffer size 1024 bytes

Number of tuning steps 8

AXI Clock frequency 300 MHz

AHB Clock frequency 150 MHz

SD Card Clock 200 MHz

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Table C-4 Configuration Settings for Default SD Configuration

Configuration Value

bclk 300 MHz

tmclk 1 MHz

Table C-5 provides information about the power and area numbers for DWC_mshc when AXI data and
address width are 32.

Table C-5 Power and Area for SD Configuration When AXI Data Width = 64 and AXI Address Width = 32

Power (in W)

Total Area (in

Technology Gating Type Leakage Switching Internal Average gates)

7 nm No Clock Gating (No CG) 2.76e-07 1.84e-05 2.12e-03 2.14e-03 108520

Design Compiler (DC) CG 2.44e-07 3.86e-05 4.09e-04 4.48e-04 92855

16 nm No Clock Gating (No CG) 9.29e-08 2.80e-05 3.69e-03 3.71e-03 114885

Design Compiler (DC) CG 7.69e-08 5.70e-05 6.87e-04 7.44e-04 97250

C.2.1.3 SD Configuration When AXI Data Width = 64 and AXI Address Width = 64
Table C-6 provides information about the power consumption of the DWC_mshc for an SD default
configuration.

Table C-6 Configuration Settings for Default UHS-II Configuration When AXI Data Width=64 and AXI Address
Width=32

Configuration Value

Card Interface Type - SD

AXI Data bus width 64

AXI Address bus width 32

Packet buffer size 1024 bytes

PHY interface 16 bit

AXI Clock frequency 300 MHz

AHB Clock frequency 150 MHz

pclk 150 MHz

bclk 300 MHz

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Table C-6 Configuration Settings for Default UHS-II Configuration When AXI Data Width=64 and AXI Address
Width=32

Configuration Value

tmclk 1 MHz

Table C-7 provide information about power and area for an DWC_mshc when AXI data address width are
64.

Table C-7 Configuration Settings for SD Configuration When AXI Data Width = 64 and AXI Address Width = 64

Power (in W)

Total Area (in

Technology Gating Type Leakage Switching Internal Average gates)

7 nm No Clock Gating (No CG) 2.93e-07 1.68e-05 2.27e-03 2.29e-03 115517

Design Compiler (DC) CG 2.58e-07 3.51e-05 4.08e-04 4.44e-04 98737

16 nm No Clock Gating (No CG) 9.85e-08 2.53e-05 3.95e-03 3.98e-03 122164

Design Compiler (DC) CG 8.18e-08 5.60e-05 6.92e-04 7.48e-04 103316

C.2.2 Power and Area for a UHS-II Configuration

C.2.2.1 UHS-II Configuration When AXI Data Width = 32 and AXI Address Width = 32
Table C-8 provides information about the power consumption of the DWC_mshc for a UHS-II default
configuration.

Table C-8 Configuration Settings for Default UHS-II Configuration When AXI Data Width = 32 and AXI
Address Width = 32

Configuration Value

Card Interface Type - UHS-II

AXI Data bus width 32

AXI Address bus width 32

Packet buffer size 1024 bytes

Number of tuning steps 8

AXI Clock frequency 300 MHz

AHB Clock frequency 150 MHz

SD Card Clock 200 MHz

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Table C-8 Configuration Settings for Default UHS-II Configuration When AXI Data Width = 32 and AXI
Address Width = 32

Configuration Value

bclk 300 MHz

tmclk 1 MHz

Table C-9 provides information about the power and area numbers for DWC_mshc when AXI data and
address width are 32.

Table C-9 Power and Area for UHS-II Configuration When AXI Data Width = 32 and AXI Address Width = 32

Area (in
Power (in W) gates)

Total
Technology Gating Type Leakage Switching Internal Average

7 nm No Clock Gating (No CG) 2.43e-07 1.15e-05 1.68e-03 1.69e-03 95059

Design Compiler (DC) CG 2.19e-07 2.92e-05 3.53e-04 3.82e-04 83447

16 nm No Clock Gating (No CG) 8.18e-08 1.39e-05 2.94e-03 2.95e-03 100579

Design Compiler (DC) CG 7.00e-08 4.04e-05 5.85e-04 6.25e-04 87678

C.2.2.2 UHS-II Configuration When AXI Data Width = 64 and AXI Address Width = 32
Table C-10 provides information about the power consumption of the DWC_mshc for an UHS-II default
configuration.

Table C-10 Configuration Settings for Default UHS-II Configuration

Configuration Value

Card Interface Type - UHS-II

AXI Data bus width 64

AXI Address bus width 32

Packet buffer size 1024 bytes

Number of tuning steps 8

AXI Clock frequency 300 MHz

AHB Clock frequency 150 MHz

SD Card Clock 200 MHz

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Table C-10 Configuration Settings for Default UHS-II Configuration

Configuration Value

bclk 300 MHz

tmclk 1 MHz

Table C-11 provides information about the power and area numbers for DWC_mshc when AXI data width
is 64 and address width is 32.

Table C-11 Power and Area for UHS-II Configuration When AXI Data Width = 64 and AXI Address Width = 32

Area (in
Power (in W) gates)

Total
Technology Gating Type Leakage Switching Internal Average

7 nm No Clock Gating (No CG) 2.77e-07 1.29e-05 1.97e-03 1.98e-03 108187

Design Compiler (DC) CG 2.47e-07 2.97e-05 3.65e-04 3.95e-04 94156

16 nm No Clock Gating (No CG) 9.26e-08 1.62e-05 3.44e-03 3.45e-03 114528

Design Compiler (DC) CG 7.86e-08 3.84e-05 6.03e-04 6.42e-04 98865

C.2.2.3 UHS-II Configuration When AXI Data Width = 64 and AXI Address Width = 64
Table C-12 provides information about the power consumption of the DWC_mshc for an UHS-II default
configuration.

Table C-12 Configuration Settings for Default UHS-II Configuration When AXI Data Width=64 and AXI Address
Width=64

Configuration Value

Card Interface Type - UHS-II

AXI Data bus width 64

AXI Address bus width 64

Packet buffer size 1024 bytes

PHY interface 16 bit

AXI Clock frequency 300 MHz

AHB Clock frequency 150 MHz

pclk 150 MHz

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Table C-12 Configuration Settings for Default UHS-II Configuration When AXI Data Width=64 and AXI Address
Width=64

Configuration Value

bclk 300 MHz

tmclk 1 MHz

Table C-13provide information about power and area for an DWC_mshc when AXI data and address
widths are 64.

Table C-13 Configuration Settings for UHS-II Configuration When AXI Data Width = 64 and AXI Address Width =
64

Power (in W)

Total Area (in

Technology Gating Type Leakage Switching Internal Average gates)

7 nm No Clock Gating (No CG) 2.94e-07 1.25e-05 2.12e-03 2.13e-03 115151

Design Compiler (DC) CG 2.62e-07 2.36e-05 3.71e-04 3.95e-04 100043

16 nm No Clock Gating (No CG) 9.84e-08 1.49e-05 3.69e-03 3.71e-03 121820

Design Compiler (DC) CG 8.35e-08 4.02e-05 6.07e-04 6.48e-04 104951

C.2.3 Power and Area for an eMMC Configuration

C.2.3.1 eMMC Configuration When AXI Data Width = 32 and AXI Address Width = 32
Table C-14 provides information about the power consumption of the DWC_mshc for an eMMC default
configuration.

Note Data strobe and cqe enabled configurations.

Table C-14 Configuration Settings for Default eMMC Configuration When AXI Data Width = 32 and AXI
Address Width = 32

Configuration Value

Card Interface Type - eMMC

AXI Data bus width 32

AXI Address bus width 32

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Table C-14 Configuration Settings for Default eMMC Configuration When AXI Data Width = 32 and AXI
Address Width = 32

Configuration Value

Packet buffer size 1024 bytes

Number of tuning steps 8

AXI Clock frequency 300 MHz

AHB Clock frequency 150 MHz

SD Card Clock 200 MHz

bclk 300 MHz

tmclk 1 MHz

Table C-15 provides information about the power and area numbers for DWC_mshc when AXI data and
address widths are 32.

Table C-15 Power and Area for eMMC Configuration When AXI Data Width = 32 and AXI Address Width = 32

Area (in
Power (in W) gates)

Total
Technology Gating Type Leakage Switching Internal Average

7 nm No Clock Gating (No CG) 2.57e-07 2.01e-05 1.78e-03 1.81e-03 100729

Design Compiler (DC) CG 2.37e-07 3.93e-05 4.85e-04 5.25e-04 90529

16 nm No Clock Gating (No CG) 8.67e-08 2.91e-05 3.11e-03 3.14e-03 106542

Design Compiler (DC) CG 7.61e-08 6.07e-05 8.12e-04 8.73e-04 94804

C.2.3.2 eMMC Configuration When AXI Data Width = 64 and AXI Address Width = 32
Table C-16 provides information about the power consumption of the DWC_mshc for an eMMC default
configuration.

Table C-16 Configuration Settings for Default eMMC Configuration

Configuration Value

Card Interface Type - eMMC

AXI Data bus width 64

AXI Address bus width 32

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Table C-16 Configuration Settings for Default eMMC Configuration

Configuration Value

Packet buffer size 1024 bytes

Number of tuning steps 8

AXI Clock frequency 300 MHz

AHB Clock frequency 150 MHz

SD Card Clock 200 MHz

bclk 300 MHz

tmclk 1 MHz

Table C-17 provides information about the power and area numbers for DWC_mshc when AXI data width
is 64 and address width is 32.

Table C-17 Power and Area for eMMC Configuration When AXI Data Width = 64 and AXI Address Width = 32

Area (in
Power (in W) gates)

Total
Technology Gating Type Leakage Switching Internal Average

7 nm No Clock Gating (No CG) 3.25e-07 1.98e-05 2.41e-03 2.43e-03 127663

Design Compiler (DC) CG 2.92e-07 4.04e-05 5.05e-04 5.46e-04 111567

16 nm No Clock Gating (No CG) 1.09e-07 3.06e-05 4.20e-03 4.23e-03 135095

Design Compiler (DC) CG 9.33e-08 6.67e-05 8.51e-04 9.18e-04 116901

C.2.3.3 eMMC Configuration When AXI Data Width = 64 and AXI Address Width = 64
Table C-18 provides information about the power consumption of the DWC_mshc for an eMMC default
configuration.

Table C-18 Configuration Settings for Default eMMC Configuration When AXI Data Width=64 and AXI Address
Width=64

Configuration Value

Card Interface Type - eMMC

AXI Data bus width 64

AXI Address bus width 64

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Table C-18 Configuration Settings for Default eMMC Configuration When AXI Data Width=64 and AXI Address
Width=64

Configuration Value

Packet buffer size 1024 bytes

PHY interface 16 bit

AXI Clock frequency 300 MHz

AHB Clock frequency 150 MHz

bclk 300 MHz

tmclk 1 MHz

Table C-19 provide information about power and area for an DWC_mshc when AXI data and address bus
widths are 64.

Table C-19 Configuration Settings for eMMC Configuration When AXI Data Width = 64 and AXI Address Width =
64

Power (in W)

Total
Technology Gating Type Leakage Switching Internal Average Area (in gates)

7 nm No Clock Gating (No CG) 3.43e-07 1.73e-05 2.55e-03 2.57e-03 134848

Design Compiler (DC) CG 3.08e-07 3.94e-05 5.08e-04 5.48e-04 117752

16 nm No Clock Gating (No CG) 1.16e-07 2.72e-05 4.45e-03 4.48e-03 142900

Design Compiler (DC) CG 9.80e-08 6.15e-05 8.50e-04 9.12e-04 123133

C.2.4 Maximum Configuration

C.2.4.1 Area for SD+UH-II+eMMC+CQE Configurations for AXI Master Bus Interface Unit
Table C-20 lists the area for SD+UHS-II+eMMC+CQE default configuration for 28nm and 45nm libraries for
AXI Master Bus Interface Unit (MBIU) configuration.

Table C-20 Area for Default SD+UHS-II+eMMC+CQE Configuration for AXI MBIU

Gates

AXI Data Width = 32 AXI Data Width = 64 AXI Data Width = 64

Library AXI Bus Width = 32 AXI Bus Width = 32 AXI Bus Width = 64

Industry Standard 7 nm 147621 175094 181816

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Table C-20 Area for Default SD+UHS-II+eMMC+CQE Configuration for AXI MBIU

Gates

AXI Data Width = 32 AXI Data Width = 64 AXI Data Width = 64

Library AXI Bus Width = 32 AXI Bus Width = 32 AXI Bus Width = 64

Industry Standard 16 nm 156185 184801 192246

C.2.4.2 Area for SD+UH-II+eMMC+CQE Configurations for AHB Master Bus Interface Unit
Table C-21 lists the area for SD+UHS-II+eMMC+CQE default configuration for 28nm and 45nm libraries for
AHB MBIU configuration.

Table C-21 Area for Default SD+UHS-II+eMMC+CQE Configuration for AHB MBIU

Gates

AXI Data Width = 32 AXI Data Width = 64

Library AXI Bus Width = 32 AXI Bus Width = 32

Industry Standard 7 nm 142655 169263

Industry Standard 16 nm 150903 178890

C.2.5 Area in Slave-Only Mode

Table C-22 provides information about the area configuration used for slave-only mode.

Table C-22 Configuration Used for Slave-Only Mode Area Generation

Master if present No

Packet buffer size 1024 bytes

AHB Clock frequency 150MHz

pclk 150MHz

bclk 300MHz

cclk 200MHz

tmclk 1 MHz

Technology 7 nm and 16nm

Table C-23 provides information about the Area for SD, eMMC and SD+eMMC+UHS-II configurations.

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Table C-23 Area for SD, eMMC and SD+eMMC+UHS-II Configurations

Configuration Area Savings in Gate Count

SD 48462

eMMC 43383

SD+eMMC+UHS-II 47402

C.2.6 Area and Power With Context Sensitive Clock Gates

Table C-24 provides information about power benefits of individual clock gates that can be inserted using
coreConsultant. The information in Table C-24 lists results generated using the SD+eMMC mode with CQE.

Table C-24 Power Saving Achieved in SD+eMMC Mode (with CQE) using the
test_cust_card_wr_rd_emmc_cqe_mode Testcase

Area Increase Power Saving

CG Configuration (in gates) (in mW)

DMA CG 233 0.25

TS CG 295 0.57

CQE CG 393 0.891

MBIU CG 178 1.07

ASYNC CG 444 0.31

ALL CG 815 1.94

C.2.7 Area Savings Without ADMA3 Mode

Table C-25 provides information about the area saved when ADMA3 mode is deselected in coreConsultant.

Table C-25 Area for Default Configuration for 28 nm Without ADMA3 Mode

Configuration Area Savings Without ADMA3

Default 4889 gates

C.2.8 Area Savings While Using Optimized Clocking Mode

Table C-26 provides configuration used for capturing area saved information when using various
optimized clocking modes.

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Table C-26 Area Saved in Various Optimized Clocking ModesE-0

Configuration Used Value

Card Interface Type - SD + UHS-II + eMMC

AXI Data bus width 32

AXI Address bus width 32

Packet buffer size 1024 bytes

PHY interface 16 bit

CQE enable 1

AXI Clock frequency 300 MHz

AHB Clock frequency 150 MHz

pclk 150 MHz

bclk 300 MHz

tmclk 1 MHz

Table C-27 provides information about area saving for configuration

Table C-27 Area Saved for Different Configurations

Configuration Gate Count Savings

Master, base and slave clock merged 10643

Master and base clock merged 3481

Master and slave clock merged 441

Base and slave clock merged 6833

C.3 Design for Testability for Controller

Table C-28 provides information about the Design for Testability (DFT)of the DWC_mshc for an SD default
configuration.

Table C-28 Design for Testability in DWC_mshc

TetraMax Values

TetraMAX StuckAtTestCov 99.9%

TetraMAX StuckAtFaultCov 99.8%

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D
Clock and Data Crossing (CDC)

This appendix discusses information about clocks and metastability simulation in DWC_mshc.

D.1 DWC_mshc Clocks

The DWC_mshc contains the following eight clocks:
■ hclk (slave clock)
■ aclk/m_hclk (master clock)
■ bclk (base clock)
■ pclk (PHY clock for UHS-II)
■ cclk_tx (Transmit card clock for SD/eMMC)
■ cclk_rx (Receive card clock for SD/eMMC)
■ tmclk (Timer clock)
■ cqetmclk (CQE timer clock)
■ tck (JTAG interface clock)
For detailed information on clocks, see the "Clock I/O Interface" section in the DesignWare Cores Mobile
Storage Host Controller User Guide.
The Spyglass CDC report confirms that all CDC paths in the design were synchronized between clock
domains using standard CDC library parts as discussed in “Synchronizers Used in DWC_mshc” on
page 596, with the exception of the paths that are waived. Re-convergence CDC reports have been
generated and analyzed for upto sequential re-convergence depth of 3.

D.2 Metastability Simulation

The CDC synchronizer parts have a behavioral metastability model to simulate metastability missampling
across the clock domain. By passing the DW_MODEL_MISSAMPLES parameter, the part randomly
missamples data transitions across the clock domain, thereby stressing the CDC design. This stressing
highlights areas of the design prone to error caused by divergence and re-convergence as the CDC signals is
skewed by the missampling algorithm.

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D.3 Asynchronous Input Signals

Certain input signals to DWC_mshc are assumed to be asynchronous. They are internally synchronized
using BCM21/BCM41. Following are the asynchronous input signals:
■ card_clk_stable
■ int_bclk_stable
■ int_aclk_stable
■ int_tmclk_stable
■ host_reg_vol_stable
■ card_detect_n
■ card_write_prot
■ sd_dat_in
■ sd_cmd_in

D.4 Naming Convention Used for CDC Signals

Every clock-crossing signal has a prefix that identifies the signal type. The prefix helps in identifying the
signals during design, review, and analysis phases. This also enables exception filtering using the signal
prefixes. The prefix indicates source clock, destination clock, type of signal and whether the clock is
synchronized. Prefix consists of letters used for clocks and acronyms used for type of signal. Figure D-1
shows a prefix “m2s_l” used for the pktstat signal.

Figure D-1 Naming Convention for Source Clock Domain Signal

Destination Clock

m2s_l_pktstat

Signal Name
Source
Clock Type of Signal

The name of synchronized signal is name of source clock domain signal prefixed with letter ‘s’. The
synchronized version of “m2s_l_pktstat “signal is called as “sm2s_l_pktstat”. Table D-1 shows alphabets
used for different DWC_mshc clock names.

Table D-1 Alphabet Used to Depict a Clock Name

Clock Name Alphabet

hclk s

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Table D-1 Alphabet Used to Depict a Clock Name

Clock Name Alphabet

aclk/m_hclk m

bclk b

cclk_tx tx

cclk_rx rx

pclk p

tmclk tm

cqetmclk ctm

Unknown clock x

Table D-2 shows alphabets used for different signal types.

Table D-2 Alphabet Used to Depict a Signal Type

Signal Type Alphabet

Level signal l

Toggle signal t

Pulse signal p

Quasi static signal qs

D.5 Naming Convention Used for Synchronizer (BCM) Instances

Each synchronizer instance is provided with a unique and formatted name. An instance name contains
information about source clock, destination clock, type of synchronizer, and name of signal. Consider that
pkststat is synchronized from master clock (aclk/m_hclk) to slave clock (hclk) using pulse synchronizer.
Figure D-2 shows the prefix used for the pktstat signal and the synchronizer instance name is suffixed with
“sync”.

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Figure D-2 Naming Convention Used for a Synchronizer Instance

The alphabets used to depict clocks are the same as in Table D-1. The alphabets used to depict a
synchronous module are listed in Table D-3.

Table D-3 Alphabet Used to Depict a Synchronizer Module

Type of Synchronizer Synchronizer Module Alphabet

Simple Multiple Register BCM21/BCM41 l

Synchronizer.

Pulse synchronizer that BCM22 p

generates pulse using pulse
in the source clock domain.

Pulse synchronizer that BCM22 tp

generates pulse using
toggle signal source clock
domain.

Pulse synchronizer that BCM22 rp

generates pulse using rising
edge in source clock
domain.

Pulse synchronizer that BCM22 fp

generates pulse using falling
edge in source clock
domain.

Asynchronous FIFO BCM74 af

Quasi-static synchronizer BCM36 qs

Note The naming convention in Table D-3 is applicable to only those BCM instances that
are not instantiated under any other BCM module.

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D.5.1 Context-Sensitive Clock Gating

This feature reduces the active mode power of DWC_mshc during active and idle modes by inserting clock
gates that are controlled by DWC_mshc. The functional clock gating control is generated and controlled by
the hardware, and the functional gating signal must be synchronous to the clock that is being gated. By
default, this feature is always enabled and it can be disabled by setting the MSHC_CTRL_R.SW_CG_DIS
register bit. The test_scan_mode signal can be used to disable clock gating during design for test (DFT).
test_scan_mode signal ensures that both the hardware and software controls are disabled when in test
mode.
test_scan_mode' input can disable clock gating during DFT
The following parameters can be used to reduce power by configuring DWC_mshc to insert respective clock
gates:
■ DWC_MSHC_MBIU_CLK_GATE
■ DWC_MSHC_DMA_CLK_GATE
■ DWC_MSHC_CQE_CLK_GATE
■ DWC_MSHC_TS_CLK_GATE
■ DWC_MSHC_ASYNC_CLK_GATE

Note For CDC reasons, MSHC_CTRL_R.SW_CG_DIS should be programmed only when

aclk/m_hclk, bclk, cclk_tx and cclk_rx clocks are stopped.

These parameters are available under "Low Power Configuration" settings in coreConsultant as shown in
Figure D-3.

Figure D-3 Low-Power Configuration

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D.5.2 Optimized Clocking Mode

DWC_mshc provides the DWC_MSHC_CLKS_GROUP_EN and DWC_MSHC_CLKS_GROUP_SEL
parameters to reduce the consumption of area and power by optimizing the usage of clocks. The
DWC_MSHC_CLKS_GROUP_EN parameter enables you to connect grouped clocks to a common clock
source external to DWC_mshc. The DWC_MSHC_CLKS_GROUP_SEL parameter enables you to select the
clock group to which the same clock is connected. The different clock group options provided are Master
clock (aclk/m_hclk), Base clock (bclk), and Slave clock (hclk). The system design is optimized based on
selection of this clock group. The default group for this parameter is the “Master, Slave and Base Clock”.
For more information about clock connections when the Optimized Clocking Mode feature is used, see the
"Clock I/O Interface" section in the "Integrating with PHY and Application RTL" chapter in the DesignWare
Cores Mobile Storage Host Controller User Guide.

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E
Clock Domain for Individual Registers

This appendix discusses Clock Domain for Individual Registers.

Table E-1 Clock Domain for Individual Registers

Register Name Domain

SDMASA_R Master clock ; when host version 4 is enabled, it is implemented in

base clock domain and acts as 32-bit block count register

BLOCKSIZE_R Base clock

BLOCKCOUNT_R Base clock

ARGUMENT_R Base clock

XFER_MODE_R Base clock

CMD_R Base clock

RESP01_R Slave clock

RESP23_R Slave clock

RESP45_R Slave clock

RESP67_R Slave clock

BUF_DATA_R Slave clock

PSTATE_REG Slave clock

HOST_CTRL1_R Slave clock

PWR_CTRL_R Slave clock

BGAP_CTRL_R Slave clock

WUP_CTRL_R Slave clock

CLK_CTRL_R Slave clock

TOUT_CTRL_R Slave clock

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Table E-1 Clock Domain for Individual Registers

Register Name Domain

SW_RST_R Slave clock

NORMAL_INT_STAT_R Slave clock

ERROR_INT_STAT_R Slave clock

NORMAL_INT_STAT_EN_R Slave clock

ERROR_INT_STAT_EN_R Slave clock

NORMAL_INT_SIGNAL_EN_R Slave clock

ERROR_INT_SIGNAL_EN_R Slave clock

AUTO_CMD_STAT_R Slave clock

HOST_CTRL2_R Slave clock

CAPABILITIES1_R Slave clock

CAPABILITIES2_R Slave clock

CURR_CAPABILITIES1_R Slave clock

CURR_CAPABILITIES2_R Slave clock

FORCE_AUTO_CMD_STAT_R Slave clock

FORCE_ERROR_INT_STAT_R Slave clock

ADMA_ERR_STAT_R Master clock

ADMA_SA_LOW_R Master clock

ADMA_SA_HIGH_R Master clock

PRESET_INIT_R Slave clock

PRESET_DS_R Slave clock

PRESET_HS_R Slave clock

PRESET_SDR12_R Slave clock

PRESET_SDR25_R Slave clock

PRESET_SDR50_R Slave clock

PRESET_SDR104_R Slave clock

PRESET_DDR50_R Slave clock

PRESET_UHS2_R Slave clock

ADMA_ID_LOW_R Master clock

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Table E-1 Clock Domain for Individual Registers

Register Name Domain

ADMA_ID_HIGH_R Master clock

UHS_II_BLOCK_SIZE_R Base clock

UHS_II_BLOCK_COUNT_R Base clock

UHS_II_COMMAND_PKT_0_3_R Base clock

UHS_II_COMMAND_PKT_4_7_R Base clock

UHS_II_COMMAND_PKT_8_11_R Base clock

UHS_II_COMMAND_PKT_12_15_R Base clock

UHS_II_COMMAND_PKT_16_19_R Base clock

UHS_II_XFER_MODE_R Base clock

UHS_II_CMD_R Base clock

UHS_II_RESP_0_3_R Slave clock

UHS_II_RESP_4_7_R Slave clock

UHS_II_RESP_8_11_R Slave clock

UHS_II_RESP_12_15_R Slave clock

UHS_II_RESP_16_19_R Slave clock

UHS_II_MSG_SEL_R Slave clock

UHS_II_MSG_R Slave clock

UHS_II_DEV_INTR_STATUS_R Slave clock

UHS_II_DEV_SEL_R Slave clock

UHS_II_DEV_INR_CODE_R Slave clock

UHS_II_SOFT_RESET_R Slave clock

UHS_II_TIMER_CNTRL_R Slave clock

UHS_II_ERR_INTR_STATUS_R Slave clock

UHS_II_ERR_INTR_STATUS_EN_R Slave clock

UHS_II_ERR_INTR_SIGNAL_EN_R Slave clock

P_UHS_II_SETTINGS_R Slave clock

P_UHS_II_HOST_CAPAB Slave clock

P_UHS_II_TEST Slave clock

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Table E-1 Clock Domain for Individual Registers

Register Name Domain

P_EMBEDDED_CNTRL Slave clock

P_VENDOR_SPECIFIC_AREA Slave clock

P_VENDOR2_SPECIFIC_AREA Slave clock

SLOT_INTR_STATUS_R Slave clock

HOST_CNTRL_VERS_R Slave clock

UHS2_GEN_SET_R Base clock

UHS2_PHY_SET_R Base clock

UHS2_LNK_TRAN_SET_1_R Base clock

UHS2_LNK_TRAN_SET_2_R Base clock

UHS2_GEN_CAP_R Slave clock

UHS2_PHY_CAP_R Slave clock

UHS2_LNK_TRAN_CAP_1_R Slave clock

UHS2_LNK_TRAN_CAP_2_R Slave clock

FORCE_UHS_II_ERR_INTR_STATUS Slave clock

_R

EMBEDDED_CTRL_R Slave clock

CQVER Master clock

CQCAP Base clock if master interface is not present; Master clock if master
interface is present

CQCFG Master clock

CQCTL Master clock

CQIS Master clock

CQISE Master clock

CQISGE Master clock

CQIC Master clock

CQTDLBA Master clock

CQTDLBAU Master clock

CQTDBR Master clock

CQTCN Master clock

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Table E-1 Clock Domain for Individual Registers

Register Name Domain

CQDQS Slave clock

CQDPT Master clock

CQTCLR Master clock

CQSSC1 Slave clock

CQSSC2 Slave clock

CQCRDCT Slave clock

CQRMEM Slave clock

CQTERRI Slave clock

CQCRI Slave clock

CQCRA Slave clock

MSHC_VER_ID_R Slave clock

MSHC_VER_TYPE_R Slave clock

MSHC_CTRL_R Slave clock

MBIU_CTRL_R Master clock

EMMC_CTRL_R Slave clock

BOOT_CTRL_R Slave clock

GP_IN_R Slave clock

GP_OUT_R Slave clock

AT_CTRL_R Slave clock

AT_STAT_R Slave clock

All registers in DWC_mshc_phy_block Slave clock

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F
Frequently Asked Questions

Following are some frequently asked questions while configuring DWC_mshc:

Q: DWC_mshc defined four types of driver strengths (Type A, Type B, Type C and Type
D) in the HOST_CTRL2_R register while the eMMC standard specifies five types of
driver strength (Type0, Type1, Type2, Type3 and Type 4). How can MSHC supports
all the driver strength in align with eMMC?
A. Currently MSHC outputs 2-bit signal “uhs1_drv_sth” reflecting the register
content of HOST_CRTL2_R.DRV_STRENGTH_SEL to select one of the driver
strength which is aligned with Host Controller specification. This 2-bit output
in conjunction with 1-bit general purpose output can be used to select one of
the driver strength supported by eMMC. Table F-1 maps eMMC driver types
using the uhs1_drv strength and gp_out output of DWC_mshc.
Table F-1 Mapping of eMMC Driver Types

Driver Type uhs1_drv_sth[1:0] gp_out[n]

Type0 00 0

Type1 01 0

Type2 10 0

Type3 11 0

Type4 xx 1

You can also implement the entire control bit using the GP_OUT_R register.
Q: In the HOST_CTRL2_R register, there is a control bit “SIGNALING_EN” that
controls the I/O voltage regulator to switch from 3.3V to 1.8V. But, in eMMC, I/O
voltage can be either 3V, 1.8V, or 1.2V. How do we control the I/O voltage switching
for eMMC?
A. Currently DWC_mshc outputs 1-bit signal (uhs1_swvolt_en) reflecting the
register content of the HOST_CTRL2_R. SIGNALING_EN field to allow the
I/O voltage switching. This 1-bit output in conjunction with 1-bit general
purpose output can be used to select any of the I/O voltage supported by

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eMMC. Table F-2 maps I/O voltage types using the uhs1_swvolt_en strength
and gp_out output of DWC_mshc.
Table F-2 Mapping of eMMC I/O Voltage Types

I/O Voltage uhs1_swvolt_en gp_out[n]

3.0V 0 0

1.8V 1 0

- 0 1

1.2V 1 1

Q: What are preset registers? Can these registers be used for eMMC?
A. DWC_mshc outputs three signals namely crclk_gen_sel, crclk_freq_sel, and
uhs1_drv_sth. Based on the required speed mode, an application must
configure the CLK_CTRL_R register to enable the external clock generator to
generate the required frequency. Additionally, the driver strength is
appropriately programmed by the application. These values can be
automatically loaded from the preset registers considering that the preset
registers are appropriately configured in coreConsultant, and if the
HOST_CTRL2_R.PRESET_VAL_ENABLE field is set to 1, based on the
selected speed modes. With this configuration, only four types of driver
strengths are supported. Type4 can be explicitly selected by programming the
GP_OUT_R (General Purpose) register. Table F-3 shows HOST_CTRL2_R
values for different speed modes.
Preset value for initialization (0x60h) is not selected by bus speed mode.
Before starting the initialization sequence host driver needs to set a clock
preset value to SDCLk/RCLK Frequency select in clock control register.
Preset value Enable can be set after initialization is completed.

Table F-3 HOST_CTRL2_R Values

Host Control 1
Register
(HOST_CTRL1_R)
Host Control 2 Register (HOST_CTRL2_R) Fields Fields

PRESET_VAL UHS2_IF_ SIGNALING UHS_MODE_ Selected Preset

_ENABLE ENABLE _EN SEL HIGH_SPEED_EN Speed Mode Register

1 1 0 111 No impact UHS-II mode PRESET_UHS2_R

1 0 0 No impact 0 SD Default PRESET_DS_R

Speed mode

1 0 0 No impact 1 SD High PRESET_HS_R

Speed mode

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Table F-3 HOST_CTRL2_R Values

Host Control 1
Register
(HOST_CTRL1_R)
Host Control 2 Register (HOST_CTRL2_R) Fields Fields

PRESET_VAL UHS2_IF_ SIGNALING UHS_MODE_ Selected Preset

_ENABLE ENABLE _EN SEL HIGH_SPEED_EN Speed Mode Register

1 0 1 000 No impact SDR12/ PRESET_SDR12_

eMMC legacy R
mode

1 0 1 001 No impact SDR25/ PRESET_SDR25_

eMMC High R
Speed mode

1 0 1 010 No impact SDR50 mode PRESET_SDR50_

R

1 0 1 011 No impact SDR104/ PRESET_SDR104

eMMC HS200 _R
mode

1 0 1 100 No impact DDR50/ PRESET_DDR50_

eMMC High R
Speed DDR
mode

1 0 1 111 No impact eMMC HS400 PRESET_UHS2_R

mode

.
Q: It is mentioned that SDCLK is phase shifted to meet the setup and hold time inside the
device. Is there any signal provided by DWC_mshc to control the phase shift?
A. DWC_mshc has configurable GP_OUT_R register. You can implement this
register to control the phase shift of the card clock.
Note: GPIO option "GP_OUT_R" has to be updated in Linux driver to control
delay lines for different speed modes
Q: We intend to do the complete Spyglass CDC analysis for eMMC mode with datastrobe
enable. What are the additional constraints to be considered?
A. As datastrobe (sd_dat_stb) and cclk_rx are used to sample the data from the
device, you must setup two scenarios of Spyglass CDC goal and perform CDC
analysis for both scenarios. This can be achieved by performing the
set_case_analysis on clk_sel that selects either sd_dat_stb or cclk_rx m,
mentioned as follows:
Scenario 1:

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set_case_analysis -name
"DWC_mshc.U_DWC_mshc_sd4.U_DWC_mshc_sd4_sync.U_DWC_mshc_sd4_sample.U_scan_
clk_mux_2x1_cclk_rx_ds_enh_mux_gen.clk_sel" -value 0
set_case_analysis -name
"DWC_mshc.U_DWC_mshc_sd4.U_DWC_mshc_sd4_sync.U_DWC_mshc_sd4_sample.U_scan_
clk_mux_2x1_cclk_rx_ds_mux_gen.clk_sel" -value 0
Scenario 2:
set_case_analysis -name
"DWC_mshc.U_DWC_mshc_sd4.U_DWC_mshc_sd4_sync.U_DWC_mshc_sd4_sample.U_scan_
clk_mux_2x1_cclk_rx_ds_enh_mux_gen.clk_sel" -value 1
set_case_analysis -name
"DWC_mshc.U_DWC_mshc_sd4.U_DWC_mshc_sd4_sync.U_DWC_mshc_sd4_sample.U_scan_
clk_mux_2x1_cclk_rx_ds_mux_gen.clk_sel" -value 1
Q: Why set_input_delay for sd_cmd_in is defined with respect to both cclk_rx and
cclk_tx in SDC? Is there any timing consideration?
A. cclk_rx is used to sample the data and the command line driven by the device.
Additionally, DWC_mshc samples sd_cmd_in in the subsequent rising edge
of cclk_tx when a command is driven out on sd_cmd_out to monitor
command conflict. As the data driven on sd_cmd_out is compared with
sd_cmd_in in the subsequent clock edge of cclk_in_tx, there is a one cycle path
timing between sd_cmd_out to sd_cmd_in.
Q: Can sd_cmd_out_en be defined as multicycle path of 2?
A. sd_cmd_out_en is asserted one cycle prior to start bit and de-asserted at the
same time with the end bit. Since the state of end-bit and default state of CMD
line is ‘1’, sd_cmd_out_en can be defined as multicycle path.
Q: Can sd_dat_out_en be defined as multicycle path of 2?
A. sd_dat_out_en is also asserted one cycle prior to start bit and de-asserted
together with endbit. It can also be defined as multi cycle path if SDIO read
wait feature for < 50MHz is not supported.

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G
Standard Terms and Definitions

Table G-1 lists the standard terms and definitions used in the DWC_mshc Databook and User Guide.

Table G-1 Standard Terms and Definitions Used in DWC_mshc Documents

Term Definition

2L-HD mode Half duplex mode with two lanes.

ADMA Advanced DMA. Includes ADMA1, ADMA2, and ADMA3 modes.

Application Upper layer of software that uses the functionality provided by the transaction layer.

ASCII American Standard Code for Information Interchange.

BCD Binary Coded Decimal.

Block Basic data transfer unit normally defined as number of bytes.

Block Gap Period between blocks of data.

Boot Code Code that performs the initial set of operations.

Boot Code Loading Transmitting boot code from the boot device to the Host after PHY initialization.

Broadcast Command sent to all cards on the SD bus.

BlockLen Block length set by CMD 16 as defined in the SD standard.

BSYN Synchronization for Boot Code Loading

CMD Command sent from host to device indicated by an index n. For example, CMD16 indicates for
Set Block length.

CQHCI Command Queuing Host Controller Interface

Descriptor table Sequence of ADMA programs created on system memory.

Device Initialization Process to make the device to enable all its functions.

DMA Direct Memory access. A method of directly access data from or to directly put into system
memory with minimal involvement of the processor.

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Table G-1 Standard Terms and Definitions Used in DWC_mshc Documents (Continued)

Term Definition

FCRDY Flow Control ReaDY

FCRDY Flow Control REQuest

FD Full Duplex mode

Flash Type of multiple time programmable non-volatile memory.

Full Duplex mode Communication mode where the direction of two lanes is opposite to each other.

Half duplex mode Communication mode where the direction of two lanes is the same.

Link (layer) Layer within the host/device that performs link management functions such as PHY
initialization, data integrity, power management, and flow control.

LSS Link Symbol Set

Node Host or device.

Payload Net amount of data.

Page Size Unit of system memory management. Normally page size is 4 KB.

PIO Programmed input/output

PHY (layer) Layer within the host/device that deals with electrical specifications, such as voltage levels
(signaling), symbol encoding/decoding.

Resume Restore and restart a suspended function (defined in SDIO spec).

SDIO SD Input/Output

SDMA Single operation DMA.

SPRAM Single Port Random Access Memory

Speed Class Minimum performance defined in default and high-speed modes.

Speed Grade Minimum performance defined in UHS-I and UHS-II modes.

Suspend Stop and save a function to be able to Resume later (defined in SDIO spec).

Transaction Unit of communication that takes place by one command.

Transaction (layer) Layer within the host/device that performs protocol management including packet generation
and analysis, command-response handshake.

Tuning Process of adjusting the sampling clock to optimally sample the received data. Normally
achieved using the tuning command by Host.

UHS-I Ultra high-speed version-1

UHS-II Ultra high-speed version -2

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H
Internal Parameter Descriptions
Provides a description of the internal parameters that might be indirectly referenced in expressions in the
Signals, Parameters, or Registers chapters. These parameters are not visible in the coreConsultant GUI and
most of them are derived automatically from visible parameters. You must not set any of these parameters
directly.
Some expressions might refer to TCL functions or procedures (sometimes identified as function_of) that
coreConsultant uses to make calculations. The exact formula used by these TCL functions is not provided in
this chapter. However, when you configure the core in coreConsultant, all TCL functions and parameters
are evaluated completely; and the resulting values are displayed where appropriate in the coreConsultant
GUI reports.

Table H-1 Internal Parameters

Parameter Name Equals To

BUS_WIDTH_PRESET 7'b000_0000

CCMD 3'b000

DWC_MSHC_ADDR64_V3_SUPPORT =(DWC_MSHC_MBIU_AW == 64)

DWC_MSHC_ADDR64_V4_SUPPORT =(DWC_MSHC_MBIU_AW == 64)

DWC_MSHC_ANY_CLK_GATE { (DWC_MSHC_INTERNAL_CLK_GATE ==1) ||

(DWC_MSHC_MBIU_CLK_GATE ==1) ||
(DWC_MSHC_DMA_CLK_GATE ==1) ||
(DWC_MSHC_CQE_CLK_GATE ==1) ||
(DWC_MSHC_TS_CLK_GATE ==1) ||
(DWC_MSHC_ASYNC_CLK_GATE ==1) }

DWC_MSHC_AXI_BL 16

DWC_MSHC_BADDRW =[::DWC_mshc::calc_baddrw
DWC_MSHC_EMMC_CQE_EN
DWC_MSHC_EMMC_CQE_EXTRA_ROWS
DWC_MSHC_PKT_BUFFER_DEPTH
DWC_MSHC_CMDQD]

DWC_MSHC_BLW =[::DWC_mshc::calc_num_in_log2
DWC_MSHC_AXI_BL]

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Table H-1 Internal Parameters (Continued)

Parameter Name Equals To

DWC_MSHC_BUS_8BIT_SUPPORT {(DWC_MSHC_SD_EMMC_SUPPORT == 1) &&

(DWC_MSHC_SD_DAT_WIDTH == 1)}

DWC_MSHC_DDR50_SUPPORT {(DWC_MSHC_SD_EMMC_SUPPORT ==1) &&

(DWC_MSHC_LS_NO_PHY_MODE ==0)}

DWC_MSHC_EMMC_SUPPORT {DWC_MSHC_CARD_INTERFACE_TYPE == 3 ||
DWC_MSHC_CARD_INTERFACE_TYPE == 4 ||
DWC_MSHC_CARD_INTERFACE_TYPE == 5}

DWC_MSHC_HIGHSPD_SUPPORT 1

DWC_MSHC_POSEDGE_SCAN_CLK {(DWC_MSHC_SD_EMMC_SUPPORT ==1) ||

(DWC_MSHC_ANY_CLK_GATE ==1)}

DWC_MSHC_QOS_EN 0

DWC_MSHC_RAC_INT_PIPE_STAGE 0

DWC_MSHC_SD_EMMC_SUPPORT {DWC_MSHC_CARD_INTERFACE_TYPE == 0 ||
DWC_MSHC_CARD_INTERFACE_TYPE == 1 ||
DWC_MSHC_CARD_INTERFACE_TYPE == 3 ||
DWC_MSHC_CARD_INTERFACE_TYPE == 4 ||
DWC_MSHC_CARD_INTERFACE_TYPE == 5}

DWC_MSHC_SDR104_SUPPORT {(DWC_MSHC_SD_EMMC_SUPPORT ==1) &&

(DWC_MSHC_LS_NO_PHY_MODE ==0)}

DWC_MSHC_SDR50_SUPPORT {DWC_MSHC_SD_EMMC_SUPPORT ==1}

DWC_MSHC_STRW {DWC_MSHC_MBIU_DW/8}

DWC_MSHC_SUSRES_SUPPORT 0

DWC_MSHC_UHS2_64BIT_ADDR =(DWC_MSHC_MBIU_AW == 64)

DWC_MSHC_UHS2_BOOTCODE_LOAD 0

DWC_MSHC_UHS2_SUPPORT {DWC_MSHC_CARD_INTERFACE_TYPE == 0 ||
DWC_MSHC_CARD_INTERFACE_TYPE == 2 ||
DWC_MSHC_CARD_INTERFACE_TYPE == 3}

DWC_MSHC_VOLT18_VDD2_SUPPORT {DWC_MSHC_UHS2_SUPPORT ==1}

DWC_QOS_DW 4

DWC_SIDEBAND_TASKID_W 5

EBSY 8'b1000_0000

H 1'b1

MSHC_MAHB_LITE 0

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Table H-1 Internal Parameters (Continued)

Parameter Name Equals To

MSHC_S_ADDR_WIDTH 32

MSHC_S_DATA_WIDTH 32

MSHC_SDEMMCPHY_NUMPADS {(DWC_MSHC_SD_DAT_WIDTH ==1) ? 12 : 6}

MSHC_UHS2_PHY_LINK_WIDTH_BYTES ((DWC_MSHC_PHY_LINK_WIDTH ==0) ? 1 : 2)

MSHC_VERSION_ID {[::RCE::getIpVersionNumber -format ASCII -language

integer]}

MSHC_VERSION_TYPE {[::RCE::getIpVersionType -format ASCII -language

integer]}

ONE 2'b00

RANGE_A 2'b00

SD_DAT_WIDTH ((DWC_MSHC_SD_DAT_WIDTH ==0) ? 4 : 8)

SNPS_RSVDPARAM_6 {DWC_MSHC_PKT_BUFFER_DEPTH /
(2*(DWC_MSHC_LINK_MAX_BLK_SIZE /
(DWC_MSHC_MBIU_DW/8)))}

T_DMT_ENTRY DWC_MSHC_T_DMT_ENTRY

TRANS_ABORT 3'b011

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