Computer Science ( D9) XII - Paper –II

INSTRUCTIONS SET OF 8085

An instruction is a binary pattern designed inside a microprocessor to perform a specific
function. The entire group of instruction called the instruction set. The 8085 microprocessor
instruction set has 74 operation codes that result in 246 instructions. The 8085 instructions
can be classified into the following five function groups, five addressing modes, and three
word sizes.
Groups Addressing Mode Bytes ( Word Size)
1. Data transfer (copy) operations 1. Register 1. One byte
2. Arithmetic operations 2. Registers Indirect 2. Two bytes
3. Logical operations 3. Direct 3. Three bytes
4. Branching operations 4. Immediate
5. Machine Control and Stack I/O 5. Implied

The Following Notations are used in the A (8) F (8)

description of the instructions:
R / Rs/ Rd / r : 8-bit registers
s z A
C
P
c
(A, B, C, D, E, H and L) B (8) C (8)
M : Memory,
D (8) E (8)
(Whose address always present in HL
pair)
H (8) L (8)
Rp: Register pairs (16 bits):
BC denote B, DE denote D, HL denote H, PC (Program Counter) (16)
SP denote SP
LXI : X  Registers pairs SP (Stack Pointer) (16)

PROGRAMMING MODEL OF 8085

Groups: (Summary)
1) Data Transfer (copy): This group of instruction copies data from a location called
source to another location called as destination, without modifying the contents of the
source. The various type of data transfer(copy) are listed below:
i) Between Register: Copy the contents of 8-bit registers (source) to another
registers 8-bit (destination). Addressing mode is Register.
a. e.g. MOV A, B
ii) Data Byte to register or Memory Location: Load any 8-bit (destination)
registers with the data byte presents the instruction. Addressing mode is
Immediate.
iii) Between a Memory location and a registers: From the memory location to
any 8-bit registers and vice versa. Addressing Mode is Register Indirect or
Direct.
iv) Between an I/O device and the accumulator: From an input keyboard to the
accumulator. Addressing Mode is Implied (if Instruction doesn’t have
operand)
2) Arithmetic operations: These instructions perform arithmetic such as addition,
subtraction, increment and decrement.
a. Addition/ Subtraction: Any 8-bit number, or the content of a registers, or the
contents of a memory location can be added/subtracted to the content of the
accumulator and the sum is stored in the accumulator.

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b. Increment/Decrement: The 8-bit content of any registers or a memory

location can be increment and decrement by 1. Similarly the contents of
registers pairs can also be incremented or decremented by 1.
3) Logical Operations: These instructions perform various logical operations with the
contents of the accumulator.
a. Logical : AND , OR , NOT , EX-OR : Any 8-bit number, or the content of a
registers, or the contents of a memory location can be logically ANDed,
ORed, Complement (NOT), EXclusive –ORed with the contents of the
accumulator.
b. Rotate: Each bit in the accumulator can be shifted either left or right to the
next position.
c. Compare: Any 8-bit number, or the content of a registers, or the contents of a
memory location can be compared for <, = , > with the contents of the
accumulator.
4) Branching operations: This group of instructions alters the sequence of program
execution either conditionally or unconditionally.
5) Machine Control operations: These instruction control machine functions such as
Halt, Interrupt or Do nothing.
Bytes: The8085 instruction set is classified into the following three bytes or word sizes.
 One word or 1 byte (206) : If operand is neither 8-bit data nor 16-bit address, than the
instructions are called as One byte instruction. e.g. MOV A, B
 Two Word or 2 Bytes (23) : if the any instructions which having 8-bits data in the
operand e.g. MVI 8-bit data, ADI 8-bit data, are called as Two bytes.
 Three Word or 3 Bytes (17) : if the any instructions which having 16-bits address /data
in the operand e.g. LDA 16 bit address , LXI Rp,16 bit data are called as Three bytes.
Hint: refers the op-code chart.
Program Format:

Memory Locations Label Mnemonic Hex Code Comments

Op-code Operand
1000 one memory location for one byte Start: MOV A, B 78 1 byte Copy the content registers
B to accumulator
instruction

1001 Two memory locations for two MVI A, 39H 3E 2 Load registers A with hex
no. 39
bytes
bytes
1002 instructions
39
STA 2000 Store the content of A

32
registers to Memory
1003 location 2000

1004 Three memory locations on one 00 3 bytes

byte
20
1005 instructions

1006
1007

DATA TRANSFER (COPY) OPERATIONS: The data transfer (copy) instructions copies
data from source into a destination without modifying the contents of the source. The
previous contents of the destination are replaced by the contents of the source. No flags are
affected in data transfer instructions.

1) Syntax: MOV Rd, Rs

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Where Rd: Register destination may be any 8-bit registers (A, B, C, D, E, H and L)
Rs: Register source may be any 8-bit registers (A, B, C, D, E, H and L)
Description: Copies data from source register (Rs) into destination register (Rd).
Addressing Mode: Registers Addressing Mode (because data is transfer between Register to Register)
(Rd Rs)
A F A 23 F
Bytes: One Byte B 23 B 23
C C
Example: MOV A, B
D E D E
H L H L
Before After

Combinations: 49 instructions
MOV A, A MOV B, A MOV C, A MOV D, A MOV E, A MOV H, A MOV L, A
MOV A, B MOV B, B MOV C, B MOV D, B MOV E, B MOV H, B MOV L, B
MOV A, C MOV B, C MOV C, C MOV D, C MOV E, C MOV H, C MOV L, C
MOV A, D MOV B, D MOV C, D MOV D, D MOV E, D MOV H, D MOV L, D
MOV A, E MOV B, E MOV C, E MOV D, E MOV E, E MOV H, E MOV L, E
MOV A, H MOV B, H MOV C, H MOV D, H MOV E, H MOV H, H MOV L, H
MOV A, L MOV B, L MOV C, L MOV D, L MOV E, L MOV H, L MOV L, L

2) Syntax: MOV M, Rs or MOV Rd, M

Where Rd: Register destination may be any 8-bit registers (A, B, C, D, E, H and L)
Rs: Register source may be any 8-bit registers (A, B, C, D, E, H and L)
M : Memory, whose address always present only in HL registers pairs
Description: Copies data from source register or memory (Rs / M) to destination register or
memory (M / Rd).
Addressing Mode: Register Indirect, (because data is transfer between Register and memory.)
(M R)
Bytes: One Byte Example: MOV A, M

Combinations: 7 instructions
MOV A ,M ; MOV B ,M ; MOV C ,M ; MOV D ,M ; MOV E ,M ; MOV H ,M ; MOV L ,M
; Example : MOV M, A

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Combinations: 7 instructions
MOV M ,A ; MOV M ,B ; MOV M ,C ; MOV M ,D ; MOV M ,E ; MOV M ,H ; MOV M ,L ;

3) Syntax: MVI R, 8-bit data or MVI M, 8-bit data

Where R: Register may be any 8-bit registers (A, B, C, D, E, H and L)
8-bit data: Immediate move 8-bit data in the destination (register/memory).
M: Memory, whose address always present only in HL registers pairs
Description: The 8-bit data is stored in the destination register or memory. If the operand is a
memory location, it is specified by the contents of HL registers.
Addressing Mode: Immediate, (because data is immediate moved to Register or Memory.)
(R/M data)
Bytes: Two Bytes
Example: MVI B, 92H

Example: MVI M, 92H H 20 20 L Memory

Data
2020 92
2021
2022
Combinations: 8 Instructions
MVI A, data ; MVI B, data ; MVI C, data ; MVI D, data ; MVI E, data ; MVI H, data ;
MVI L, data and MVI M, data.
4) Syntax: LXI Rp, 16-bit
Where Rp: Registers Pairs may be any 16-bit registers pairs (BC, DE, HL and SP)
BC denotes by B, DE denotes by D, HL denotes by H and SP denotes by SP.
16-bit: may be memory address or data
Description: The instruction loads 16-bit data or memory address in the registers pairs
designated in the operand
Addressing Mode: Immediate, (because data is immediate moved to register pairs.)
(Rp 16 bit data)
Bytes: Three Bytes
Example: LXI B, 2092H

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Combinations: 4 Instructions
LXI B,16-bit; LXI D,16-bit; LXI H,16-bit; LXI SP,16-bit;

5) Syntax: LDA 16-bit address

Where LDA: Load Direct Accumulator, this instruction has only one operand and other
operand implicitly considered destination as Accumulator.
Description: The contents of a memory location, specified by a 16-bit address in the operand
are copied to the accumulator. The contents of the source are not altered.
Addressing Mode: Direct, (because data is copy to accumulator directly from 16-bit memory address.)

Combinations: Only one Instruction

6) Syntax: STA 16-bit address
Where STA: STore from Accumulator, this instruction has only one operand and other
operand implicitly considered source as Accumulator.
Description: The contents of the accumulator are copied to memory location, specified by a
16-bit address in the operand. The contents of the source are not altered.
Addressing Mode: Direct, (because data is copy from accumulator directly to 16-bit memory address.)

Combinations: Only one Instruction

ARITHMETIC OPERATIONS: The 8085 microprocessor performs various arithmetic

operations, such as addition, subtraction, increment and decrement. ADD and SUB are
performed in relation to the contents of the accumulator. Increment and decrement can be
performed in any registers. The instructions for these operations are explained below (except
INR, INX, DCR and DCX)
I. Assume implicitly that the Accumulator is one of the operand (Destination
Register).
II. Modify all the flags according to the data conditions of the results.
III. Place the result in the accumulator.
IV. Do not affect the contents of the source register.

The Instruction INR, INX, DCR, DCX

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I. Affect the contents of the specified register (A, B, C, D, E, H and L).

II. Affect all flags except the CY flag

Binary Chart
23
2
2
2 1
20
Number
Octal / Decimal
8 4 2 1
/ Hexadecimal
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3 0-7 Octal Numbers
0 1 0 0 4
0 1 0 1 5 0-9 Decimal Numbers
0 1 1 0 6 0-F Hexadecimal Numbers
0 1 1 1 7
0 & 1 Binary Numbers
1 0 0 0 8
1 0 0 1 9
1 0 1 0 A 10
1 0 1 1 B 11
1 1 0 0 C 12
1 1 0 1 D 13
1 1 1 0 E 14
1 1 1 1 F 15

ADDITION: The 8085 performs addition with 8-bit binary number and stores the sum in the
accumulator. Addition can be performed either by adding the contents of a source register (A,
B, C, D, E, H and L or memory) to the content of the accumulator.

7) Syntax: ADD R or ADD M

Where ADD: ADDition, this instruction has only one operand and other operand implicitly
considered source as Accumulator. R: may be any 8-bit registers (A, B, C, D, E, H and L).
M: Memory, whose address always present only in HL registers pairs
Description: The contents of the operand (register or memory) are added to the contents of
the accumulator and the result is stored in the accumulator. If the operand is a memory
location, that is indicated by the 16-bit address in the HL register.
Addressing Mode: Register for ADD R and Indirect for ADD M.
(A R / M)
A 99 F
B ED
Bytes: ONE Byte C
D E
Flags: All flags are modifying.
H L
Example: ADD B Before

Combinations: 8 Instructions
ADD A; ADD B; ADD C; ADD D; ADD E; ADD H; ADD L and ADD M.

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Example:

FLAGS REGISTER:

1 0 1 0 1

Example: Solve ADD M

8) Syntax: ADI 8-bit data

Where ADI: ADdition Immediate, this instruction has only one operand and other operand
implicitly considered source as Accumulator. 8-bit data: add any 8 bits data immediate to
accumulator.
Description: The 8-bit data (in operand) are added to the contents of the accumulator, and
the result in placed in the accumulator.
Addressing Mode: Immediate
(A 8-bit data)
A 99 F
Bytes: Two Bytes B C

Flags: All flags are modifying. D E

H L
Example : ADI EDH
Before Addition

A 86 1 0 1 01 F
B C

D E

H L

After Addition
Combinations: One Instruction

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SUBTRACTION: The 8085 performs subtraction by using of 2’s complement. Subtraction

can be performed by using either the instruction SUB to subtract the contents of a source
register (A, B, C, D, E, H and L or memory) from the contents of the accumulator.

9) Syntax: SUB R or SUB M

Where SUB: SUBtraction, this instruction has only one operand and other operand implicitly
considered source as Accumulator. R: may be any 8-bit registers (A, B, C, D, E, H and L).
M: Memory, whose address always present only in HL registers pairs
Description: The contents of the operand (register or memory) are subtracted to the contents
of the accumulator and the result is stored in the accumulator. If the operand is a memory
location, that is indicated by the 16-bit address in the HL register.

Addressing Mode: Register for SUB R and Indirect for SUB M.

(A R / M)
A 99 F
Bytes: ONE Byte B ED
C

Flags: All flags are modifying. D E

H L
Example : SUB B
Before
Combinations: 8 Instructions
SUB A; SUB B; SUB C; SUB D; SUB E; SUB H; SUB L and SUB M.

Example: A :1 0 0 1 1 0 0 1
B :1 1 1 0 1 1 0 1

Step 1: 1s complement of B is 0001 0010 (Substitute 0 for 1 and 1 for 0)

Step 2: Now find 2s complement obtain by adding 1 to 1s complement.
2’s complement is 0001 0010
1
A AC 1 0 0 10
00010011 F
B ED
C
Step3: D7 D6 D5 D4 D3 D2 D1 D0 D E
Carry 1 1 1
e.g. : A :1 0 0 1 1 0 0 1 H L
2s : 0 0 0 1 0 0 1 1 After

carry 0 1 0 1 0 1 1 0 0
Result AC
Sign

Step 4: Complement Carry.

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FLAGS REGISTER:

1 0 0 1 0

Example: SUB M

10) Syntax: SUI 8-bit data

Where ADI: SUbtraction Immediate, this instruction has only one operand and other operand
implicitly considered source as Accumulator. 8-bit data: subtract any data immediate to
accumulator.
Description: The 8-bit data (in operand) are subtracted to the contents of the accumulator,
and the result in placed in the accumulator.
Addressing Mode: Immediate
(A 8-bit data)

Bytes: Two Bytes

Flags: All flags are modifying.

Example : SUI EDH

A 99 F
B C

D E

H L

Before Immediate Subtraction

A AC 1 0 010 F
B C

D E

H L

After Immediate Subtraction

Combinations: One Instruction

11) Syntax: INR R or INR M

Where INR: INcrement; R: may be any 8-bit registers (A, B, C, D, E, H and L).
M: Memory, whose address always present only in HL registers pairs

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Description: The contents of the designated register or memory are incremented by 1 and the
results are stored in the same register or memory. If the operand is a memory location, that is
indicated by the 16-bit address in the HL register pair.
Addressing Mode: Register For INR R; Register Indirect For INR M
(R /M Inc by 1)

Bytes: One Byte

Flags: S, Z, P, AC are modified to reflect the result of the operation. CY is not modified.
Example : INR A

A: 1 0 0 1 1 0 0 0
1
1 0 0 1 1 0 0 1

A 98 F A 99 1 0 0 1 0 F
B C B C
D E D E
H L L
H
Before Addition After Addition

Combination : INR A, INR B, INR C, INR D, INR E, INR H, INR L

Example: INR M
12) Syntax: INX Rp
Where Rp: Registers Pairs may be any 16-bit registers pairs (BC, DE, HL and SP)
BC denotes by B, DE denotes by D, HL denotes by H and SP denotes by SP.
Description: The contents of the specified register pair are incremented by 1 and the results
are stored in the same register pair.
Addressing Mode: Register
(Rp Inc by 1)
Bytes: One Byte
Flags: S, Z, P , AC flags are affected but CY flag is not modified.
Example: INX D
Binary Numbers Hexa
A: 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2000
1 1
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 2001

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Combinations: INX B, INX D, INX H, INX SP

13) Syntax: DCR R or DCR M

Where DCR: Decrement; R: may be any 8-bit registers (A, B, C, D, E, H and L).
M: Memory, whose address always present only in HL registers pairs

Description: The contents of the designated register or memory are decremented by 1 and
the results are stored in the same registers or memory. If the operand is a memory location,
that is indicated by the 16-bit address in the HL register.
Addressing Mode: Register For DCR R; Register Indirect For DCR M
(R /M Dec by 1)
Bytes: One Byte
Flags: S,Z,P, AC are modified to reflect the result of the operation. CY is not modified.
Combinations: DCR A, DCR B, DCR C, DCR D, DCR E, DCR H, DCR L

14) Syntax: DCX Rp

Where Rp: Registers Pairs may be any 16-bit registers pairs (BC, DE, HL & SP)
BC denotes by B, DE denotes by D, HL denotes by H and SP denotes by SP.

Description: The contents of the specified register pair are decremented by 1 and the results
are stored in the same register pair.
Addressing Mode: Register
(Rp Dec by 1)
Bytes: One Byte
Flags: No flags are affected Combinations: DCX B, DCX D, DCX H, DCX SP

Solve : ALP PROGRAMS

Solve: 1) Write a program to perform the following functions, and verify the output.
a) Load the number 8BH in register D. b) Load the number 6FH registers C.
c) Increment the content of registers C by one. d) Add the contents of registers C
and D and display the sum at memory location 1003H.

2) Write a program to perform the following: a) Load the number 30H in register B and
39H in Registers C. b) Subtract 39H from 30H. c) Display the sum at memory
location 1003H.
3) Write ALP to perform addition two Hexadecimal stores at the memory location
1000H and 1001H. Store the sum at the memory location 1003H.
4) Write ALP to perform Subtraction two Hexadecimal stores at the memory location
1000H and 1001H. Store the sum at the memory location 1003H.

LOGICAL OPERATIONS: A microprocessor is basically a programmable logic chip. It

can perform all the logic functions of the hard-wired logic through its instructions set. The
8085 instruction set includes a) Logic functions b) Rotates functions c) Compare Functions
I. Assume implicitly that the Accumulator is one of the operand (destination
register).

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II. Reset the CY flags.

III. Modify the Z, P, and S flags according to the data conditions of the results.
IV. Place the result in the accumulator.
V. Do not affect the contents of the source register.

LOGIC FUNCTIONS:
15) Syntax: ANA R or ANA M
Where ADD: ANded Accumulator, this instruction has only one operand and other operand
implicitly considered source as Accumulator. R: may be any 8-bit registers (A, B, C, D, E,
H and L). M: Memory, whose address always present only in HL registers pairs
Description: The contents of the operand (registers or memory) are ANDed to the contents
of the accumulator and the result is stored in the accumulator. If the operand is a memory
location, that is indicated by the 16-bit address in the HL register.
Addressing Mode: Register for ANA R and Register Indirect for ANA M

(A R / M) A 99 F
B ED
C
D E

H L
Bytes: ONE Byte Before

Flags: Reset the CY flags.

Modify the Z, P, and S.

Example : ANA B A 89 1 0 0 0 0 F
B ED
C
D E
D7 D6 D5 D4 D3 D2 D1 D0
H L
A 1 0 0 1 1 0 0 1
B 1 1 1 0 1 1 0 1 After

carry 0 1 0 0 0 1 0 0 1
Result
Sign

Combinations: 8 Instructions
ANA A; ANA B; ANA C; ANA D; ANA E; ANA H; ANA L and ANA M.

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16) Syntax: ANI 8-bit data

Where ADI: ANd Immediate, this instruction has only one operand and other operand
implicitly considered source as Accumulator. 8-bit data: ANDed any data immediate to
accumulator.
Description: The 8-bit data (in operand) are added to the contents of the accumulator, and
the result in placed in the accumulator.
Addressing Mode: Immediate
(A 8-bit data)
A 99 F
Bytes: Two Bytes B C

Flags: Reset the CY flags. D E

modify the Z, P, and S . H L

Example : ANI EDH Before Addition

A 89 1 0 000 F
B C

D E

H L

After Addition

Combinations: One Instruction

17) Syntax

Sr Instruction Addressing Bytes Flag Description

Reset the Same as AND
ORA A , ORA B , CY , Z, P,
and S are
ORA C , ORA D , modify. Input Input Output Y=
1 Register One A B A+B

ORA E , ORA H, 0 0 0
0 1 1

ORA L
1 0 1
1 1 1

Reset the
CY , Z, P,
2 Indirect One
ORA M and S are
modify.
Reset the
CY , Z, P,
3 ORI 8-bit data Immediate Two
and S are
modify.
XRA A , XRA B , Reset the
4 Register One CY , Z, P,

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XRA C , XRA D , and S are

modify. Input A Input B Output Y

XRA E , XRA H, 0 0 0
0 1 1

XRA L 1 0 1
1 1 0

Reset the
CY
5 Indirect One , Z, P, and
XRA M
S are
modify.
Reset the
CY , Z, P,
6 XRI 8-bit data Immediate Two
and S are
modify.
No flags Input A Output Y
are 0 1
affected 1 0
7 CMA Implied One

ROTATE OPERATIONS: This group has four instructions; two are for rotating left and
two are rotating right.
I. Assume implicitly that the accumulator is one of the operand (destination
register).
II. Modify the CY flag according the D7 and D0.
III. Place the result in the accumulator.

18) Syntax: RLC: Rotate Accumulator Left

Where RLC: This instruction has only one operand considered as Accumulator.
Description: The contents of accumulator shifted each bit to the adjacent left position i.e. Bit
D7 goes to D0 and Carry Flag.

Addressing Mode: Register / Implied

Bytes: One Byte
Flags: Only CY flag is modified.

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Example: Accumulator (A): D8

Accumulator (A) : B1

19) Syntax: RAL: Rotate Accumulator Left Through Carry

Where RAL: This instruction has only one operand considered as Accumulator.
Description: The contents of accumulator shifted each bit to the adjacent left position i.e.
Bit D7 goes to D0 and Carry Flag.

Addressing Mode: Register / Implied

Bytes: One Byte

Flags: Only CY flag is modified.

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Accumulator (A) : D8

Accumulator (A) : B0

20) Syntax: RRC: Rotate Accumulator Right

21) Syntax: RAR: Rotate Accumulator Right Through Carry
Where RAR/RRC: This instruction has only one operand considered as Accumulator.
Description: The contents of accumulator shifted each bit to the adjacent right position i.e.
Bit D0 goes to D7 and Carry Flag.
Addressing Mode: Register /
Implied
Bytes: One Byte
Flags: Only CY flag is modified.

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COMPARE OPERATIONS:
22) Syntax: CMP R or CMP M
Where CMP: CoMPare; R: may be any 8-bit registers (A, B, C, D, E, H and L).
M: Memory, whose address always present only in HL registers pairs
Description: The microprocessor compares a data byte (or Registers / Memory contents)
with the contents of the accumulator by subtracting the data byte from (A) and indicates
whether the data byte us >, < ,= with (A) by modifying the flags. However, the contents are
not modified. The 8085 instruction set has two types of Compare operations CMP and CPI.
CMP R/M : Compare (register / memory ) with Accumulator)

Addressing Mode: Register and Register Indirec

Bytes: One Byte
Flags: Specially Carry and Zero flags are affected.
Combinations: CMP A, CMP B, CMP C, CMP D, CMP E, CMP H and CMP L

CPI 8-bit data : Compare 8-bit data immediate with content of the accumulator.
Addressing Mode: Immediate
Bytes: One Byte
Flags: Specially Carry and Zero flags are affected.

 If (A) < (R/M/ 8-bit data) , The CY flag is Set and Zero flag is Reset.
 If (A) = (R/M/ 8-bit data) , The Zero flag is Set and Carry flag is Reset.
 If (A) > (R/M/ 8-bit data) , The CY flag and Zero flag are Reset.

BRANCHING OPERATIONS: The branch instructions are the most powerful instructions
because they allow the microprocessor to change the sequence of a program, either
conditionally or under certain conditions. The programming technique used to instruct the
microprocessor to repeat tasks is called Looping. Loops can be classified into two groups: a)
Continuous loop means repeat a task continuously unconditionally. b) Conditional loop
means repeats a task until certain data conditions are met i.e. conditionally.
The branch instructions are classified in four categories.
1) Jump Instructions.
2) Call instruction
3) Return instructions.
4) Restart instructions.

JUMP INSTRUCTION
1) Immediate Addressing Mode. 2) Three Bytes.
UNCONDITIONALLY JUMP CONDITIONALLY JUMP
Doesn’t depend on Flags Check the Flag and Make decision to jump or not to jump
register S Z P CY

Jump on Zero i.e. if Z =1

JZ 16-bit address
JMP 16-bit address
Jump on Not Zero i.e. if Z =0
JNZ 16-bit address

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Jump on Carry i.e. if CY =1

JC 16-bit address
Jump on Not Carry i.e. if CY = 0
JNC 16-bit address
Jump on Plus i.e. if S =0
JP 16-bit address
Jump on Minus i.e. if S =1
JM 16-bit address
Jump on Parity Odd i.e. if P =0
JPO 16-bit address
Jump on Parity Even i.e. if P =1
JPE 16-bit address

CALL SUBROUTINE INSTRUCTION

1) Immediate Addressing Mode. 2) Three Bytes.
UNCONDITIONALLY CALL CONDITIONALLY CALL
Doesn’t depend on Flags Check the Flag and Make decision to call or not to call
register S Z P CY

Call on Zero i.e. if Z =1

CZ 16-bit address
CALL 16-bit address
Call on Not Zero i.e. if Z =0
CNZ 16-bit address
Call on Carry i.e. if CY =1
CC 16-bit address
Call on Not Carry i.e. if CY = 0
CNC 16-bit address
Call on Plus i.e. if S =0
CP 16-bit address
Call on Minus i.e. if S =1
CM 16-bit address
Call on Parity Odd i.e. if P =0
CPO 16-bit address
Call on Parity Even i.e. if P =1
CPE 16-bit address

RETURN INSTRUCTION
1) Implied Addressing Mode. 2) One Byte.
CONDITIONALLY RETURN
UNCONDITIONALLY RETURN Check the Flag and Make decision to return or not to return
Doesn’t depend on Flags S Z P CY
register

RZ Return on Zero i.e. if Z =1

RET RNZ Return on Not Zero i.e. if Z =0

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RC Return on Carry i.e. if CY =1

RNC Return on Not Carry i.e. if CY = 0
RP Return on Plus i.e. if S =0
RM Return on Minus i.e. if S =1
RPO Return on Parity Odd i.e. if P =0
RPE Return on Parity Even i.e. if P =1

RESTART INSTRUCTION
1) Implied Addressing Mode. 2) One Byte.
RST instructions are one byte Call instruction that transfer the program execution to specific
location on page 00H. They are executed the same way as Call instruction.
RST 0 CALL 0000H
RST 1 CALL 0008H
RST 2 CALL 0010H
RST 3 CALL 0018H
RST 4 CALL 0020H
RST 5 CALL 0028H
RST 6 CALL 0030H
RST 7 CALL 0000H

MACHINE CONTROL OPERATIONS: The machine instructions are the most powerful
instructions because they allow the microprocessor to controls of machine such as stop
program, stop processing and wait etc.

23) Syntax: NOP

Description: No operation.
Addressing Mode: Implied
Bytes: One Byte
Flags: No flags are affected.

24) Syntax: HLT

Description: Stop processing and Wait
Addressing Mode: Implied
Bytes: One Byte
Flags: No flags are affected.

STACK, SUBROUTINE AND INTERRUPT

The STACK in an 8085 microprocessor system can be described as a set of memory locations
in the R/W memory, specified by a programmer in a main program. These memory locations
are used to store binary information (bytes) temporarily during the execution of a program.

A subroutine is group of instructions that perform a subtask to repeated occurrence. The

subroutine is written as a separate unit, apart from the main program.

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The interrupt process allows the microprocessor to respond to these external requests for
attention or service on demand basis and leaves the microprocessor free to perform other
tasks. The interrupt requests are classified in two categories a) Maskable interrupt and b)
Non-Maskable interrupt.

Solve Following : ALP PROGRAM

1) Two Decimal numbers are store at memory locations XX00H and XX01H. Write
ALP to perform the addition two numbers.
2) Sixteen bytes of data are stored in memory locations at XX50 to XX5FH. Write ALP
to transfer the entire the block of data to new memory locations starting at XX70H.
Data: 37, A2, F2, 82, 57, 5A, 7F, DA, E5, 8B, A7, C2, B8, 10, 19, 98.
3) Six bytes of data are stored in memory locations at XX50 to XX5AH. Write ALP to
transfer the data to the memory locations starting at XX80H to XX85H in the reverse
order. (e.g. the data 22H should be stored at XX85H and 37H at XX80H.
Data: 22, A5, B2, 99, 7F, 37
4) Write a program to add the following five data bytes stored in memory locations
starting at XX60H and display the sum. (The Sum does not generate a carry.) Use
register pair DE as a memory pointer to transfer a byte from memory into a register.
Data:1A, 32, 4F, 12, 27.
5) Six bytes of data are stored in memory locations starting at XX50H. Write ALP to add
all the data bytes. Use register B to save any carries generated while adding data
bytes. Store the sum at two consecutive memory locations XX70H and XX71H.
Data: A2, FA, DF, E5, 98, 8B.
6) A set of ten reading are stored in memory locations starting at XX50H. Write ALP to
check each reading, reject all negative readings and add all positive readings. Use
register B to save any carries generated while adding data bytes. Store the sum at two
consecutive memory locations XX70H and XX71H.
Data: 28, D8, C2, 21, 24, 30, 2F, 19, F2, 9F
7) A set of ten numbers are stored in memory locations starting at XX50H. Write ALP to
check each reading, reject all odd numbers and add all even numbers. Use register
B to save any carries generated while adding data bytes. Store the sum at two
consecutive memory locations XX70H and XX71H.
Data: 28, D8, C2, 21, 24, 30, 2F, 19, F2, 9F
8) A set of readings are stored in memory locations starting at XX50H. The end of the
data strings is indicated by the data bytes 00H. Write ALP to add the set of readings.
Use register B to save any carries generated while adding data bytes. Store the sum at
two consecutive memory locations XX70H and XX71H.
Data: 32, 52, F2, A5, 00
9) Two hexadecimal numbers are store at memory locations XX00H and XX01H. Write
ALP to find the greater of two numbers.
10) Two hexadecimal numbers are store at memory locations XX00H and XX01H. Write
ALP to multiplication of two numbers.
11) Two hexadecimal numbers are store at memory locations XX00H and XX01H. Write
ALP to find the division of two numbers.
12) A set of eight readings are stored in memory locations starting at XX50H. Write ALP
to search whether a byte 40H exists in the set. If it does, stop checking and display its

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memory locations at two consecutive memory locations XX70H and XX71H.;

otherwise output FFH.
Data: 48, 32, F2, 38, 37, 40, 82, 8A.
13) A set three of numbers are stored in memory locations starting at XX50H. Write ALP
to sort the numbers in ascending order using Bubble sort method.
Data:87, 56, 42
14) A set 10 current reading store at 2FFFH. Write an assembly language program to
count the number of times the data ADH is found in a block locations starting from
3000H. Store the result in location 2000H.
15) An 8-bit Hexadecimal number store in location 2000H. Write an ALP to count how
many times 1’s present in hexadecimal numbers. Store the count in memory location
2001H. i.e. A= 10111101 Ans: 6 times 1’s

16) Write an ALP to generate the Fibbonacci series for first eight numbers. Store the
series in a memory block starting from C000H. ( 00 01 01 02 03 05 08 0D)

17) Write an ALP to separate two nibbles of an 8-bit number stored in memory locations
1500H. Add these two nibbles and store the sum in memory at BABAH.

18) Write an ALP to find the largest number in a series. The length of the series is stored
at 2500H and the numbers are stored from 2501H. Store the result at 2400H.

19) A hexadecimal number is stored at location C000H. Write an ALP to interchange its
digits. The new number is to be stored at C001H. Add original number with new
number and store the result at location C002H.
20) Write an ALP to separate two nibbles of an 8-bit number stored in memory locations
1500H. Multiply these two nibbles and store the result in memory.

OTHER INSTRUCTION FROM ALL GROUPS:

(Important for Exam point of View)

Syntax: ACI 8-bit data

Description: The 8bit data (operand) and the carry flag are added to the contents of the
accumulator, and result is stored in the accumulator.
 Group: Arithmetic
 Addressing Mode: Immediate
 Bytes: Two Bytes
 Flags: All flags are affected.
 Example: Assuming the accumulator contains 26H and the previous operation has set the
carry flag, add byte 57H to the accumulator.
1 1 1
A: 57H 0 1 0 1 0 1 1 1
 Data 26H 0 0 1 0 0 1 1 0
 Carry 0 0 0 0 0 0 0 1

A: 7E 0 1 1 1 1 1 1 0

After addition the previous carry flag is cleared.

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S Z AC P CY
0 0 0 1 0

1) Syntax: ADC R or ADC M

Where ADD: Addition with Carry, this instruction has only one operand and other operand
implicitly considered source as Accumulator. R: may be any 8-bit registers (A, B, C, D, E,
H and L). M: Memory, whose address always present only in HL registers pairs
Description: The contents of the operand (registers or memory) and the carry flag are added
to the contents of the accumulator and the result is stored in the accumulator. If the operand is
a memory location, that is indicated by the 16-bit address in the HL register.
Addressing Mode: Register for ADD R and Indirect for ADD M.
(A R / M)
A 99 F
Group: Arithmetic B ED
C
Bytes: ONE Byte
Flags: All flags are modifying. D E

H L
Before Addition with carry

Example: ADC B A 87 1 0 1 1 1 F
B ED
D7 D6 D5 D4 D3 D2 D1 D0 C
Carry 1 1 1 1 1 D E
A:1 0 0 1 1 0 0 1
B :1 1 1 0 1 1 0 1 H L
Previous Carry : 0 0 0 0 0 0 0 1 After Addition with carry

carry 1 1 0 0 0 0 1 1 1
Result 87
Sign

FLAGS REGISTER:

1 0 1 1 1

Combinations:
ADC; ADC B; ADC C; ADC D; ADC E; ADC H; ADC L and ADC M.

2) Syntax: CMC
Description: The carry flag is complemented.
 Group: Arithmetic

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 Addressing Mode: Implied

 Bytes: One Byte
 Flags: The carry flag is modified. No other flags are affected.

3) Syntax: STC
Description: The carry flag is Set.
 Group: Arithmetic
 Addressing Mode: Implied
 Bytes: One Byte
 Flags: The carry flag is modified. No other flags are affected.

4) Syntax: DAA (Decimal Adjustment Accumulator)

Description: The contents of the accumulator are changed from a binary value to two 4-bit
binary-coded decimal digits.
 Group: Arithmetic A 99 F
 Addressing Mode: Implied B 98
C
 Bytes: One Byte D E
 Flags: All flags are affected.
H L
Before

D7 D6 D5 D4 D3 D2 D1 D0 A 97 1 0 1 01 F
Carry 1 1 B 98
C
A:1 0 0 1 1 0 0 1
B :1 0 0 1 1 0 0 0 D E

H L
carry 1 0 0 1 1 0 0 0 1
Result
(A)

After
S2(3) S1(1)
Sign

Now Execute DAA instruction:

Condition Action on result

If S1 > 9 or AC = 1 Add 06 i.e. 0 0 0 0 0 1 1 0

If S2 > 9 or CY = 1 Add 60 i.e. 0 1 1 0 0 0 0 0

If S2 > 9 or CY = 1 / S1 > 9 or AC = 1 Add 66 i.e. 0 1 1 0 0 1 1 0

**According the third Condition: Add 66 to Final result and get Decimal Result.
1 1
Result 0 0 1 1 0 0 0 1 99
 66 0 1 1 0 0 1 1 0 98
1 0 0 1 0 1 1 1 197
carry 1 S2(9) S1(7)

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5) Syntax: DAD Rp
Where Rp: Registers Pairs may be any 16-bit registers pairs (BC, DE, HL and SP)
BC denotes by B, DE denotes by D, HL denotes by H and SP denotes by SP.
Description: The 16-bit contents of the specified register pair are added to the contents of the
HL register pair and the sum is saved in the HL registers pair. The content of the source
register pair are not altered. HL = HL + Rp
 Group: Arithmetic A 1 0 1 01 F
 Addressing Mode: Register B
 Bytes: One Byte C
02 12
 Flags: If the result is larger than 16-bit the D E
cy flag is set. H 02 42 L

Example: DAD D (HL = HL + DE) Before

A 1 0 1 01
1 1 F
B
0000 0010 0001 0010 C
0000 0010 0100 0010 D
02 12
E
0000 0100 0101 0100
H 04 54 L
Combinations: DAD B, DAD D, DAD H, DAD SP After
6) Syntax: DI
Description: The interrupt Enable Flip-flop is reset and all the interrupts except the TRAP
are disables.
 Group: Machine Control
 Addressing Mode: Implied
 Bytes: One Byte
 Flags: No flags are affected.
7) Syntax: EI
Description: The interrupt Enable Flip-flop is set and all the interrupts are Enable.
 Group: Machine Control
 Addressing Mode: Implied
 Bytes: One Byte
 Flags: No flags are affected.

8) Syntax: IN 8-bit Port address

Description: The contents of the input port designated in the operand and read and loaded
into the accumulator.
 Group: Machine Control
 Addressing Mode: Direct
 Bytes: Two Bytes
 Flags: No flags are affected.
9) Syntax: OUT 8-bit Port address
Description: The contents accumulator is written into output port designated in the operand.
 Group: Machine Control
 Addressing Mode: Direct
 Bytes: Two Bytes

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 Flags: No flags are affected.

10) Syntax: LDAX Rp
Where Rp: Registers Pairs may be any 16-bit registers pairs (BC, DE).
BC denotes by B, DE denotes by D.
Description: The contents of the designated register pair point to a memory location. This
instruction copies the contents of that memory location into the accumulator.

A C3 F
B C Memory Address Data
2000 A1
D E 2001 C3
20 01
2002 F4
H L 2004 54

 Group: Data Transfer (copy)

 Addressing Mode: Register Indirect
 Bytes: One Byte
 Flags: No flags are affected.

Example : LDAX D
Combination: LDAX B, LDAX D

11) Syntax: STAX Rp

Where Rp: Registers Pairs may be any 16-bit registers pairs (BC, DE).
BC denotes by B, DE denotes by D.
Description: the contents the accumulator are copies into the memory location specified by
the contents of the operand (register pair).
 Group: Data Transfer (copy)
 Addressing Mode: Register Indirect
 Bytes: One Byte A C3 F
 Flags: No flags are affected. B C Memory Address Data
2000 A1
Example : STAX D D
20 01 E 2001 C3
2002 F4
H L 2004 54

Combination: STAX B, STAX D

12) Syntax: LHLD 16-bit address
Description: The instruction copies the contents of the memory location pointed out by the
16-bit address in register L and copies the contents of the next memory location in register H.
The contents of source memory locations are not altered.

 Group: Data Transfer (copy) A F

 Addressing Mode: Direct B C
 Bytes: Three Bytes D Memory Address Data
 Flags: No flags are affected. E
2000 A1
H C3 A1
L 2001 C3
2002
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 Computer Science ( D9) XII - Paper –II

Example: LHLD 2000H

13) Syntax: SHLD 16-bit address

Description: The instruction copies the contents of register L in the memory location pointed
out by the 16-bit address in the operand and the contents of register H are stored in the next
memory location by incrementing the operand. The contents of source registers HL are not
altered.

 Group: Data Transfer (copy)

 Addressing Mode: Direct
 Bytes: Three Bytes A F
 Flags: No flags are affected. B C
D E Memory Address Data
50 00 2000 AA
H
Example: SHLD 2002H L 2001 CC
2002 00
2004 50

14) Syntax: PCHL

Description: The contents of register H and L are copied into the Program Counter (PC). The
contents of H are placed as a high order byte and of L as low order byte.
 Group: Branching
 Addressing Mode: Implied A F A
 Bytes: One Byte B B
C
 Flags: No flags are affected.
D E D

H 50 00 H 50 00
L
Example: PCHL PC PC
2000 5000
Before After
15) Syntax: SPHL
Description: The contents of register H and L are copied into the Stack Pointer registers. The
contents of H are placed as a high order byte and of L as low order byte.

 Group: Machine control

 Addressing Mode: Implied A
F
A
 Bytes: One Byte B B
C
 Flags: No flags are affected.
D D
E
H 50 00 H 50 00
L
Example: SPHL PC PC

SP SP
1000 5000
Before After

16) Syntax: XCHG

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Description: The contents of register H exchange with the contents of register D and the
content of register L are exchanged with content of register E.
 Group: Data transfer (copy)
 Addressing Mode: Implied
 Bytes: One Byte A F A F
 Flags: No flags are affected. B B C C

Example: XCHG D
40 20 E D
50 10 E
H 50 10 H 40 20
17) Syntax: XTHL L L
Before After
Description: The contents of register L exchange with the stack memory pointed out by the
contents of the stack pointer register. The contents of register H are exchanged with the next
stack pointer location (SP+1). However the contents of the stack pointer register are not
altered.
 Group: Machine control
A
 Addressing Mode: Implied F 4095
 Bytes: One Byte B C
4096
 Flags: No flags are affected. D E 4097 50
H 60 10
Example: XTHL L 4098
40

SP Stack Memory
4097

18) Syntax: PUSH Rp

Where Rp: Registers Pairs may be any 16-bit registers pairs (BC, DE, HL, PSW). BC
denotes by B, DE denotes by D, HL denotes by H, PSW denotes by PSW. PSW: Program
Status Word i.e. the register pair (AF)
Description: The contents of register pair designated in the operand are copied into the stack
in the following sequence. The stack pointer register is decremented and the contents of the
high order registers (A, B, D, H) are copied into that location. The stack pointer register is
decremented again and the contents of the low order register (C, E, L, F) are copied to that
location.
A F
 Group: Machine control B 32 57
4095

C
Addressing Mode: Register 4096
 Bytes: One Byte D E 4097
 Flags: No flags are affected. H xx
L 4098
SP Stack Memory
Example : PUSH B 4098 Before

A F 4095
B 32 57 57
C
4096
D E 4097 32
H L xx
4098
SP Stack Memory
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 Computer Science ( D9) XII - Paper –II

Combinations: PUSH PSW, PUSH B, PUSH D, PUSH H

19) Syntax: POP Rp
Where Rp: Registers Pairs may be any 16-bit registers pairs (BC, DE, HL, PSW). BC
denotes by B, DE denotes by D, HL denotes by H, PSW denotes by PSW. PSW (Program
Status Word i.e. the register pair AF)
Description: The contents of memory location pointed out by the stack pointer register are
copied to low order register (C, E, L, F) of the operand. The stack pointer register is
incremented by 1 and the contents of that memory location are copied to the high order
registers (A, B, D, H) of the operand. The stack pointer register is again incremented by 1.
A F 4095
 Group: Machine control B C 57
 Addressing Mode: Register 4096
 Bytes: One Byte D E 4097 32
 Flags: No flags are affected. H L xx
4098

Example : POP D SP
4096 Before
Stack Memory

A F 4095
B C
4096
32 57
D E 4097
H L xx
4098
SP Stack Memory
4098 After

Combinations: POP PSW, POP B, POP D, POP H

20) Syntax: RIM

Description: This is multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5
and to read serial data input bit. The instruction loads eight bits in the accumulator with the
following interpretations.

 Group: Machine control

 Addressing Mode: Implied
 Bytes: One Byte
 Flags: No flags are affected.
Serial input data bit Interrupt
Interrupt masked
21) Syntax: SIM pending if If bit = 1
Interrupt enable
Bit = 1 Flip-flop is set
If bit = 1
Description: This is multipurpose instruction and used to implement the 8085 interrupts 7.5,
6.5, 5.5 and serial data output bit. The instruction loads eight bits in the accumulator with the
following interpretations.

 Group: Machine control

 Addressing Mode: Implied

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 Bytes: One Byte

 Flags: No flags are affected.
Reset RST 7.5
flip-flop masks
Serial Output Data if D4 =1 Interrupt
If bit= 1
Mask set
Serial data Enable if
Enable D3 = 1
1 = Enable
0= Disable

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