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Unit No. 3: Introduction To Intel X Introduction To Intel X-86 Family 86 Family

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Unit No. 3: Introduction To Intel X Introduction To Intel X-86 Family 86 Family

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helps7025
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Computer Science ( D9) XII - Paper –II

Unit No. 3: INTRODUCTION TO INTEL X


X-86
86 FAMILY

X-86 Family Microprocessor


80586
Attribute 8086 80286 80386 80486
64 bits
Data Bus 16 bits 16 bits 32 bits 32 bits
32 bits
Address Bus 20 bits 24 bits 32 bits 32 bits
Internal
Coprocessor External External External External
4 GB
Memory Address 1 MB 16 MB 4 GB 4 GB
1993
Manufacture year 1978 1982 1985 1991

The Pentium processor has a 32 bits address bus and a 64 bits data bus and it designed to
operate from 60 MHz to 233 MHz. The Pentium processor has some enhancement features
1) On Chip Cache: The Pentium processor has two 8K byte of cache memory on the
chip, one used for code and other is used for data.
2) Branch Predication:: This is a mainframe technique implemented in this processor to
improve
rove the performance. In this technique the most likely instructions to be execute
is predetermined.
3) Dual Pipelining: The Pentium processor has two execution units with dual pipelined
architecture; thus it is able to execute two instruction simultaneously per clock cycle
and achieve a high level of performance.
4) 64 bit Data bus: The Pentium processor has 64 bits data bus, which increase the
processing speed and also support multiprocessing applications.

PROGRAMMING MODEL OF X
X-86
86 MICROPROCESSOR
MICROPROCES

16-bit Registers

Page 39
Computer Science ( D9) XII - Paper –II

The original Intel 8086 and 8088 have fourteen 16-bit registers. Four of them (AX, BX, CX,
DX) are general-purpose registers. Each can be accessed as two separate bytes (thus BX's
high byte can be accessed as BH and low byte as BL). There are two pointer registers. SP
points to the top of the stack and BP (base pointer) which is used to point at some other place
in the stack, typically above the local variables. Two registers (SI and DI) are for array
indexing. Four segment registers (CS, DS, SS and ES) are used to form a memory address.
The instruction pointer (IP) points to the next instruction that will be fetched from memory
and then executed.
32-bit Registers
With the advent of the 32-bit 80386 processor, the 16-bit general-purpose registers, base registers,
index registers, instruction pointer, and FLAGS register, but not the segment registers, were expanded
to 32 bits. This is represented by prefixing an "E" (for Extended) to the register names in x86
assembly languages. Thus, the AX register corresponds to the lowest 16 bits of the new 32-bit EAX
register, SI corresponds to the lowest 16 bits of ESI, and so on. Two new segment registers (FS and
GS) were added. With a greater number of registers, instructions and operands, the machine code
format was expanded. To provide backward compatibility, segments with executable code can be
marked as containing either 16-bit or 32-bit instructions. BX/EBX: base index (ex: arrays)

 CX/ECX: counter
 DX/EDX: data/general
 SI/ESI: "source index" for string operations.
 DI/EDI: "destination index" for string operations.
 SP/ESP: stack pointer for top address of the stack.
 BP/EBP: stack base pointer for holding the address of the current stack frame.
 IP/EIP: instruction pointer. Holds the program counter, the current instruction
address.

FLAG REGISTER OF X-86 FAMILY


The FLAGS register is the status register in Intel x86 microprocessors that contains the
current state of the processor. This register is 16 bits wide. Its successors, the EFLAGS
registers are 32 bits .

31------------------ 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved AC VM RT xx NT IOPL O D I T S Z XX A XX P xx C

Bit 0 = Where :CARRY Bit 12 = IOPL : I/O PRIVILEGE


Bit 1 = XX :RESERVED Bit 13 = IOPL : I/O PRIVILEGE
Bit 2 = P : PARITY Bit 14 = NT : NESTED TASK
Bit 3 = XX : RESERVED Bit 15 = XX : RESERVED
Bit 4 = A : AUXILIARY CARRY Bit 16 = RF : RESUME
Bit 5 = XX: : RESERVED Bit 17 = VM : VIRTUAL 8086 MODE
Bit 6 = Z : ZERO Bit 18 = AC : ALIGNMENT CHECK
Bit 7 = S : SIGN
Bit 8 = T : TRAP
Bit 9 = I : INTERRUPT
Bit 10 = D : DIRECTION
Bit 11 = O : OVERFLOW

Page 40

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