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Ejercicios Basicos Combinacional VHDL Solucion

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0% found this document useful (0 votes)
22 views7 pages

Ejercicios Basicos Combinacional VHDL Solucion

Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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1.

Tabla de verdad
library ieee;
use ieee.std_logic_1164.all;

entity tabla_verdad is
port (
A,B,C: in std_logic;
X,Y: out std_logic
);
end tabla_verdad;

architecture procesos of tabla_verdad is


-- Agrupamos las entradas en una sola señal
signal temp: std_logic_vector(2 downto 0);
begin

temp <= A & B & C;

process(temp)
begin
case temp is
when "000" =>
X <= '0'; Y <= '1';
when "001" =>
X <= '1'; Y <= '0';
when "010" =>
X <= '1'; Y <= '0';
when "011" =>
X <= '0'; Y <= '1';
when "100" =>
X <= '0'; Y <= '1';
when "101" =>
X <= '0'; Y <= '0';
when "110" =>
X <= '1'; Y <= '0';
when "111" =>
X <= '1'; Y <= '1';
when others =>
X <= '-'; Y <= '-';
end case;

end process;

end procesos;

architecture sentencias_concurrentes of tabla_verdad is


-- Agrupamos las entradas en una sola señal
signal temp: std_logic_vector(2 downto 0);
begin

temp <= A & B & C;

X <= '1' when temp="001" or temp="010" or temp="110" or temp="111" else


'0';

Y <= '1' when temp="000" or temp="011" or temp="100" or temp="111" else


'0';

end sentencias_concurrentes;
2.Decodificador de 3 a 8

library ieee;
use ieee.std_logic_1164.all;

entity DEC_3_8 is
port (
E: in std_logic_vector(2 downto 0);
En: in std_logic;
S: out std_logic_vector(7 downto 0)
);
end DEC_3_8;

architecture funcional of DEC_3_8 is


begin

process(E,En)
begin
if En='0' then
S <= (others=>'0');
else
case E is
when "000" =>
S <= "00000001";
when "001" =>
S <= "00000010";
when "010" =>
S <= "00000100";
when "011" =>
S <= "00001000";
when "100" =>
S <= "00010000";
when "101" =>
S <= "00100000";
when "110" =>
S <= "01000000";
when "111" =>
S <= "10000000";
when others =>
S <= (others=>'-'); -- Indiferente
end case;
end if;
end process;

end funcional;
3.Decodificador 7 segmentos
library ieee;
use ieee.std_logic_1164.all;

entity DEC_7_SEG is
port (
D: in std_logic_vector(3 downto 0);
segA: out std_logic;
segB: out std_logic;
segC: out std_logic;
segD: out std_logic;
segE: out std_logic;
segF: out std_logic;
segG: out std_logic
);
end DEC_7_SEG;

architecture funcional of DEC_7_SEG is


signal temp: std_logic_vector(6 downto 0);
begin

segA <= temp(6);


segB <= temp(5);
segC <= temp(4);
segD <= temp(3);
segE <= temp(2);
segF <= temp(1);
segG <= temp(0);

process(D)
begin
case D is -- abcdefg
when "0000" => temp <= "1111110"; -- 0
when "0001" => temp <= "0110000"; -- 1
when "0010" => temp <= "1101101"; -- 2
when "0011" => temp <= "1111001"; -- 3
when "0100" => temp <= "0110011"; -- 4
when "0101" => temp <= "1011011"; -- 5
when "0110" => temp <= "1011111"; -- 6
when "0111" => temp <= "1110000"; -- 7
when "1000" => temp <= "1111111"; -- 8
when "1001" => temp <= "1111011"; -- 9
when "1010" => temp <= "1110111"; -- A
when "1011" => temp <= "1001111"; -- B
when "1100" => temp <= "1001110"; -- C
when "1101" => temp <= "0111100"; -- D
when "1110" => temp <= "1001111"; -- E
when others => temp <= "1000111"; -- F
end case;
end process;

end funcional;
4.Comparador

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity COMP8 is
port (
A,B: in unsigned(7 downto 0); -- Declarar signed para comparación con signo
Mayor,Menor,Igual: out std_logic
);
end COMP8;

architecture funcional of COMP8 is


begin

Mayor <= '1' when A > B else '0';


Menor <= '1' when A < B else '0';
Igual <= '1' when A = B else '0';
-- alternativa
-- Igual <= not(Mayor or Menor);

end funcional;
architecture secuencial of COMP8 is

begin

process(A, B)
begin
if A > B then
Mayor <= '1';
Menor <= '0';
Igual <= '0';
elsif A < B then
Mayor <= '0';
Menor <= '1';
Igual <= '0';
else
Mayor <= '0';
Menor <= '0';
Igual <= '1';
end if;
end process;
end secuencial;

architecture preasignacion_por_defecto of COMP8 is


begin

process(A, B)
begin
Mayor <= '0';
Menor <= '0';
Igual <= '0';
if A > B then
Mayor <= '1';
elsif A < B then
Menor <= '1';
else
Igual <= '1';
end if;
end process;
end preasignacion_por_defecto;
5.Generador de paridad

library ieee;
use ieee.std_logic_1164.all;

entity PARGEN is
port (
D: in std_logic_vector(7 downto 0);
P: out std_logic
);
end PARGEN;

architecture funcional of PARGEN is


begin

P <= D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor D(2) xor D(1) xor D(0);

end funcional;
6.Decodificador de Direcciones
library ieee;
use ieee.std_logic_1164.all;

entity ADDR_DEC is
port (
Addr: in std_logic_vector(15 downto 0);
Enable: out std_logic_vector(4 downto 0)
);
end ADDR_DEC;

architecture funcional of ADDR_DEC is


begin

process(Addr)
begin
-- smallest block is 8k (13 bit) => 16-13=3 bits to decode
case Addr(15 downto 13) is
when "000" => --Block 0 (8k)
Enable <= "00001";
when "001" => --Block 1 (8k)
Enable <= "00010";
when "010" | "011" => --Block 2 (16k)
Enable <= "00100";
when "100" | "101" => --Block 3 (16k)
Enable <= "01000";
when "110" | "111" => --Block 4 (16k)
Enable <= "10000";
when others =>
Enable <= "-----";
end case;
end process;

end funcional;

7.Sumador-Restador

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ADDSUB is
port (
A,B: in signed(15 downto 0);
Sel: in std_logic;
R: out signed(15 downto 0);
Ov: out std_logic
);
end ADDSUB;

architecture funcional of ADDSUB is


signal result: signed(15 downto 0); -- Cannot read R
signal op1,op2: signed(15 downto 0); -- Need to chech overflow
begin

op1 <= A;
op2 <= B when Sel='0' else -B;
result <= op1+op2;

R <= result;
-- Overflow if two operands have same sign and result the opposite
Ov <= '1' when (op1(15)='1' and op2(15)='1' and result(15)='0') or
(op1(15)='0' and op2(15)='0' and result(15)='1') else
'0';

end funcional;
8.ALU
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ALU8 is
port (
A,B: in std_logic_vector(7 downto 0);
Cin: in std_logic;
Sel: in std_logic_vector(1 downto 0);
M: in std_logic;
Y: out std_logic_vector(7 downto 0);
Cout: out std_logic;
Ov: out std_logic
);
end ALU8;

architecture funcional of ALU8 is


signal lresult: std_logic_vector(7 downto 0);
signal aresult: signed(7 downto 0);
begin

Y <= lresult when M='0' else std_logic_vector(aresult);


Ov <= '1' when M='1' and (Sel="01" or Sel="10") and
((A(7)='1' and B(7)='1' and aresult(7)='0') or
(A(7)='0' and B(7)='0' and aresult(7)='1')) else
'0';

process(Sel,A,B)
begin
-- Logical operation
case Sel is
when "00" => lresult <= A and B; -- Bitwise AND
when "01" => lresult <= A or B; -- Bitwise OR
when "10" => lresult <= not A; -- Bitwise NOT
when "11" => lresult <= A xor B; -- Bitwise XOR
when others => lresult <= (others=>'-');
end case;
end process;

process(Sel,A,B,Cin)
begin
-- Arithmetical operation
Cout <= '0';
case Sel is
when "00" =>
if Cin='0' then
aresult <= signed(A) + signed(B);
else
aresult <= signed(A) + signed(B) + 1;
end if;
when "01" =>
if Cin='0' then
aresult <= signed(A) - signed(B);
else
aresult <= signed(A) - signed(B) - 1;
end if;
when "10" =>
aresult <= signed(A(6 downto 0)&'0'); -- SHL
Cout <= A(7);
when "11" =>
aresult <= signed(A);
when others =>
aresult <= (others=>'-');
end case;
end process;

end funcional;

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