10.

REALIZATION OF HALF ADDER USING DATA FLOW, STRUCTURAL,

BEHAVIORAL MODELING, AND TEST BENCH

10.1 Objective

To design and implement a Half Adder using different modeling techniques in Verilog: Data
Flow, Structural, and Behavioral modeling, and to verify the functionality of the Half Adder
using a test bench.

10.2 Equipment and Software Requirement

• Computer with Windows/Linux operating system

• Softwares: Synthesis tool: Xilinx ISE
Simulation tool: ModelSim Simulator

10.3 Theory

10.3.1 Verilog Hardware Description Language (HDL)

A Hardware Description Languages (HDL)s is a specialized computer language used to

describe the structure, design, and operation of electronic circuits, particularly digital logic
circuits. HDLs are used for designing complex digital systems such as microprocessors,
memory chips, and digital signal processors. The two most widely used HDLs are:

i.) Verilog HDL

ii.) VHDL -VHSIC (Very High Speed Integrated Circuit) HDL

Verilog HDL (Hardware Description Language) is one of the primary languages used
for digital design and verification. Developed in the mid-1980s by Gateway Design
Automation, Verilog has become a standard for electronic design automation (EDA). It was
later standardized as IEEE 1364 and has evolved to include features that make it suitable for
system-level design and verification. Verilog enables designers to describe a digital system at
various levels of abstraction and versatile modelling styles, making it easier to design, test, and
debug. Its event-driven simulation capabilities, modular design support, and rich syntax make
it an essential language for modern digital system development.
Modeling Styles in Verilog

In Verilog, three primary types of modeling are employed:

i.) Dataflow modeling

ii.) Structural modeling

iii.) Behavioral modeling

Each model serves a different purpose and provides a unique abstraction level, offering various
methods to describe the functionality and structure of digital circuits.

i.) Dataflow modeling

Dataflow modeling in Verilog emphasizes the flow of data through the system. It is used
to describe the logic by specifying how data moves from inputs to outputs using continuous
assignments. It focuses on the relationship between inputs and outputs without explicitly
detailing the hardware structure. This model is particularly useful for describing combinational
logic. In dataflow modeling, the key construct is the `assign` statement, which allows the
designer to express the logic in terms of Boolean equations. These equations represent the
relationships between inputs and outputs, making it easier to translate mathematical
expressions directly into Verilog code.

Example

module and_gate_d(output Y, input A, B);

assign Y = A & B;
endmodule

This example shows a simple AND gate, where the output `Y` is the logical AND of
inputs `A` and `B`. The ‘module’ command tells the compiler that we are creating something
which has some inputs and outputs. ‘and_gate_d’ is the identifier. The `assign` statement
continuously evaluates the expression and updates the output whenever any input changes.
‘endmodule’ terminates the module.

Dataflow modeling is efficient for simple combinational circuits but becomes complex
for larger designs with intricate timing and control requirements.
ii.) Structural modeling

Structural modeling focuses on the physical interconnection of components within a

system. It describes the circuit in terms of modules and instances, reflecting the actual hardware
layout. It describes how different hardware elements (like gates and flip-flops) are connected
to form the complete circuit. This model is analogous to a schematic diagram, where various
components (gates, flip-flops, etc.) are connected to form the complete design.

Structural modeling employs instances of lower-level modules to build higher-level

systems, making it highly hierarchical. It is suitable for describing the exact hardware
configuration, ensuring that the design closely matches the intended implementation.

Example

module and_gate_s(output Y, input A, B);

and(Y, A, B);
endmodule

In this example ‘and’ is the operation performed on A, B, to get output Y. Verilog has
this functionality to describe the circuit at the gate level.

Structural modeling provides a clear view of the circuit's physical composition but can
be tedious for large designs due to the extensive detail required.

iii.) Behavioral modeling

Behavioral modeling describes the functionality of the system in terms of algorithms and
high-level constructs, abstracting away the physical implementation details. This style uses
constructs like ‘always’ blocks, ‘if-else’ statements, and ‘case’ statements to describe the
functionality. Behavioral modeling abstracts the hardware to a greater extent and focuses on
the functionality rather than the physical connections or data flow. It uses procedural statements
within `always` blocks to define the behavior over time, making it suitable for both
combinational and sequential logic.

Behavioral modeling is the most abstract form of modeling and allows designers to focus
on the desired functionality without worrying about the hardware specifics. This model is often
used in the initial stages of design for simulation and verification purposes.
 Example

module and_gate_behavioral(output reg Y, input A, B);

always @ (A or B) begin
if (A == 1'b1 & B == 1'b1) begin
Y = 1'b1;
end
else
Y = 1'b0;
end
endmodule

In this example, level of abstraction is behavioral level, hence use ‘reg’ datatype in the
output ports. The reg data object holds its value from one procedural assignment statement to
the next. if (A == 1'b1 & B == 1'b1) states that if both A and B are 1, then Y has to be 1, else
0.

Behavioral modeling provides high-level abstraction and simplicity but might not offer
insights into the actual hardware structure, which can be critical for detailed hardware design
and optimization.

Importance of Testbenches

In Verilog, testbenches are essential for verifying the correctness of the design. A
testbench is a piece of code written to apply stimuli (input signals) to the design under test
(DUT) and observe the outputs to check if they match the expected results. Testbenches help
identify and fix errors early in the design process. They are not synthesized into hardware but
are used in simulations to validate the design.

10.3.2 Half Adder

A Half Adder is a combinational circuit that performs the addition of two binary digits.
It has two inputs and two outputs. The inputs are the two binary digits to be added, and the
outputs are the Sum and the Carry.

Fig 10.1 Block Schematic of Half Adder

 Table 1 Truth Table of Half Adder

Input Output
A B Sum Carry
0 0 0 0
0 1 1 0
Sum = 𝐴̅𝐵 + 𝐴𝐵̅ Carry = 𝐴𝐵
1 0 1 0
= 𝐴⨁𝐵
1 1 0 1 Fig 10.2 Boolean Expression of Half Adder

Fig 10.3 Logic Diagram of Half Adder

10.4 Procedure for Verilog Simulation of Digital Circuits using Xilinx 7.1e ISE

Step 1: Open Xilinx ISE 7.1

• Launch the Xilinx ISE software

Step 2: Create a New Project

• Click on File → New Project.

• In the New Project wizard:

• Project Name: Enter a project name.

• Location: Choose or create a folder for the project.

• Top-Level Module Type: Select HDL.

• Click Next.

• Set the following properties:

• Device Family: Select your FPGA family (e.g., Spartan3E).

 • Device: Select the device you are using (e.g., xc3s100e).

• Package: Select the package type (e.g., vq100).

• Speed: Select the speed grade (e.g., -4).

• Top-Level Module Type: HDL

• Synthesis Tool: XST(VHDL/Verilog)

• Simulator: ModelSim

• Generated Simulation Language: Verilog

• Click Next.

Step 3: Create a Verilog Source File

• Select New Source.

• Choose Verilog Module.

• Enter a name for your Verilog file and click Next.

• Define the module’s inputs and outputs (you can also edit this later).

• Click Next and then Finish.

Step 4: Write Your Verilog Code

• The newly created Verilog file will open in the editor.

• Write Verilog code in the HDL editor.

Step 5: Save the File

• Click File → Save to save the code.

Step 6: Verify Syntax

• In the left pane, under the Process for Source, expand the Synthesize-XST menu by
clicking the "+" icon.

• Double-click Check Syntax to check for syntax errors in code.

Step 7: View the RTL Schematic

 • Double-click View RTL Schematic to see the RTL schematic.

• Explore the schematic by double-clicking the diagram for more details.

Step 8: View the Synthesis Report

• Double-click View Synthesis Report under Synthesize-XST to review the synthesis

results, including resource utilization, timing analysis, and any warnings or errors.

Step 9: Simulate the Design

• Expand the Design Utilities section under Process for Source.

• Click Launch ModelSim Simulator (integrated with ISE) to start the simulation
process.

Step 10: Assign Input Values

• In the ModelSim simulator:

• Right-click on each input variable (e.g., A, B).

• Choose Force from the context menu and assign values (1 or 0).

• Repeat for all input variables.

Step 11: Execute the Simulation and Analyze Results

• Click the Run icon to start the simulation.

• Observe the waveform window to see how inputs affect the outputs.

• Check the waveforms to ensure the design is functioning as expected.

10.4.1 Steps to Create and Simulate a Test Bench in Xilinx 7.1e ISE

Step 1: Create a New Test Bench File

• In the Project Navigator, right-click on choose the Verilog module you want to create
a test bench for from the list of existing modules and select New Source.

• Choose Verilog Test Fixture, enter a name for your test bench module and click Next.

• Click Finish to create the test bench file.

Step 2: Write the Test Bench Code

 • Open the newly created test bench file in the editor.

• Instantiate the DUT (Design Under Test) in the test bench.

• Declare the necessary signals and variables.

• Write the stimulus to drive the inputs and monitor the outputs.

Step 3: Simulate the Design

• Go to the Processes pane.

• Under Simulation, double-click Simulate Behavioral Model to start the simulation.

Step 4: View Simulation Results

• ModelSim will launch and display the waveform window.

• Analyze the waveforms to verify the design behavior.

10.5 Verilog Code for Half Adder

10.5.1 Data Flow Modeling

module halfadder_d (Sum, Carry, A, B);

input A, B;
output Sum, Carry;
assign Sum = A^B; // XOR operation
assign Carry = A&B; // AND operation
endmodule

10.5.2 Structural Modeling

module halfadder_s (Sum, Carry, A, B);

input A, B;
output Sum, Carry;
xor G1(Sum, A, B);
and G2(Carry, A, B);
endmodule

10.5.3. Behavioral Modeling

module halfadder_b (Sum, Carry, A, B);

 input A, B;
output Sum, Carry;
reg Sum, Carry;
always@(A,B)
begin
if (A == B)
begin
Sum = 0; Carry = B;
end
else
begin
Sum = 1; Carry = 0;
end
end
endmodule

10.5.4. Test Bench

module halfadder_tb;
reg A, B;
wire Sum, Carry;
halfadder_s uut (.Sum(Sum), .Carry(Carry), .A(A), .B(B)); // Instantiate the Unit
Under Test (UUT)
initial
begin
#000 A=0; B=0;
#100 A=0; B=1;
#100 A=1; B=0;
#100 A=1; B=1;
end
endmodule

10.6 Output Waveform

10.7 Result

The Half Adder was successfully designed and implemented using Data Flow,
Structural, and Behavioral modeling techniques in Verilog, with functionality verified through
a test bench.

Prelab Questions

1. List the various types of EDA tools currently utilized in the VLSI design industry.
2. Why has Verilog HDL emerged as a prominent Hardware Description Language in digital
circuit design?
3. What is the importance of simulating a Verilog design before implementing it on hardware?
4. What are the primary components of a half adder circuit, and what is the function of each
component?
5. How does a half-adder differ from a full-adder?
6. Where are half-adders typically used in digital circuits?

Post lab Questions

1. Describe the purpose of ‘module’ and ‘endmodule’ in Verilog.

2. What is the use of ‘input’, ‘output’, and ‘reg’ keywords in Verilog?
3. Explain the significance of ‘always’ blocks in behavioral modeling. How does the
sensitivity list affect the behavior of the block?
4. What is the significance of the ‘assign’ statement in data flow modeling?
5. Design and implement a full adder using Data Flow, Structural, and Behavioral modeling.
Verify the functionality using a test bench.