Combinational Circuits

What is Combinational Circuits?

• A Combinational Circuit is a combination of

Logic gates, the output depends upon the
current value of the inputs.
Examples of Combinational Circuits
 Addition:
 Half Adder (HA).
 Full Adder (FA).
 BCD(Decimal) Adder.
 Subtraction:
 Half Subtractor.
 Full Subtractor.
 Multiplication:
 Binary Multipliers.
 Comparator:
 Magnitude Comparator.
Examples of Combinational Circuits
 Multiplexers
 Demultiplexers
 Encoders
 Decoders
 Converters
• Binary to Gray Code
• Gray to Binary Code
• Binary to BCD Code
Two types of questions come in the exam
based on Combinational Circuit:
1.Designing of a combinational Circuit
2.Analysis of Combinational Circuit
 Designing Combinational Circuits
In general we have to do following steps:
1. Problem description
2. Input/output of the circuit
3. Define truth table
4. Simplification for each output
5. Draw the circuit
 Half Adder
 Adding two single-bit binary values, X, Y produces a sum S
bit and a carry out C-out bit.
 This operation is called half addition and the circuit to
realize it is called a half adder.

X Half S
Y Adder C-OUT
Half Adder Truth Table
Inputs Outputs

X Y S C-out S(X,Y) = S (1,2)

0 0 0 0 S = X’Y + XY’
0 1 1 0 S = XY
1 0 1 0
1 1 0 1 C-out(x, y) = S (3)
C-out = XY
 Full Adder
 Adding two single-bit binary values, X, Y with a carry input bit
C-in produces a sum bit S and a carry out C-out bit.

Full Adder Truth Table

Inputs Outputs
X Y

X Y C-in S C-out
Full
0 0 0 0 0 C-out
Adder
C-in
0 0 1 1 0
0 1 0 1 0
S
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 Full Adder
Sum S X
XY
C-in 00 01 11 10
X Y C-in S C-out 0 2 6 4
0 0 0 0 0 0 1 1
0 0 1 1 0 1
1
3 7
1
5
C-in
1
0 1 0 1 0
0 1 1 0 1 Y
Inputs Outputs
1 0 0 1 0
S = X’Y’(C-in) + XY’(C-in)’ + XY’(C-in)’ + XY(C-in)
1 0 1 0 1 S = X  Y  (C-in)
1 1 0 0 1
1 1 1 1 1 Carry C-out X
XY
C-in 00 01 11 10
Full Adder Truth Table 0 2 6 4
0 1
1 3 7 5
S(X,Y, C-in) = S (1,2,4,7) 1 1 1 1 C-in

C-out(x, y, C-in) = S (3,5,6,7)

Y

C-out = XY + X(C-in) + Y(C-in)

 Full Adder Circuit Using AND-OR

X’ X’Y’C-in
X Y’
X X’ C-in

X’
X’YC-in’ Sum S
Y
Y C-in’
Y Y’ X
Y

C-in C-in’ XY’C-in’

C-in C-in’ X
Y
C-in’ XYC-in

X XY
Y

X
XC-in C-out
C-in
Y

C-in YC-in
 Full Adder Circuit Using Ex-OR
X

Y Sum S
C-in

X
XY

X
XC-in C-out
C-in

C-in YC-in
Full Adder Circuit Using two half - Adders

Half Adder -1
Half Adder -2
 Binary adder
• Binary adder that produces the arithmetic
sum of binary numbers can be constructed
with full adders connected in cascade, with
the output carry from each full adder is
connected to the input carry of the next full
adder in the chain
• Note that the input carry C0 in the least
significant position must be 0.
Binary Adder

C0 = 0
 Binary Adder
• For example to add A= 1011 and B= 0011
subscript i: 3 2 1 0
Input carry: 0 1 1 0 Ci
Augend: 1 0 1 1 Ai
Addend: 0 0 1 1 Bi
--------------------------------
Sum: 1 1 1 0 Si
Output carry: 0 0 1 1 Ci+1
DECIMAL/BCD ADDER
Subtractors
Combinational Arithmetic
Circuits
 Addition:
 Half Adder (HA).
 Full Adder (FA).
 Binary Adder
 BCD(Decimal) Adder.
 Subtraction:
 Half Subtractor.
 Full Subtractor.
 Multiplication:
 Binary Multipliers.
 Comparator:
 Magnitude Comparator.
Combinational Arithmetic
Circuits
 Multiplexers
 Demultiplexers
 Encoders
 Decoders
 Half Subtractor
 Subtracting a single-bit binary value Y from anther X (I.e. X
-Y ) produces a difference bit D and a borrow out bit B-out.
 This operation is called half subtraction and the circuit to
realize it is called a half subtractor.
D(X,Y) = S (1,2)
D = X’Y + XY’
D = XY
Half Subtractor Truth Table
Inputs Outputs B-out(x, y, C-in) = S (1)
X Y D B-out B-out = X’Y
0 0 0 0 Difference
X
0 1 1 1 D
Y
1 0 1 0
1 1 0 0 B-out
X Half D
Y Subtractor B-OUT
 Binary Arithmetic Operations
Subtraction
 Two binary numbers are subtracted by subtracting each pair of
bits together with borrowing, where needed.
 Subtraction Example:

0 0 1 1 1 1 1 0 0 Borrow
X 229 1 1 1 0 0 1 0 1
Y - 46 - 0 0 1 0 1 1 1 0
183 1 0 1 1 0 1 1 1
 Full Subtractor
 Subtracting two single-bit binary Difference D X
values, Y, B-in from a single-bit value XY

X produces a difference bit D and a B-in 00 01 11 10

0 2 6 4
borrow out B-out bit. This is called full 0 1 1
subtraction. 1
1
3 7
1
5
B-in
1
Full Subtractor Truth Table
Inputs Outputs Y
S = X’Y’(B-in) + XY’(B-in)’ + XY’(B-in)’ + XY(B-in)
X Y B-in D B-out S = X  Y  (C-in)
0 0 0 0 0
0 0 1 1 1 Borrow B-out
0 1 0 1 1 X
0 1 1 0 1 XY
1 0 0 1 0 B-in 00 1
01 11 10
0 2 6 4
1 0 1 0 0 0 1 1 1
1 1 0 0 0 1 3 7 5
B-in
1 1 1 1 1 1

S(X,Y, C-in) = S (1,2,4,7)

Y

C-out(x, y, C-in) = S (1,2,3,7) B-out = X’Y + X’(B-in) + Y(B-in)

 Full Subtractor Circuit Using
AND-OR X’ X’Y’B-in
X Y’
X X’ B-in

X’
X’YB-in’ Difference D
Y
Y B-in’
Y Y’ X
Y

B-in B-in’ XY’B-in’

B-in B-in’ X
Y
B-in’ XYB-in

X Y X’ X’Y
Y
Full X’
B-out B-in X’B-in
Subtractor B-out
B-in
Y
D
B-in YB-in
 Full Subtractor Circuit Using XOR
X

Y Difference D
X Y B-in

Full X’ X’Y
B-out B-in
Subtractor Y

X’
X’B-in
B-out
D B-in
Y

B-in YB-in
 n-bit Subtractors
An n-bit subtracor used to subtract an n-bit number Y from another
n-bit number X (i.e X-Y) can be built in one of two ways:

 By using n full subtractors and connecting them in series, creating a borrow

ripple subtractor:
 Each borrow out B-out from a full subtractor at position j is connected
to the borrow in B-in of the full subtracor at the higher position j+1.

 By using an n-bit adder and n inverters:

 Find two’s complement of Y by:
 Inverting all the bits of Y using the n inverters.
 Adding 1 by setting the carry in of the least significant position to 1
 The original subtraction (X - Y) now becomes an addition of X to
two’s complement of Y using the n-bit adder.
 Binary Subtractor
• The subtrcation A – B can be done by taking
the 2’s complement of B and adding it to A
because A- B = A + (-B)
• It means if we use the inveters to make 1’s
complement of B (connecting each Bi to an
inverter) and then add 1 to the least
significant bit (by setting carry C0 to 1) of
binary adder, then we can make a binary
subtractor.
4 bit 2’s complement Subtractor

=1
 Adder Subtractor
• The addition and subtraction can be combined
into one circuit with one common binary
adder (see next slide).
• The mode M controls the operation. When
M=0 the circuit is an adder when M=1 the
circuit is subtractor. It can be don by using
exclusive-OR for each Bi and M. Note that 1 ⊕
x = x’ and 0 ⊕ x = x
 Checking Overflow
• Note that in the previous slide if the numbers
considered to be signed V detects overflow. V=0
means no overflow and V=1 means the result is
wrong because of overflow
• Overflow can be happened when adding two
numbers of the same sign (both negative or positive)
and result can not be shown with the available bits.
It can be detected by observing the carry into sign bit
and carry out of sign bit position. If these two carries
are not equal an overflow occurred. That is why
these two carries are applied to exclusive-OR gate to
generate V.
 Design example: 2x2-bit
multiplier
A2 A1 B2 B1 P8 P4 P2 P1
0 0 0 0 0 0 0 0
0 1 0 0 0 0
1 0 0 0 0 0
1 1 0 0 0 0
A1 P1 0 1 0 0 0 0 0 0
A2 P2 0 1 0 0 0 1
1 0 0 0 1 0
B1 P4 1 1 0 0 1 1
B2 P8 1 0 0 0 0 0 0 0
0 1 0 0 1 0
1 0 0 1 0 0
1 1 0 1 1 0
1 1 0 0 0 0 0 0
block diagram 0 1 0 0 1 1
and 1 0 0 1 1 0
truth table 1 1 1 0 0 1

4-variable K-map
for each of the 4
output functions
 Design example: 2x2-bit
multiplier (cont’d)
A2 A2
K-map for P8 K-map for P4
0 0 0 0 0 0 0 0
P4 = A2B2B1'
0 0 0 0 0 0 0 0
B1 + A2A1'B2 B1
0 0 1 0 0 0 0 1
B2 P8 = A2A1B2B1 B2
0 0 0 0 0 0 1 1
A1 A1

A2 A2
0 0 0 0
K-map for P2 K-map for P1 0 0 0 0
P1 = A1B1
0 0 1 1 0 1 1 0
B1 B1
0 1 0 1 0 1 1 0
B2 P2 = A2'A1B2 B2
0 1 1 0 + A1B2B1' 0 0 0 0
A1 + A2B2'B1 A1
+ A2A1'B1
Magnitude Comparator
 Magnitude Comparator
• It is a combinational circuit that compares two
numbers and determines their relative magnitude
• The output of comparator is usually 3 binary
variables indicating: A>B
A=B
A<B
• For example to design a comparator for 2 bit binary
numbers A (A1A0) and B (B1B0) we do the following
steps:
 Comparators
• For a 2-bit comparator we have four inputs A1A0 and B1B0 and three
output E ( is 1 if two numbers are equal), G (is 1 when A > B) and L (is 1
when A < B) If we use truth table and KMAP the result is
• E= A’1A’0B’1B’0 + A’1A0B’1B0 + A1A0B1B0 + A1A’0B1B’0
or E=(( A0 ⊕ B0) + ( A1 ⊕ B1))’ (see next slide)
• G = A1B’1 + A0B’1B’0 + A1A0B’0
• L= A’1B1 + A’1A’0B0 + A’0B1B0

A0
E
A1
Comparator G
B0
L
B1
 Truth Table
A0 A1 B0 B1 E L G
0 0 0 0 1 0 0
0 0 0 1 0 1 0
0 0 1 0 0 1 0
0 0 1 1 0 1 0
0 1 0 0 0 0 1
0 1 0 1 1 0 0
0 1 1 0 0 1 0
0 1 1 1 0 1 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 1 0 0
1 0 1 1 0 1 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
 Magnitude Comparator

• From the truth table:

E = (0,5,10,15)
= A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0’B1B0’ +A1A0B1B0
 Magnitude Comparator
• A>B means A1 B1 Y1
------------
0 0 0
0 1 0
1 0 1
1 1 0
if A1=B1 (X1=1) then A0 should be 1 and B0 should be 0
A0 B0 Y0
------------
0 0 1
0 1 0
1 0 0
1 1 0
For A> B: A1 > B1 or A1 =B1 and A0 > B0
It means Y= A1B’1 + X1A0B’0 should be 1 for A>B
 Magnitude Comparator
• For B>A B1 > A1
or
A1=B1 and B0> A0
z= A’1B1 + X1A’0B0
• The procedure for binary numbers with more than 2 bits can
also be found in the similar way. For example next slide shows
the 4-bit magnitude comparator, in which
(A= B) = x3x2x1x0
(A> B) = A3B’3 + x3A2B’2 + x3x2A1B’1+ x3x2x1A0B’0
(A< B) = A’3B3 + x3A’2B2 + x3x2A’1B1+ x3x2x1A’0B0
 Design example: two-bit
comparator
A B C D LT EQ GT
0 0 0 0 0 1 0
0 1 1 0 0
1 0 1 0 0
N1 A LT AB<CD 1 1 1 0 0
B 0 1 0 0 0 0 1
EQ AB=CD
C 0 1 0 1 0
N2 GT AB>CD 1 0 1 0 0
D
1 1 1 0 0
1 0 0 0 0 0 1
0 1 0 0 1
1 0 0 1 0
1 1 1 0 0
block diagram 1 1 0 0 0 0 1
and 0 1 0 0 1
1 0 0 0 1
truth table 1 1 0 1 0

we'll need a 4-variable Karnaugh map

for each of the 3 output functions
 Design example: two-bit
comparator (cont’d)
A A A
0 0 0 0 1 0 0 0 0 1 1 1

1 0 0 0 0 1 0 0 0 0 1 1
D D D
1 1 0 1 0 0 1 0 0 0 0 0
C C C
1 1 0 0 0 0 0 1 0 0 1 0
B B B

K-map for LT K-map for EQ K-map for GT

LT = A' B' D + A' C + B' C D

EQ = A'B'C'D' + A'BC'D + ABCD + AB'CD’ = (A xnor C) • (B xnor D)
GT = B C' D' + A C' + A B D'

Canonical PofS vs minimal?

LT and GT are similar (flip A/C and B/D)

 Design example: two-bit
comparator (cont’d)
A B C D

two alternative
implementations of EQ
with and without XOR

EQ

XNOR is implemented with

at least 3 simple gates
EQ
Code Converter
Binary to Gray Code Converter
 Steps to design the converter
1. Design a converter by the following procedures:
a. Write down the truth table of both input and output bits of the
converter.
b. Apply Karnaugh Map to look for the minimized logic expression for the
output bits.
c. Implement the logic gates by using Circuit Maker.
Example:
For Binary to Gray Code Converter, binary bits are input and gray code
bits are output. So first write the truth table for binary bits and gray code.
Then k-map for the all bits of gray code, find the simplified expression for
each bit of gray code. Then design the logical circuit.
Truth Table
K-Map for each bit of Gray code
Gray to Binary Converter
 Truth Table
Dec G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
3 0 0 1 1 0 0 1 0
2 0 0 1 0 0 0 1 1
6 0 1 1 0 0 1 0 0
7 0 1 1 1 0 1 0 1
5 0 1 0 1 0 1 1 0
4 0 1 0 0 0 1 1 1
12 1 1 0 0 1 0 0 0
13 1 1 0 1 1 0 0 1
15 1 1 1 1 1 0 1 0
14 1 1 1 0 1 0 1 1
10 1 0 1 0 1 1 0 0
11 1 0 1 1 1 1 0 1
9 1 0 0 1 1 1 1 0
 K MAP For B3
G1’G0’ G1’G0 G1G0 G1G0’
0 0 0 0
G3’G2’

0 0 0 0
G3’G2

1 1 1 1
G3G2

1 1 1 1
G3G2’

B3 = G3
 K MAP For B2
G1’G0’ G1’G0 G1G0 G1G0’
0 0 0 0
G3’G2’

1 1 1 1
G3’G2

0 0 0 0
G3G2

1 1 1 1
G3G2’

B1  G3  G 2  G1
 K MAP For B1
G1’G0’ G1’G0 G1G0 G1G0’
0 0 1 1
G3’G2’

1 1 0 0
G3’G2

0 0 1 1
G3G2

1 1 0 0
G3G2’

B1  G3  G 2  G1
 K MAP For B0
G1’G0’ G1’G0 G1G0 G1G0’
0 1 0 1
G3’G2’

1 0 1 0
G3’G2

0 1 0 1
G3G2

1 0 1 0
G3G2’

B0  G3  G 2  G1  G0
 B3 G3

B2 G2

B1 G1

G0
B0
 Assignment
Design the Converter for
1. Binary to BCD
2. BCD to Gray
3. BCD to Binary
4. BCD to Excess
Analysis of Combinational Circuits
 Designing Combinational Logic Circuits
•A logic circuit having 3 inputs, A, B,
C will have its output HIGH only
when a majority of the inputs are
HIGH.
Step 1 Set up the truth table

Step 2
Write the AND term for each case
where the output is a 1.
 Sum-Of-Products Form
• SOP is useful in simplification and design
• Two or more AND terms OR together
–Ex: ABC+ABC
–the inversion sign cannot cover more than
one variable (ABC)
• Another general form for logic expressions is
sometimes used in logic-circuit design. It called
product-of-sum (POS)
• Consist 2 or more OR terms that are AND together.
- Ex: (A+B+C)(A+C)
 Analysis of Logic Circuits
• First obtain one expression for the circuit, then try to simplify.
• Example:

• Two methods for simplifying:

- Algebraic method (use Boolean algebra theorems)
- Karnaugh mapping method (systematic, step-by-step approach)
 Algebraic Simplification
1. Put the original expression into SOP form by repeated
application of DeMorgan’s theorems
2. Once in SOP form, check for common factors and factor
whenever possible.
Example:
Step 3 Write the SOP form the output
Step 4 Simplify the output expression
Step 5 Implement the circuit
 Karnaugh Map (K-Map) Method

• K Map shows the relationship between inputs & outputs

• Horizontally & vertically adjacent squares differ only in one
variable.
Looping is a process combining the squares which contain 1s.
The output expression can be simplified by looping.
 Rule for loops of any size
When a variable appears in both
complemented & uncomplemented form
within a loop, that variable is eliminated from
the expression. Variables that are the same for
all squares of the loop must appear in the final
expression.
 Complete Simplification Process
1.Construct the K map and place 1s and 0s in the squares according to the
truth table.
2.Loop the isolated 1s which are not adjacent to any other 1s. (single loops)
3.Loop any pair which contains a 1 adjacent to only one other 1. (double
loops)
4.Loop any octet even if it contains one or more 1s that have already been
looped.
5.Loop any quad that contains one or more 1s that have not already been
looped, making sure to use the minimum number of loops.
6.Loop any pairs necessary to include any 1s that have not yet been looped,
making sure to use the minimum number of loops.
7.Form the OR sum of all the terms generated by each loop.
“Don’t-Care” Conditions are certain input conditions for which
there are no specified output levels. “Don’t-care” conditions
should be changed to either 0 or 1 to produce K-map looping
that yields the simplest expression.
 Filling K-Map from Output Expression

When the desired output is presented as a

Boolean expression instead of a truth table,
the K map can be filled by using the following
steps:
1. Get the expression into SOP form if it is not already so.
2. For each product term in the SOP expression, place a 1 in
each K-map square whose label contains the same
combination of input variables. Place a 0 in all other
squares.
• Don’t care condition can come about for several reasons:
– In some situations certain input combination can
never occur and so there is no specified output for
these condition.
• Whenever don’t care conditions occur, we must decide which
x to change to 0 and which to 1 to produce the best K-map
looping (i.e the simplest expression)
Example
 Example
A BCD counter produces a four bit output
representing the BCD code for the number of pulses
hat have been applied to the counter input. For
example, after 4 pulses have occurred, the counter
outputs are DCBA= 01002 = 410. The counter resets to
0000 on the tenth pulse and starts counting over
again. In other words, the DCBA output will never
represent a number greater than 10012=910. Design
the logic circuit that produces a HIGH output
whenever the count is 2,3, or 9. Use K mapping and
take advantage of the don’t care conditions.
 Summary
• Compared to the algebraic method, the K-map
process is a more orderly process requiring
fewer steps and always producing a minimum
expression.
• For the circuits with large numbers of inputs
(larger than four), other more complex
techniques are used.
 Exclusive-OR and Exclusive-NOR Circuits
Exclusive-OR (XOR) produces a HIGH output whenever
the two inputs are at opposite levels.
Exclusive-NOR (XNOR) produces a HIGH output
whenever the two inputs are at the same level.
XNOR gate may be used to simplify circuit
implementation.
Parity Generator and Checker
• A transmitter can attach a parity bit to a set of data bits
before transmitting the data bits to a receiver. The receiver
will detect any single bit errors that may have occurred during
the transmission.
• In figure (a) the set of data to be transmitted is applied to the
parity-generator circuit, which produces the even-parity bit, P,
at its output. This parity bit is transmitted to the receiver
along with the original data bits, making a total of five bits.
• In figure (b) these five bits (data+parity) enter the receiver’s
parity-checker circuit, which produces an error output, E that
indicates whether or not a single-bit error has occurred.
Enable/Disable Circuits
 Enable/Disable Circuits cont.
Ex. 1(Fig.a): Design a logic circuit that will allow a
signal to pass to the output only when control inputs B
and C are both HIGH; otherwise, the output will stay
LOW.
Ex. 2(Fig.b): Design a logic circuit that will allow a
signal to pass to the output only when one, but not
both, of the control inputs are HIGH; otherwise, the
output will stay LOW.
Multiplexer/De-multiplexer
 Mux/Demux Vocabulary
MULTIPLEXER (aka DATA SELECTOR)- circuit that can select one of a number
of inputs and pass the logic level of that input to the output.

DEMULTIPLEXER (aka DATA DISTRIBUTOR)- circuit that depending on the status

of its select inputs will channel its data input to one of several outputs.

SELECT INPUTS (aka ADDRESS LINES)- used by the mux to determine which data
inputs will be switched to the output.
if 2 N input lines  N select lines
 Example of a Combinatorial Circuit:
A Multiplexer (MUX)

Consider an integer ‘m’, which is

constrained by the following relation:
m = 2n, where m and n are both integers.
• A m-to-1 Multiplexer has
• m Inputs: I0, I1, I2, ................ I(m-1)
• one Output: Y
• n Control inputs: S0, S1, S2, ...... S(n-1)
• One (or more) Enable input(s)
such that Y may be equal to one of the inputs, depending upon
the control inputs.
BASIC TWO-INPUT MULTIPLEXER

I1
DATA
INPUTS Z  I 0  S  I1  S
I0

S S OUTPUT
SELECT INPUT
0 Z=I0
1 Z=I1
 Example: A 4-to-1 Multiplexer

A 4-to-1 Multiplexer:

I0

2n inputs I1 Y
I2 4:1 MUX
1 output
I3

Enable (G) S0 S1
n control inputs
 FOUR-INPUT MULTIPLEXER
I0

I1

I2

I3 S1 S0 OUTPUT
0 0 Z=I0
0 1 Z=I1
1 0 Z=I2
S1 S0 1 1 Z=I3
 MULTIPLEXER LOGIC DIAGRAM
•Takes one of many inputs and funnels it to an output Z.

•Take the selector lines convert to a decimal number and this is the
input funneled to the output.

•Strobe is active low enable

S2 S1 S0 E Z
0 0 0 0 I0
D
A
I0 0 0 1 0 I1
T I1
A I2 74151
0 1 0 0 I2
I
I3
I4 MUX
Z
_
0 1 1 0 I3
N
P I5 Z 1 0 0 0 I4
U I6
T I7 1 0 1 0 I5
S
E
S2 S1 S0 1 1 0 0 I6
1 1 1 0 I7
SELECT LINES
MULTIPLEXER APPLICATIONS

•DATA ROUTING
•PARALLEL-TO-SERIAL CONVERSION
•OPERATION SEQUENCING
•IMPLEMENT LOGIC FUNCTION OF A TRUTH
TABLE
LOGIC FUNCTION GENERATION
+5

I0
C B A Z
I1
0 0 0 0
I2 74151
Z  ABC  ABC  ABC 0 0 1 1
I3
I4 MUX 0 1 0 1
I5
0 1 1 0
I6 1 0 0 0
I7 1 0 1 0
E 1 1 0 0
S2 S1 S0 1 1 1 1
DEMULTIPLEXER
DEMULTIPLEXER LOGIC DIAGRAM
•Logic circuit that depending on the status of its select inputs will funnel
its data input to one of several data outputs.

•Separate enable inputs (useful for cascading decoders) into AND gate
which must be high to enable the decoder outputs.

O0
E3 O1
E2 74138 O2
E
DEMUX O3
E1 1-OF-8 DECODER E1 E 2 E3 OUTPUTS
O4
0 0 1 RESPOND TO INPUT CODE A2A1A0
O5 1 X X DISABLED –ALL HIGH
X 1 X DISABLED –ALL HIGH
O6 X X 0 DISABLED –ALL HIGH
O7

A2 A1 A0

SELECT LINES
 LOGIC FUNCTION GENERATION
74138
O0
O1
O2
+5
O3 f(ABC)
E3 O4
O5
E2
O6
C B A f
E1 O7
0 0 0
A2 A1 A0 0 0 1
0 1 0
C B A 0 1 1
1 0 0
A B X
1 0 1
0 0 1 1 1 0
0 1 1 1 1 1
1 0 1
1 1 0

NAND- any low in gives a high out

DEMULTIPLEXER
DEMULTIPLEXER
 115

OTHER COMBINATIONAL LOGIC

CIRCUITS

DECODERS
 116

DECODER
•A decoder is a logic circuit that accepts a set of inputs that
represents a binary number and activates only the output
that corresponds to the input number.
•In other words, a decoder circuit looks at its inputs,
determines which binary number is present there, and
activates the one output that corresponds to that number ;
all other outputs remain inactive
 117

In its general form, a decoder has N input lines to handle N

bits and form one to 2 N output lines to indicate the presence
of one or more N-bit combinations.
The basic binary function
•An AND gate can be used as the basic decoding element
because it produces a HIGH output only when all inputs are
HIGH

Refer next slide for example

 118

Decoding logic for the binary code 1001 with an active-HIGH output.
 119
General decoder diagram

# There are 2N possible input combinations, from A0 to AN1.

For each of these input combinations only one of the M outputs will be active HIGH (1),
all the other outputs are LOW (0).
 120

• If an active-LOW output (74138, one of the output will

low and the rest will be high) is required for each decoded
number, the entire decoder can be implemented with
1. NAND gates
2. Inverters

• If an active-HIGH output (74139, one of the output will

high and the rest will be low) is required for each decoded
number, the entire decoder can be implemented with
• AND gates
• Inverters
 121

2-to-4-Line Decoder
(with Enable input)-Active LOW output (1)...
 122

2-to-4-Line Decoder
(with Enable input)-Active LOW output (2)

• The circuit operates with complemented outputs

and a complement enable input. The decoder is
enabled when E is equal to 0.
• Only one output can be equal to 0 at any given
time, all other outputs are equal to 1.
• The output whose value is equal to 0 represents
the minterm selected by inputs A and B
• The circuit is disabled when E is equal to 1.
 123

3-8 line decoder (active-HIGH)

 124

•This decoder can be referred to in several ways. It can be

called a 3-line-to- 8-line decoder, because it has three input
lines and eight output lines.
•It could also be called a binary-octal decoder or converters
because it takes a three bit binary input code and activates
the one of the eight outputs corresponding to that code. It is
also referred to as a 1-of-8 decoder, because only 1 of the 8
outputs is activated at one time.
 125

Logic diagram of 74138 (Example of a 3Bit Decoder)

 126

Truth table of 74138 (Example of a 3 8 Bit Decoder)

active-LOW
 127

74138 (Example of a 3 8 Bit Decoder)

• There is an enable function on this device, a LOW level on

each input E’1, and E’2, and a HIGH level on input E3, is
required in order to make the enable gate output HIGH.

• The enable is connected to an input of each NAND gate in the

decoder, so it must be HIGH for the NAND gate to be enabled.

• If the enable gate is not activated then all eight decoder

outputs will be HIGH regardless of the states of the three
input variables A0, A1, and A2 .
 128

Example of a 5 to 32 Bit Decoder

 129

Logic symbol for a 4-line-to-16-line (1-of-16) decoder .

74HC154
 130

4-line-to-16 line Decoder constructed with two 3-line-to-8 line

decoders (1)...
 131

4-line-to-16 line Decoder constructed with two 3-line-to-8 line

decoders (2)

• When w=0, the top decoder is enabled and the

other is disabled. The bottom decoder outputs
are all 0’s , and the top eight outputs generate
min-terms 0000 to 0111.
• When w=1, the enable conditions are reversed.
The bottom decoder outputs generate min-
terms 1000 to 1111, while the outputs of the top
decoder are all 0’s.
 132
Application example
A simplified computer I/O port system with a port address decoder with only four address
lines shown.
 133

•Decoders are used in many types of applications. One example is in computers for I/O
selection as in previous slide

•Computer must communicate with a variety of external devices called peripherals by sending
and/or receiving data through what is known as input/output (I/O) ports

•Each I/O port has a number, called an address, which uniquely identifies it. When the
computer wants to communicate with a particular device, it issues the appropriate address
code for the I/O port to which that particular device is connected . The binary port address is
decoded and appropriate decoder output is activated to enable the I/O port

•Binary data are transferred within the computer on a data bus, which is a set of parallel lines
 134
BCD -to- Decimal decoders

•The BCD- to-decimal decoder converts each BCD code into

one of Ten Positionable decimal digit indications. It is
frequently referred as a 4-line -to- 10 line decoder
•The method of implementation is that only ten decoding
gates are required because the BCD code represents only the
ten decimal digits 0 through 9.
•Each of these decoding functions is implemented with NAND
gates to provide active -LOW outputs. If an active HIGH
output is required, AND gates are used for decoding
Logic diagram of BCD - decimal
135decoder

(Active LOW output)

 136

Output Waveform for BCD Decoder

 137
A Decoder Application - Counter -decoder combination used to provide timing and sequential
operations (1)...
 138

A Decoder Application - Counter -decoder combination used to provide

timing and sequential operations (1)...

•Decoders are used whenever an output or a group of

outputs is to be activated only on the occurrence of
specific combination of input levels. These input levels are
often provided by the outputs of a counter or register.
•When the decoder inputs come from a counter that is
being continually pulsed, the decoder outputs will be
activated sequentially, and there can be used as timing or
sequencing signals to turn device on or off at specific
times
 139

BCD-7segment decoders/drivers

Most digital equipment has some means

for displaying information in a form that
can be understood by the user. This
information is often numerical data but
also be alphanumeric.
One of the simplest and most popular
methods for displaying numerical digits
uses a 7-segment configuration to form
digital characters 0 to 9 and some times
the hex characters A to F
 140

One common arrangements uses light-emitting diodes (LED's)

for each segment. By controlling the current thru each LED,
some segments will be light and others will be dark so that
desired character pattern will be generated
Figure shows the segment
pattern that are used to
display the various digits. For
example, to display a “6” the
segments a,c,d,e,f and g are
made bright while segment
b is dark
 141

7-segment decoder

•A BCD-7 segment decoder/driver is used to take four-bit BCD

input and provide the outputs that will pass current through
the appropriate segments to display the decimal digit.
•The logic for this decoder is more complicated than the logic
of decoders of earlier case, because each output is activated
for more than one combination of inputs.
 142

74LS47 ( BCDtoSevenSegment Decoder)

143
 144

Lamp Test (LT)

•When LT = Low, BI/RBO = HIGH then all of the 7 segments in

display are turned zero, LT is used to verify that no segments
are burned out

Zero Suppression (BI, RBI, RBO)

•Zero suppression is a feature used for multi digit displays to

blank out unnecessary zeros.

Example:
In a 6-digit display the number 6.4 may be displayed as
006.400 if the zeros are not blanked out
 145

•Leading Zero Suppression

Blanking the zeros at the front of a numbers

•Trailing Zero Suppression

Blanking the zeros at the back of the number

Only nonessential zeros are blanked, the number 030.080

will be displayed as 30.08 (the essential zeros remain)
 146

7-segment display

• There are two types of 7segment LED

displays;
• A) common - anode
• B) common  cathode
 147

Common Anode
In commonanode, the anode of all of the LEDs are tied together to positive of
the power supply (Vcc) as shown
 148

Common Cathode

• In commoncathode, the cathode of all of the LEDs are tied

together to ground as shown.

GND
 149

Combinational Logic Circuit Implementation using a Decoder

• Any combinational logic circuit with n inputs

and m outputs can be implemented with an n-
to-2n-line decoder and m OR gates.
• Procedure:
– Express the given Boolean function in sum of min-terms
– Choose a decoder to generate all the min-terms of the
input variables.
– Select the inputs to each OR gate from the decoder
outputs according to the list of min-term for each function.
 150
Combinational Logic Circuit Implementation using
a Decoder - An example (1)
• From the truth table of the full adder,
x y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

• the functions can be expressed in sum of min-terms.

S(x,y,z) = Sm(1,2,4,7)
C(x,y,z) = Sm(3,5,6,7)
where S indicates sum, m indicates min-term and the number in brackets
indicate the decimal equivalent
 151

Combinational Logic Circuit Implementation using a

Decoder - An example (2)

Since there are three inputs and a total of eight

min-terms, we need a 3-to-8 line decoder.
• The decoder generates the eight min-terms
for x,y,z
• The OR gate for output S forms the logical sum
of min-terms 1,2,4, and 7.
• The OR gates for output C forms the logical
sum of min-terms 3,5,6, and 7
 152
Combinational Logic Circuit Implementation using a Decoder -
example (3)

Implementation of a Full Adder with a Decoder

Encoders
 Encoder

•An encoder is a combinational logic circuit that essentially

performs a “reverse” of decoder functions.
•An encoder accepts an active level on one of its inputs,
representing digit, such as a decimal or octal digits, and
converts it to a coded output such as BCD or binary.
•Encoders can also be devised to encode various symbols and
alphabetic characters.
•The process of converting from familiar symbols or numbers
to a coded format is called encoding.
•Most decoders accept an input code and produce a HIGH
•( or a LOW) at one and only one output line. In otherworlds ,
a decoder identifies, recognizes, or detects a particular code.
The opposite of this decoding process is called encoding and is
performed by a logic circuit called an encoder.
•An encoder has a number of input lines, only one of which
input is activated at a given time and produces an N-bit output
code,depending on which input is activated.
General encoder diagram
Logic circuit for octal-to binary encoder [8-line-
3-line ]
 Truth table for octal-to binary encoder [8-line- 3-line ]

A low at any single input will produce the output binary code corresponding to that
input. For instance , a low at A3’ will produce O2 =0, O1=1 and O0 =1, which is
binary code for 3. Ao’ is not connected to the logic gates because the encoder
outputs always be normally at 0000 when none of the inputs is LOW
 Design of 4-input Priority Encoder
( 4-line-to 2 line priority encoder) (1)...
• A priority encoder is an encoder that includes the priority
function
• If two or more inputs are equal to 1 at the same time, the
input having the highest priority will take precedence.
• Truth Table of a 4-input Priority Encoder:
Inputs Outputs
D0 D1 D2 D3 x y V
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1
 Design of 4-input Priority Encoder
( 4-line-to 2 line priority encoder) (2)...

• In addition to two outputs x, and y, the truth table has a

third output designated by V, which is a valid bit indicator
that is set 1 when one or more inputs are equal to 1. If all
inputs are 0, there is no valid input and V is equal to 0.
• X’s in the output column indicate don’t care conditions,
the X’s in the input columns are useful for representing a
truth table in condensed form.
• The higher the subscript number, the higher the priority
of the input. Input D3 has the highest priority, so
regardless of the values of the other inputs, when this
input is 1, the output for xy is 11 (binary 3)
 Design of 4-input Priority Encoder
( 4-line-to 2 line priority encoder) (3)...

V=D0+D1+D2+D3
K-Maps for 4-input Priority Encoder
 Design of 4-input Priority Encoder
( 4-line-to 2 line priority encoder) (4)

Logic Diagram for 4-input priority encoder

 Decimal-BCD priority encoder

•Encoder will produce a BCD output corresponding to the

highest-order decimal digit input that is active and will ignore
any other lower order active inputs.

•For instance if the input 6 and the 3 are active, the output
will be 1001, which is the inverse value of BCD output 0110
(which represents decimal 6)
74147 decimal-BCD priority encoder

When A9’ is low, the output is 0110, which is

inverse of 1001 ( eq to 9 in BCD)
 Decimal- BCD switch decoder

The output of the decoder are inversed to produce the normal

BCD value
 The OctaltoBinary Priority Encoder-
Example

• The 74LS148 is a priority encoder that has eight

active LOW inputs and three activeLOW binary
outputs

• To enable the device, the EI (enable input) must

be LOW. It also has the EO (enable output) and
GS (group signal output) for expansion purposes.
The OctaltoBinary Encoder
 The OctaltoBinary Encoder

• ActiveLOW enable input, a HIGH on the input forces all outputs

to their inactive state (HIGH).

• ActiveLOW enable output, the output pin goes LOW when all
inputs are inactive (HIGH) and is LOW.

• ActiveLOW group signal output, this output pin goes LOW

whenever any of the inputs are active (LOW) and is LOW.
 The 16 to4 Encoder

The 74LS148 can be expanded to a 16lineto4line encoder by

connecting the EO of the higherorder encoder to the EI of the
lowerorder encoder and negativeORing the corresponding
binary outputs as shown
The 16 to4 Encoder
 Application example

A simplified keyboard encoder.

•When one of the keys is pressed, the decimal digit is encoded to the
corresponding BCD code

•The keys are represented by 10 push-button switches, each with a pull-up

resistor to V+. The pull-up resistor ensures that the line is HIGH when a key is
not depressed.

•When a key is depressed, the line is connected to ground, and a LOW is applied
to the corresponding encoder input.

•The zero key is not connected because the BCD output represents zero when
none of the other keys is depressed

•The BCD complement output of the encoder goes into a storage device, and
each successive BCD code is stored until the entire number has been entered
 Assignment

Design a single encoder for following functions.

F1 = Σm(1, 3, 7, 15)
f2 = Σm(4,6,8,10)