Frequency Synthesis 2023
Frequency Synthesis 2023
Patricia Desgreys
ICS905 - FARE
M2 « Integration Circuits & Systems »
RF oscillators
PLLs
LPF ADC I
Band selection
BPF LNA
Digital Processing
LPF ADC Q
Frequency
90°
Synthesis
DAC Q
æ pö
VBB cos ç w BB t + ÷
è 2ø
PA BPF VLO cos (w LO t )
VLO æ æ pö æ p öö
w LO - w BB w LO + w BB ç VA cos ç w BB t + ÷ + VB cos ç w BB t - ÷ ÷
2 è è 2ø è 2 øø
LPF -90°
Frequency VLO
Synthesis
+90°
2
(VA cos (w BB t ) - VB cos (w BB t ) )
• RF oscillators
• PLLs
• Frequency synthesizers
Fcw
n
Fmax
Fref Frequency
Fo=Fcw . Fref
Synthesizer Df
Fmin
The frequency range [Fmin, Fmax] and the resolution Df are synthesizer fundamental
specifications which depend on the application.
Frequency range
Resolution
Accuracy
Settling time
Reference frequency
Spurs
Power consumption
Temperature stability
Phase noise
RF oscillators
PLLs
ve vs
S H
H ( jw )
Vs = Ve
1 - G ( jw ) H ( jw )
G
ì G ( jw0 ) H ( jw0 ) = 1
ï
Positive feedback system Barkhausen criterion í
ïîarg {G ( jw0 ) H ( jw0 )} = 0
ve vs
S
The system oscillations frequency is
determined by the characteristics of the
selective circuit.
1 C1 C1 + C2
C L w= L w0 =
LC LC1C2
X C2
T1 T1
2
1 æ C1 ö
gm ç1 + ÷
è C2 ø
gm
C1
L
X C2
T1
Colpitts oscillator
CMOS differential architecture
Cvar C0
C L L Cvar (Vcom ) = 1
Vcom
æ Vcom ö2
C2 ç1 - ÷
ç Vdiff ÷
è ø
Cvar
æ P ö
Dw L ( Dw ) = 10 log ç n ÷ [ dBc / Hz ]
è PLO ø
wLO wLO
1Hz frequency band
Thus, because of the different noise sources (thermal, 1/f…) the Power Spectral
Density (PSD) spreads around f0
Phase noise and jitter are two manifestations of an unique phenomena : random
fluctuations of the oscillator period.
frequency
wLO
frequency
wLO
PB
Sn(f)
Spurious signal
HF channel
of interest
60 dB
PS
?
fL fH f
Df = 60 kHz
ICS, UE AMS&RF Functions . October 10, 2023 . Page 19
Summary
RF oscillators
PLLs
DF = F x - F y
(
y ( t ) = VLO cos w FR t + F y )
Vcom = K DP DF ò
F y = KVCO Vcom dt
Basic Phase Locked Loop
F y ( p) K GLPF ( p )
Closed loop transfer function: H ( p) = = avec K = K DP KVCO
Fx ( p) p + K GLPF ( p )
1
with first order low-pass filter: GLPF ( p ) = , we obtain a classical second order system:
p
1+
w LPF
w n2
wx Dw H ( p) = 2
p + 2zw n p + w n2
avec w n = w LPF K
wy Dw
1 w LPF
et z =
2 K
Dw
K
DF
x(t)
Waveforms in CPPLL
with wx> wy in closed loop :
y(t)
Vout cons tan t
Df
QX w y = w FR + KVCOVout = w x
DF = F x - F y = 0
QX = QY = 0
Vout
ICS, UE AMS&RF Functions . October 10, 2023 . Page 23
Charge Pump PLL
Assuming that the bandwidth of the loop is much lower than the input frequency:
CP CP CP
C
R ‘ripple’ ± 2RI R
RC p 3rd order !
z =0 z = K
2
ICS, UE AMS&RF Functions . October 10, 2023 . Page 24
CPPLL – Input phase noise filtering
Transfer function of a second-order CPPLL with a stabilization zero :
Vout F y ( p) w n2 æç1 + p w ö÷
æ 1ö KVCO
= 2 è
zø
fx K PFD ç RC p + ÷ fy H ( p) =
è pø p F x ( p ) p + 2zw n p + w n2
ìw n2 = K = K PFD KVCO
ï
avec í 1
ïîw z = RC p
Fy
log
Fx
w
HF noise is eliminated at the
w p1 wz w p2
output.
æ 1ö Vout KVCO
fx = 0 K PFD ç RC p + ÷ fy
è pø p F y ( p) p2
=
FVCO ( p ) p 2 + 2zw n p + w n2
Fy
log
FVCO
Manchester
code (biphase)
1 0 1 1 0 0 1 0
Unipolar RZ
code
1 0 1 1 0 0 1 0
Differential Important : Phase noise small enough !
Biphase code
(DBP) 1 0 1 1 0 0 1 0
Phase locked loops are key elements in digital communications systems. Their
design and optimization are complex ( trade-off between speed, precision, stability).
RF oscillators
PLLs
x(t) H y(t)
y H 1
= =
x 1+ b H b
b
÷M
fF
f out
=M
fin
÷M Frequency divider
prescaler Band counter (P>S) by pulse counting
One output cycle occurs at the end of
f1 ÷(N+1)/N ÷P f2 (N + 1) * S + N * (P-S) input cycles.
Modulus reset f1
control ÷S Channel f2 =
NP + S
counter
Channel selection
ICS, UE AMS&RF Functions . October 10, 2023 . Page 33
Integer Modulus Synthesizer
fréf Charge fout ÷M
PFD VCO
pump prescaler Band counter
f1 ÷(N+1)/N ÷P f2
÷M
Modulus reset
÷S
control Channel
counter
Modulus selection Channel selection
Main drawback:
The reference frequency has a small value.
The bandwidth of PLLs is limited to 1/10 of The bandwidth of the loop is limited!
the input frequency to ensure stability
ex : GSM inter-channel spacing : 200kHz
Settling time 100 µs or more
ICS, UE AMS&RF Functions . October 10, 2023 . Page 34
Fractional Modulus Synthesizer
fref Phase Low-pass fout
VCO
detector Filter
prescaler
÷(N+1)/N
y(t) x(t)
Modulus
A*Tout B*Tout control A*Tout B*Tout
÷(N+1)/N
Modulus
control
EXAMPLE :
Let's Consider a synthesizer for which the reference frequency is provided by a
?
1MHz oscillator. The expected output frequency is:
f out = f 0 + kf ch