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FOV-Unit1 Complete-13

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12 views5 pages

FOV-Unit1 Complete-13

Uploaded by

Harsh Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Simple MOS Capacitance Models

• 3 types of diffusion regions frequently seen - illustrated by two series transistors


• Fig (a)- each source & drain has its own isolated region of contacted diffusion
• Fig(b)- drain of the bottom transistor & source of the top transistor form a shared
contacted diffusion region
• Fig(c)- source & drain are merged into an uncontacted region
• Average capacitance of each of these types of regions can be calculated or
measured from simulation as a transistor switches between VDD and GND

K.SUJATHA , Associate Professor, BMSCE


Simple MOS Capacitance Models
• For the purposes of hand estimation- observe- diffusion
capacitance Csb & Cdb of contacted source & drain regions
is comparable to the gate capacitance (e.g., 1–2 fF/µm of
gate width)

• Diffusion capacitance of the uncontacted source or drain


is somewhat less because the area is smaller but the
difference is usually unimportant for hand calculations

• These values of Cg = Csb = Cdb ≈ 1fF/µm will be used in


examples, but should obtain the appropriate data for our
process, using methods to be discussed later

K.SUJATHA , Associate Professor, BMSCE


Detailed MOS Gate Capacitance Model
• MOS gate sits above the channel & may partially overlap
the source & drain diffusion areas

• Gate capacitance has 2 components: intrinsic


capacitance Cgc (over the channel) & overlap
capacitances Cgol (to the source & drain)

• intrinsic capacitance was approximated as a simple


parallel plate in EQ (2.12) with capacitance C0 = WLCox

• bottom plate of the capacitor depends on the mode of


operation of the transistor

K.SUJATHA , Associate Professor, BMSCE


Detailed MOS Gate Capacitance Model
• Intrinsic capacitance
has 3 components
representing different
terminals connected
to the bottom plate:
Cgb (gate-to-body),
Cgs (gate-to-source),
Cgd(gate-to-drain)
• Fig(a) plots
capacitance vs. Vgs in
the cutoff region &
for small Vds
• (b) plots capacitance
vs. Vds in the linear &
saturation regions K.SUJATHA , Associate Professor, BMSCE
Detailed MOS Gate Capacitance Model
1. Cutoff: When transistor is OFF (Vgs < Vt), channel is not inverted
& charge on the gate is matched with opposite charge from the body
- called Cgb
As Vgs increases but remains below a threshold, a depletion region
forms at the surface - effectively moves the bottom plate downward
from the oxide, reducing the capacitance
2. Linear: When Vgs > Vt , channel inverts & again serves as a good
conductive bottom plate. channel is connected to the source & drain,
rather than the body, so Cgb drops to 0.
At low values of Vds, channel charge is roughly shared between
source & drain, so Cgs = Cgd = C0/2. As Vds increases, the region near
the drain becomes less inverted, so a greater fraction of the
capacitance is attributed to the source & a smaller fraction to the
drain
3.Saturation: At Vds > Vgs – Vt , the transistor saturates & the
channel pinches off. At this point, all the intrinsic
capacitance is to the source.
Because of pinchoff, the capacitance in saturation reduces to
Cgs = 2/3 C0 for an ideal transistor
K.SUJATHA , Associate Professor, BMSCE

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