FUNDAMENTALS OF VLSI

Course Code 23EC5PCFOV

Credits 3 L-T-P 3:0:0

Faculty in charge : K.Sujatha

Associate Professor
BMSCE
K.SUJATHA , Associate Professor, BMSCE
Course Outcomes:

K.SUJATHA , Associate Professor, BMSCE

 FOV Syllabus
MODULE – I
• MOS Transistor: Long Channel I-V characteristics, C-V Characteristics, Simple MOS Capacitance Models,
Detailed MOS Gate Capacitance Model, Non-ideal I-V Effects.
• CMOS Logic: Inverter, NAND Gate, NOR Gate, CMOS Compound Gates. VLSI design flows.
MODULE – II
• CMOS Processing Technology: CMOS Technologies, CMOS Inverter Fabrication and Layout, Lay out Design
Rules, Gate Layouts and Stick Diagrams. CMOS Process enhancements. Manufacturing Issues.
MODULE – III
• Static CMOS Inverter: DC Characteristics, Beta Ratio Effect, Noise Margin, Pass Transistor DC Characteristics,
Circuit design using Pass Transistors and Transmission Gates, Tristate buffer, Multiplexers.
• Sequential MOS logic circuitry: SR Latch Circuitry, Clocked latch and Flip Flop Circuitry (SR and JK), CMOS D-
Latch and Edge Triggered Flip-Flop.
MODULE – IV
• Sequencing Static Circuits: Sequencing Methods, Max-Delay Constraints, Min-Delay Constraints, Time
Borrowing, Clock Skew.
• Array Sub system: SRAM: SRAM Cells, Row Circuitry, Column Circuitry.
• DRAM: Subarray Architectures, Column Circuitry, Embedded DRAM.
MODULE – V
• Silicon Debug Principles, Manufacturing Test Principles: Fault Models, Observability, Controllability,
Repeatability, Fault Coverage, ATPG, Delay Fault Testing, Design for Testability: Ad Hoc Testing, Scan Design,
BIST, IDDQ Testing, Design for Manufacturability, Boundary Scan

Choice: Unit-III and Unit-IV.

K.SUJATHA , Associate Professor, BMSCE

 FOV Syllabus
Text Books:
1. “CMOS VLSI Design: A Circuits and Systems Perspective”, Neil H. E. Weste
and David Harris, Pearson Education, 4th Edition, 2011, ISBN: 0-321-54774-8.
2. “CMOS Digital Integrated Circuits”, Sung-Mo Kang and Yusuf Leblebici, Tata
Mc-GrawHill, 3rd Edition, ISBN: 0-7923-7246-8.

Reference Books:
1. “Basic VLSI Design”, Douglas. A. Pucknell and Kamaran Eshraghian, PHI, 3rd
Edition, 2010, ISBN: 0-321-26977-2.
2. “Introduction to VLSI Circuits & Systems”, John P. Uyemura, Wiley India
Edition.

E books and online course materials:

1. http://swarm.cs.pub.ro/˜mbarbulescu/SMPA/CMOS-VLSI-design.pdf
MOOCs:
1. https://nptel.ac.in/courses/117101058/
K.SUJATHA , Associate Professor, BMSCE
 Introduction to VLSI
VLSI- Very Large Scale Integration
Analysis and Design of very dense electronic Integrated circuits
VLSI contains more than 1 million switching devices or logic gates

Basics of digital VLSI chip design

Emphasis on translating a system specification to a small piece of silicon
Engineering a VLSI chip is an extremely complex task

Non technical group- Idea, sand , CAD, Engineers, Marketing, $

Super chip

Design Team- Engineers, Scientists, Technicians

Design Hierarchy – chip is viewed at many different “levels” from the

abstract to the physical implementation

VLSI Field- Inherently multidisciplinary in nature, Specialist in an

unaccountable number of areas are needed to produce a working
functional design. K.SUJATHA , Associate Professor, BMSCE
 Transistors
• Transistors can be viewed as electrically controlled switches with a
control terminal and two other terminals that are connected or
disconnected depending on the voltage or current applied to the
control.
• Soon after inventing the point contact transistor, Bell Labs
developed the bipolar junction transistor
• Bipolar transistors were more reliable, less noisy, and more power-
efficient. Early integrated circuits primarily used bipolar transistors.
• Bipolar transistors require a small current into the control (base)
terminal to switch much larger currents between the other two
(emitter and collector) terminal
• The quiescent power dissipated by these base currents, drawn even
when the circuit is not switching, limits the maximum number of
transistors that can be integrated onto a single die
• By the 1960s, Metal Oxide Semiconductor Field Effect Transistors
(MOSFETs) began to enter production.
K.SUJATHA , Associate Professor, BMSCE
 MOSFET
• In 1963, Frank Wanlass at Fairchild described the first logic gates using
MOSFETs
• Fairchild’s gates used both nMOS and pMOS transistors, earning the
name Complementary Metal Oxide Semiconductor, or CMOS
• Circuits used discrete transistors but consumed only nanowatts of
power, six orders of magnitude less than their bipolar counterparts
• MOS integrated circuits became attractive for their low cost because
each transistor occupied less area & fabrication process was simpler
• Early commercial processes used only pMOS transistors and suffered
from poor performance, yield, & reliability.
• Processes using nMOS transistors became common in the 1970s
• While the nMOS process was less expensive than CMOS, nMOS logic
gates still consumed power while idle
• CMOS processes were widely adopted & have essentially replaced
nMOS & bipolar processes for nearly all digital logic applications.
K.SUJATHA , Associate Professor, BMSCE
 Moore’s Law
• Gordon Moore observed that the Transistor count doubling every
18 months

K.SUJATHA , Associate Professor, BMSCE

 MOS Transistor
Metal-Oxide-Semiconductor structure is created by superimposing several
layers of conducting & insulating materials to form a sandwich-like
structure.
These structures are manufactured using a series of chemical processing
steps involving oxidation of the silicon, selective introduction of dopants,
and deposition and etching of metal wires and contacts.
Transistors are built on nearly flawless single crystals of silicon, which
are available as thin flat circular wafers of 15–30 cm in diameter.
 CMOS technology provides two types of transistors: an n-type transistor
(nMOS) and a p-type transistor (pMOS). Transistor operation is controlled
by electric fields so the devices are also called Metal Oxide Semiconductor
Field Effect Transistors (MOSFETs) or simply FETs.

K.SUJATHA , Associate Professor, BMSCE

 MOSFET as Switches
 MOSFET: Metal-Oxide-Semiconductor
Field-Effect Transistor

 nFET: an n-channel MOSFET that uses

negatively charged electrons for electrical
current flow

(a) nFET symbol

 pFET: a p-channel MOSFET that uses
positive charges for current flow

 In many ways, MOSFETs behave like the

idealized switches
(b) pFET symbol
 The voltage applied to the gate determines
the current flow between the source and Figure 2.9 Symbols used
for nFETs and pFETs
drain terminals BMS College of Engineering-KS
 MOSFET as Switches

• Early generations of silicon MOS logic circuits used both positive

and negative supply voltages
• In modern designs require only a single positive voltage VDD and
the ground connection, e.g. VDD = 5 V and 3.3 V or lower

• The relationship between logic variables x and it’s voltages Vx

0  Vx  VDD
x  0 means that Vx  0V

x  1 means that Vx  VDD

BMS College of Engineering-KS

 Switching Characteristics of MOSFET

• In general,
 Low voltages correspond to logic 0 values
 High voltages correspond to logic 1 values
• The transition region between the
highest logic 0 voltage and the lowest
logic 1 voltage is undefined (a) Open (b) Closed

• nFET Figure 2.12 nFET switching characteristics

y  x  A which is valid iff A  1

• pFET

y  x  A which is valid iff A  0 (a) Open (b) Closed

Figure 2.13 pFET switching characteristics

BMS College of Engineering-KS

 MOS Transistors as switches
 We can model MOS transistors as controlled switches
 Voltage at gate controls path from source to drain

BMS College of Engineering-KS

 CMOS Technology

• CMOS technology uses both nMOS and pMOS

transistors.

• The transistors are arranged in a structure formed by

two complementary networks

BMS College of Engineering-KS

CMOS Logic - Inverter

BMS College of Engineering-KS

 The NOT Gate

(a) x = 0 input

Figure 2.23 CMOS not gate (b) x = 1 input

Figure 2.24 Operation of

the CMOS NOT gate
BMS College of Engineering-KS
The NAND Gate

BMS College of Engineering-KS

The NAND Gate- 3-input NAND

BMS College of Engineering-KS

 CMOS Logic Gates
• Inverter & NAND gates are eg of static CMOS logic gates, also called
complementary CMOS gates
• In general, a static CMOS gate has an nMOS pull-down network to connect
the output to 0 (GND) and pMOS pull-up network to connect the output to
1 (VDD), as shown in Fig 1.14
• Networks are arranged such that one is ON and the other OFF for any input
pattern

BMS College of Engineering-KS

 CMOS Logic Gates
In general, when we join a pull-
up network to a pull-down
network to form a logic gate as
shown in Fig, they both will
attempt to exert a logic level at
the output.

The possible levels at the output

are shown in Table 1.3.

pull-up & pull-down networks in the

inverter each consist of a single
transistor

NAND gate uses a series pull-down

network and a parallel pullup network

BMS College of Engineering-KS

 CMOS Logic Gates
This is illustrated in Fig1.15 for nMOS and pMOS transistor pairs.

By using combinations of these constructions, CMOS combinational gates can be constructed

BMS College of Engineering-KS
 The NOR Gate – 2 input
• nMOS transistors are in parallel to pull the output low when either input is
high. pMOS transistors are in series to pull the output high when both inputs
are low, as indicated in Table 1.4. Output is never crowbarred or left
floating.

BMS College of Engineering-KS

 The NOR Gate- 3 input NOR gate

If any input is high, the output is pulled low through the parallel
nMOS transistors.
If all inputs are low, the output is pulled high through the series
pMOS transistors.

BMS College of Engineering-KS

 Compound Gates
• A compound gate performing a more complex logic function in a single
stage of logic is formed by using a combination of series and parallel
switch structures

• Eg, the derivation of the circuit for the function

Y = (A · B) + (C · D) is shown in fig

• This function is sometimes called AND-OR-INVERT-22, or AOI22

because it performs the NOR of a pair of 2-input ANDs

• For the nMOS pull-down network, take the uninverted expression

((A · B) + (C · D)) indicating when the output should be pulled to ‘0.’ The
AND expressions (A · B) and (C · D) may be implemented by series
connections of switches, as shown in Figure 1.18(a)

• Now ORing the result requires the parallel connection of these two
structures, which is shown in Figure 1.18(b)
BMS College of Engineering-KS
 Compound Gates
• For the pMOS pull-up network, we must compute the complementary
expression using switches that turn on with inverted polarity.
• By DeMorgan’s Law, this is equivalent to interchanging AND and OR
operations.
• Hence, transistors that appear in series in the pull-down network
must appear in parallel in the pull-up network.
• Transistors that appear in parallel in the pulldown network must
appear in series in the pull-up network.
• This principle is called conduction complements and has already been
used in the design of the NAND and NOR gates.
• In the pull-up network, the parallel combination of A and B is placed
in series with the parallel combination of C and D. This progression is
evident in Figure 1.18(c) and Figure 1.18(d).
• Putting the networks together yields the full schematic (Figure
1.18(e)).
• The symbol is shown in Figure 1.18(f ).
BMS College of Engineering-KS
Compound Gates

BMS College of Engineering-KS

 Structured Logic Design

(a) Series-connected nFETs Figure 2.44 nFET AOI circuit

(b) Parallel-connected nFETs

Figure 2.45 nFET OAI circuit
Figure 2.43 nFET logic formation BMS College of Engineering-KS
 Structured Logic Design

(a) Parallel-connected pFETs (a) pFET AOI circuit

(b) pFET OAI circuit

(b) Series-connected pFETs
Figure 2.47 pFET arrays for AOI and OAI gates
Figure 2.46 pFET logic formation BMS College of Engineering-KS
 Compound Gates
SOLUTION: Figure 1.19 shows
such an OR-AND-INVERT-3-1
(OAI31) gate

The nMOS pull-down network

pulls the output low if D is 1 and
either A or B or C are 1, so D is
in series with the parallel
combination of A, B, and C

 The pMOS pull-up network is

the conduction complement, so D
must be in parallel with the series
combination of A, B, and C.
BMS College of Engineering-KS
 Compound Gates

• X = (a.b) + (c.d)

• Y = (a+e) . (b+f)

BMS College of Engineering-KS

 Structured Logic Design

(a) AOI circuit (b) OAI circuit

Figure 2.48 Complete CMOS AOI and OAI circuits

BMS College of Engineering-KS

 Bubble Pushing

(a) NAND - OR
(a) Parallel-connected pFETs

(b) NOR - AND

Figure 2.52 Bubble pushing using DeMorgan rules

(b) Series-connected pFETs

Figure 2.51 Assert-low models for pFETs BMS College of Engineering-KS

 XOR and XNOR Gates
An important example of using an
AOI circuit is constructing
Exclusive-OR (XOR) and
Exclusive-NOR circuits

a b  a b  a b (2.71)

a b  a b  a b (2.72)

 a  b  (a  b)  a  b  a  b (2.73)
(a) Exclusive-OR (b) Exclusive-NOR

 a b  a b  a b (2.74) Figure 2.57 AOI XOR and XNOR gates

(a) AOI22 (b) AOI321 (c) AOI221

Figure 2.58 General naming convention

BMS College of Engineering-KS
Figure 2.56 XOR
 MOS Transistor Theory

• MOS transistor is a majority-carrier device in which the

current in a conducting channel between the source &
drain is controlled by a voltage applied to the gate

• nMOS transistor: majority carriers are electrons

pMOS transistor: majority carriers are holes

• Behavior of MOS transistors can be understood by first

examining an isolated MOS structure with a gate & body
but no source or drain

K.SUJATHA , Associate Professor, BMSCE

 MOS Transistor Theory
• (a): a negative voltage is
applied to the gate, so there
is negative charge on the
gate. Mobile positively
charged holes are attracted to
the region beneath the gate-
accumulation mode
• (b): a small positive voltage
is applied to the gate,
resulting in some positive
charge on the gate. Holes in
the body are repelled from
the region directly beneath
the gate, resulting in a
depletion region forming
below the gate
• (c): a higher positive
potential exceeding a critical
threshold voltage Vt is
applied, attracting more
positive charge to the gate.
Holes are repelled further &
some free electrons in the
body are attracted to the
region beneath the gate.
Conductive layer of
electrons= inversion layer
• Threshold voltage depends
on the number of dopants
in the body &thickness tox
of the oxide
K.SUJATHA , Associate Professor, BMSCE
 MOS Transistor Theory- nMOS
• Transistor consists of the
MOS stack between two n-
type regions called source &
drain
• (a): gate-to-source voltage
Vgs is less than threshold
voltage
• source & drain have free
electrons. Body has free
holes but no free electrons
• If source is grounded,
junctions between body &
source or drain are zero-
biased or reverse-biased, so
little or no current flows
• Transistor is OFF =>mode
of operation is called cutoff
• It is often convenient to
approximate the current
through an OFF transistor
as zero, especially in
comparison to the current
through an ON transistor
• small amounts of current
leaking through OFF
transistors can become
significant, especially when
multiplied by millions or
billions of transistors on a
chip K.SUJATHA , Associate Professor, BMSCE
 MOS Transistor Theory
• (b): gate voltage is
greater than the
threshold voltage-
inversion region of
electrons (majority
carriers) called
channel connects
source & drain,
creating a conductive
path & turning the
transistor ON. Number
of carriers &
conductivity increases
with gate voltage
• Potential difference
between drain &
source is Vds=Vgs-Vgd
• If Vds = 0 (i.e., Vgs =
Vgd), there is no
electric field tending to
push current from
K.SUJATHA , Associate Professor, BMSCE
drain to source
 MOS Transistor Theory
• (c): When a small positive
potential Vds is applied to the
drain , current Ids flows
through the channel from
drain to source - mode of
operation is termed linear,
resistive, triode,
nonsaturated, or
unsaturated;current
increases with both drain
voltage & gate voltage.
• (d): If Vds becomes
sufficiently large that Vgd <
Vt , channel is no longer
inverted near the drain &
becomes pinched off
• Conduction is still brought
about by the drift of
electrons under the influence
of the positive drain voltage
As electrons reach the end of
the channel, they are injected
into the depletion region near
the drain & accelerated
toward the drain. Above this
drain voltage, current Ids is
controlled only by the gate
voltage & ceases to be
influenced by drain-mode is K.SUJATHA , Associate Professor, BMSCE
called saturation.
 MOS Transistor Theory
• In summary, the nMOS transistor has three modes of operation

• If Vgs < Vt , the transistor is cutoff (OFF)

• If Vgs > Vt , the transistor turns ON

• If Vds is small, the transistor acts as a linear resistor in which the

current flow is proportional to Vds

• If Vgs > Vt and Vds is large, the transistor acts as a current source
in which the current flow becomes independent of Vds

K.SUJATHA , Associate Professor, BMSCE

 MOS Transistor Theory
• pMOS transistor in Fig
operates in just the opposite
fashion
• n-type body is tied to a high
potential so the junctions
with the p-type source &
drain are normally reverse-
biased. When the gate is
also at a high potential, no
current flows between drain
& source
• When the gate voltage is
lowered by a threshold Vt ,
holes are attracted to form a
p-type channel immediately
beneath the gate, allowing
current to flow between
drain & source
• Threshold voltages of the
two types of transistors are
not necessarily equal, so we
use the terms Vtn & Vtp to
distinguish the nMOS &
pMOS thresholds
K.SUJATHA , Associate Professor, BMSCE
 MOS Transistor Theory
• Although MOS transistors are symmetrical, by convention
we say that majority carriers flow from their source to their
drain

• Because electrons are negatively charged, the source of an

nMOS transistor is the more negative of the two terminals

• Holes are positively charged so the source of a pMOS

transistor is the more positive of the two terminals

• In static CMOS gates, source is the terminal closer to the

supply rail & drain is the terminal closer to the output

K.SUJATHA , Associate Professor, BMSCE

 MOS Transistor Theory
• Derive an ideal model relating current & voltage (I-V) for a
transistor
• Delay of MOS circuits is determined by time required for this
current to charge or discharge the capacitance of the circuits
• Investigate transistor capacitances
• Gate of an MOS transistor is inherently a good capacitor
with a thin dielectric; its capacitance is responsible for
attracting carriers to the channel & thus for the operation
of the device
• p–n junctions from source or drain to the body contribute
additional parasitic capacitance
• Capacitance of wires interconnecting the transistors is also
important
K.SUJATHA , Associate Professor, BMSCE
 MOS Transistor Theory
• Idealized I-V model provides a general qualitative
understanding of transistor behaviour but is of limited
quantitative value
• Neglects too many effects that are important in transistors
with short channel lengths L
• Model is not sufficient to calculate current accurately
• Idealized I-V model is too complicated to use in back-of-
the-envelope calculations tuning the performance of large
circuits
• Develop even simpler models for performance estimation

• Applying the I-V models to understand the DC transfer

characteristics of CMOS gates & pass transistors
K.SUJATHA , Associate Professor, BMSCE
 Long -Channel I-V Characteristics
• As stated previously, MOS transistors have three regions of operation:
• Cutoff or subthreshold region
• Linear region
• Saturation region
• Derive a model relating current & voltage (I-V) for an nMOS transistor
in each of these regions
• Model assumes-channel length is long enough that the lateral electric
field is relatively low (which is no longer the case in nanometer devices)
• This model = long-channel, ideal, first-order, or Shockley model
• Long-channel model assumes- current through an OFF transistor is 0
• When transistor turns ON (Vgs > Vt), gate attracts carriers (electrons)
to form a channel
• Electrons drift from source to drain at a rate proportional to the electric
field between these regions
• Can compute currents if we know amount of charge in channel & rate
at which it moves
K.SUJATHA , Associate Professor, BMSCE
 Long -Channel I-V Characteristics
• Charge on each plate of a capacitor
Q = CV charge in channel Qchannel
Qchannel =Cg (Vgc -Vt ) ----(2.1)
• Cg =>capacitance of gate to channel
Vgc- Vt => voltage attracting charge
to the channel (beyond the minimum
required to invert from p to n)
• Gate voltage is referenced to the
channel, which is not grounded

• If source is at Vs & drain is at Vd ,

average Vc= (Vs + Vd)/2 = Vs + Vds /2

• Therefore,mean difference between

gate & channel potentials Vgc is
Vg – Vc = Vgs – Vds /2 K.SUJATHA , Associate Professor, BMSCE
 Long -Channel I-V Characteristics
We can model gate as a parallel plate capacitor with capacitance
proportional to area over thickness
If gate has length L & width W & oxide thickness is tox

ℇo - permittivity of free space, 8.85 × 10–14 F/cm

permittivity of SiO2 is kox = 3.9 times as great
ℇox /tox is called Cox, capacitance per unit area of gate oxide

K.SUJATHA , Associate Professor, BMSCE

 Long -Channel I-V Characteristics
• Some nanometer processes use a different gate dielectric with a
higher dielectric constant
• In these processes, we call tox the equivalent oxide thickness (EOT),
the thickness of a layer of SiO2 that has the same Cox.
• In this case, tox is thinner than the actual dielectric
• Each carrier in channel is accelerated to an average velocity, v,
proportional to the lateral electric field, i.e., field between source &
drain
• Constant of proportionality µ is called the mobility
v = µ E -----(2.3)
• A typical value of µ for electrons in an nMOS transistor with low
electric fields is 500–700 cm2/V· s
• most transistors today operate at far higher fields where the mobility is
severely curtailed
• Electric field E = Vds/L ----(2.4)
K.SUJATHA , Associate Professor, BMSCE
 Long -Channel I-V Characteristics
• Time required for carriers to cross channel is the channel length
divided by the carrier velocity: L/v
• Therefore, current between source & drain is the total amount of
charge in the channel divided by the time required to cross

K.SUJATHA , Associate Professor, BMSCE

 Long -Channel I-V Characteristics
(Vgs – Vt ) arises often - convenient to abbreviate it as VGT
EQ (2.5) describes the linear region of operation, for Vgs > Vt , but Vds
relatively small. It is called linear or resistive because when Vds << VGT
, Ids increases almost linearly with Vds, just like an ideal resistor
Geometry & technology-dependent parameters are sometimes merged
into a single factor β
Some texts lump the technology-dependent parameters alone into a
constant called “k prime” k' = µCox ------(2.7)
If Vds > Vdsat ≡ VGT , the channel is no longer inverted in the vicinity
of the drain- pinched off
Beyond drain saturation voltage, increasing the drain voltage has no
further effect on current
Substituting Vds = Vdsat at this point of maximum current into EQ (2.5),
we find an expression for saturation current that is independent of Vds

K.SUJATHA , Associate Professor, BMSCE

 Long -Channel I-V Characteristics
This expression is valid for Vgs > Vt & Vds > Vdsat
Thus, long-channel MOS transistors are said to exhibit square-law
behavior in saturation
Two key figures of merit for a transistor are Ion and Ioff. Ion (also called
Idsat) is the ON current, Ids, when Vgs = Vds = VDD
 Ioff is the OFF current when Vgs = 0 and Vds = VDD
According to the long-channel model, Ioff = 0 and

K.SUJATHA , Associate Professor, BMSCE

Cox = ℇox / tox = Kox ℇo /tox

ℇo (permittivity of free space)= 8.85 × 10–14 F/cm

permittivity of SiO2 is kox = 3.9 times as great
ℇox = Kox ℇo

K.SUJATHA , Associate Professor, BMSCE

 Example
• According to first-order model, current is zero for gate voltages < Vt higher gate
voltages, current increases linearly with Vds for small Vds As Vds reaches the
saturation point Vdsat = VGT, current rolls off and eventually becomes independent of
Vds when the transistor is saturated.
• Shockley model overestimates current at high voltage because it does not account
for mobility degradation & velocity saturation caused by high electric fields

K.SUJATHA , Associate Professor, BMSCE

 Example
• pMOS transistors behave same
way, but with the signs of all
voltages & currents reversed
• I-V characteristics in third
quadrant
• Disregard the signs - remember
that current flows from source to
drain in a pMOS transistor
• Mobility of holes in silicon is
typically lower than that of
electrons( pMOS transistors provide
less current than nMOS transistors of
comparable size & hence are slower)
• Symbols µn and µp are used to
distinguish mobility of electrons
& of holes in nMOS & pMOS
transistors
• Mobility ratio µn / µp is typically
2–3
K.SUJATHA , Associate Professor, BMSCE
 Exercise 2.1
• Consider an nMOS transistor in a 0.6µm process with
W/L = 4/2λ (i.e., 1.2/0.6 µm). In this process, the gate
oxide thickness is 100 Å and the mobility of electrons
is 350 cm2/V· s. The threshold voltage is 0.7 V
• Plot Ids vs Vds for Vgs = 0, 1, 2, 3, 4, and 5 V

K.SUJATHA , Associate Professor, BMSCE

Exercise 2.1

K.SUJATHA , Associate Professor, BMSCE

 C-V Characteristics
• Each terminal of an MOS transistor has capacitance to
the other terminals

• These capacitances are nonlinear & voltage

dependent(C-V); can be approximated as simple
capacitors when their behaviour is averaged across the
switching voltages of a logic gate

• first present simple models of each capacitance suitable

for estimating delay & power consumption

• then explore more detailed models used for circuit

simulation
K.SUJATHA , Associate Professor, BMSCE
 Simple MOS Capacitance Models
• Gate of an MOS transistor is a good capacitor- capacitance is
necessary to attract charge to invert the channel, so high gate
capacitance is required to obtain high Ids

• gate capacitor can be viewed as a parallel plate capacitor with gate

on top & channel on bottom with thin oxide dielectric between

Cg =CoxWL (2.12)

• When transistor is on, channel extends from source (& reaches drain
if transistor is unsaturated, or stops short in saturation)
• often approximate the gate capacitance as terminating at the source
& call the capacitance Cgs
• Most transistors used in logic are of minimum manufacturable length
because this results in greatest speed & lowest dynamic power
consumption K.SUJATHA , Associate Professor, BMSCE
 Simple MOS Capacitance Models
Taking this minimum L as a constant for a particular
process, we can define
Cg = Cpermicron x W (2.13)
C permicron = Cox L = (ℇox x L) /tox (2.14)

if we develop a more advanced manufacturing process in

which both channel length & oxide thickness are reduced
by the same factor, Cpermicron remains unchanged

This relationship is handy for quick calculations but not

exact; Cpermicron has fallen from about 2 fF/µm in old
processes to about 1 fF/µm at the 90 & 65 nm nodes

K.SUJATHA , Associate Professor, BMSCE

 Exercise
• 2.4) A 90 nm long transistor has a gate oxide thickness
of 16 Å. What is its gate capacitance per micron of
width?

Cpermicron = ℇox L /tox

= 1.94 fF/μm

K.SUJATHA , Associate Professor, BMSCE

 Simple MOS Capacitance Models
• source & drain also have capacitances
• not fundamental to operation of the devices, but impact
circuit performance – parasitic capacitors
• source & drain capacitances arise from p–n junctions
between source or drain diffusion & body - diffusion
capacitance Csb & Cdb
• depletion region with no free carriers forms along the
junction - acts as an insulator between the conducting p-
& n-type regions, creating capacitance across the junction
• junctions capacitances depends on- area & perimeter of
source & drain diffusion, depth of diffusion, doping
levels, voltage
• As diffusion has both high capacitance & high
resistance, it is generally made as small as possible in the
layout
K.SUJATHA , Associate Professor, BMSCE
 Simple MOS Capacitance Models
• 3 types of diffusion regions frequently seen - illustrated by two series transistors
• Fig (a)- each source & drain has its own isolated region of contacted diffusion
• Fig(b)- drain of the bottom transistor & source of the top transistor form a shared
contacted diffusion region
• Fig(c)- source & drain are merged into an uncontacted region
• Average capacitance of each of these types of regions can be calculated or
measured from simulation as a transistor switches between VDD and GND

K.SUJATHA , Associate Professor, BMSCE

 Simple MOS Capacitance Models
• For the purposes of hand estimation- observe- diffusion
capacitance Csb & Cdb of contacted source & drain regions
is comparable to the gate capacitance (e.g., 1–2 fF/µm of
gate width)

• Diffusion capacitance of the uncontacted source or drain

is somewhat less because the area is smaller but the
difference is usually unimportant for hand calculations

• These values of Cg = Csb = Cdb ≈ 1fF/µm will be used in

examples, but should obtain the appropriate data for our
process, using methods to be discussed later

K.SUJATHA , Associate Professor, BMSCE

 Detailed MOS Gate Capacitance Model
• MOS gate sits above the channel & may partially overlap
the source & drain diffusion areas

• Gate capacitance has 2 components: intrinsic

capacitance Cgc (over the channel) & overlap
capacitances Cgol (to the source & drain)

• intrinsic capacitance was approximated as a simple

parallel plate in EQ (2.12) with capacitance C0 = WLCox

• bottom plate of the capacitor depends on the mode of

operation of the transistor

K.SUJATHA , Associate Professor, BMSCE

 Detailed MOS Gate Capacitance Model
• Intrinsic capacitance
has 3 components
representing different
terminals connected
to the bottom plate:
Cgb (gate-to-body),
Cgs (gate-to-source),
Cgd(gate-to-drain)
• Fig(a) plots
capacitance vs. Vgs in
the cutoff region &
for small Vds
• (b) plots capacitance
vs. Vds in the linear &
saturation regions K.SUJATHA , Associate Professor, BMSCE
 Detailed MOS Gate Capacitance Model
1. Cutoff: When transistor is OFF (Vgs < Vt), channel is not inverted
& charge on the gate is matched with opposite charge from the body
- called Cgb
As Vgs increases but remains below a threshold, a depletion region
forms at the surface - effectively moves the bottom plate downward
from the oxide, reducing the capacitance
2. Linear: When Vgs > Vt , channel inverts & again serves as a good
conductive bottom plate. channel is connected to the source & drain,
rather than the body, so Cgb drops to 0.
At low values of Vds, channel charge is roughly shared between
source & drain, so Cgs = Cgd = C0/2. As Vds increases, the region near
the drain becomes less inverted, so a greater fraction of the
capacitance is attributed to the source & a smaller fraction to the
drain
3.Saturation: At Vds > Vgs – Vt , the transistor saturates & the
channel pinches off. At this point, all the intrinsic
capacitance is to the source.
Because of pinchoff, the capacitance in saturation reduces to
Cgs = 2/3 C0 for an ideal transistor
K.SUJATHA , Associate Professor, BMSCE
 Detailed MOS Gate Capacitance Model
Behaviour in these 3 regions are approximated in Table

K.SUJATHA , Associate Professor, BMSCE

 Detailed MOS Gate Capacitance Model
• gate overlaps source & drain in a real device & also has fringing
fields terminating on the source & drain - leads to additional
overlap capacitances, as shown in Fig 2.10

• These capacitances are proportional to the width of the transistor

• Typical values are Cgsol = Cgdol = 0.2 – 0.4 fF/µm
• should be added to the intrinsic gate capacitance to find the total
Cgs(overlap) = CgsolW (2.15)
Cgd(overlap) = CgdolW
K.SUJATHA , Associate Professor, BMSCE
 Detailed MOS Gate Capacitance Model
view - gate capacitance as a single-terminal capacitor attached to the gate (with the other side
not switching)
Because source & drain actually form second terminals, the effective gate capacitance varies
with the switching activity of the source & drain
Fig shows effective gate capacitance in a 0.35 µm process for 7 different combinations of
source & drain behaviour
More accurate modeling of the gate capacitance may be achieved by using a charge based
model
For the purpose of delay calculation of digital circuits, we usually approximate
Cg = Cgs + Cgd + Cgb ≈ C0 + 2CgolW or use an effective capacitance extracted

K.SUJATHA , Associate Professor, BMSCE

 Nonideal I-V Effects
• Ideal (long-channel )I-V model of EQ (2.10) neglects
many effects that are important to devices with channel
lengths below 1 micron

• summarize the effects of greatest significance to

designers - then model each one in more depth

• compare simulated I-V characteristics of a 1-micron

wide nMOS transistor in a 65 nm process to the ideal
characteristics computed previously

K.SUJATHA , Associate Professor, BMSCE

Non ideal I-V Effects

K.SUJATHA , Associate Professor, BMSCE

 Nonideal I-V Effects
• saturation current increases less than quadratically with
increasing Vgs
• caused by two effects: velocity saturation & mobility degradation
• At high lateral field strengths (Vds /L), carrier velocity ceases to
increase linearly with field strength- called velocity saturation &
results in lower Ids than expected at high Vds

• At high vertical field strengths (Vgs / tox ), the carriers scatter off
the oxide interface , slowing their progess- mobility degradation
effect also leads to less current than expected at high Vgs

• saturation current of the nonideal transistor increases somewhat

with Vds - caused by channel length modulation, in which
higher Vds increases the size of the depletion region around the
drain & thus effectively shortens the channel
K.SUJATHA , Associate Professor, BMSCE
 Nonideal I-V Effects
• Threshold voltage indicates gate voltage necessary to invert
channel & is determined by oxide thickness & channel doping
levels
• other fields in the transistor have some effect on the channel,
effectively modifying threshold voltage
• Increasing the potential between source & body raises the
threshold through the body effect
• Increasing drain voltage lowers the threshold through drain-
induced barrier lowering
• Increasing the channel length raises threshold through the
short channel effect
• Several sources of leakage result in current flow in nominally
OFF transistors. When Vgs < Vt , the current drops off
exponentially rather than abruptly becoming zero- called
subthreshold conduction-current into the gate Ig is ideally 0
K.SUJATHA , Associate Professor, BMSCE
 Nonideal I-V Effects
• as thickness of gate oxides reduces to only a small number
of atomic layers, electrons tunnel through the gate,
causing some gate leakage current

• source & drain diffusions are typically reverse-biased

diodes & also experience junction leakage into the
substrate or well

• Both mobility & threshold voltage decrease with rising

temperature
• mobility effect tends to dominate for strongly ON
transistors, resulting in lower Ids at high temperature
• threshold effect is most important for OFF transistors,
resulting in higher leakage current at high temperature
K.SUJATHA , Associate Professor, BMSCE
 Nonideal I-V Effects
• In summary, MOS characteristics degrade with
temperature

• It is useful to have a qualitative understanding of

nonideal effects to predict their impact on circuit
behavior & to be able to anticipate how devices will
change in future process generations

• The effects lead to complicated I-V characteristics that

are hard to directly apply in hand calculations

• Instead, the effects are built into good transistor models &
simulated with SPICE or similar software
K.SUJATHA , Associate Professor, BMSCE
 (1)Velocity Saturation and Mobility Degradation
• Recall (v = µ E) that carrier drift velocity, & hence
current, is proportional to the lateral electric field
Elat = Vds / L between source & drain
• This is a good approximation for low fields, but breaks
down when strong lateral or vertical fields are applied as
shown in fig

• At high field strength,

drift velocity rolls off due to
carrier scattering &
eventually saturates at vsat
as shown in fig

K.SUJATHA , Associate Professor, BMSCE

 (1)Velocity Saturation and Mobility Degradation
• carrier velocity may be fitted with equation 2.23 where Esat is
determined empirically
• v sat= µ Esat is in the range of 6 - 10 x 106 cm/s for electrons &
4 – 8 x106cm/s for the holes . This corresponds to a saturation field
on the order of 2 x104 V/cm for
nMOS transistors
(2.23)
• Without velocity saturation , the saturation current is

(2.24)
• If the transistor were completely velocity saturated , v=vsat
and the current becomes Ids = Cox W(Vgs – Vt) vsat (2.25)
Observe that drain current is quadratically dependent on the
voltage without velocity saturation and linearly dependent when
fully velocity saturated. K.SUJATHA , Associate Professor, BMSCE
 (1)Velocity Saturation and Mobility Degradation
• For moderate supply voltages , transistors operate in a
region where the velocity no longer increases linearly with
field , but also not completely saturated
• α – Power Law model given in equation 2.26 provides a
simple approximation to capture this behaviour. α is called
the velocity saturation index & is determined by curve
fitting measured I-V data. (2.26)

K.SUJATHA , Associate Professor, BMSCE

 (1)Velocity Saturation and Mobility Degradation
• Transistors with long channels or low VDD display quadratic I-V
characteristics in saturation & are modelled with α = 2 . As
transistors become more velocity saturated, increasing Vg has less
effect on current and α deceases, reaching 1 for transistors that are
completely velocity saturated
• For simplicity, model uses a straight line in the linear region
• Overall, the model is based on three parameters that can be
determined empirically from a curve fit of I-V characteristics:
α , β and Pv (2.26)

K.SUJATHA , Associate Professor, BMSCE

 (1)Velocity Saturation and Mobility Degradation
• As the channel lengths become shorter, the lateral field increase &
transistors become more velocity saturated (α closer to 1) if the
supply voltage is held constant
• Fig compares α-power law model against simulated results ( using α =
1.3). Fit is poor at low Vds , but current at Vds = VDD matches well
across the full range of Vgs

K.SUJATHA , Associate Professor, BMSCE

 (1)Velocity Saturation and Mobility Degradation
• low-field mobilty of holes is much lower than that of electrons, so
pMOS transistors experience less velocity saturation than nMOS
for a given VDD
• This shows up as a larger value for pMOS than for nMOS
transistors

K.SUJATHA , Associate Professor, BMSCE

 (1)Velocity Saturation and Mobility Degradation
• Strong vertical electrical fields resulting from large Vgs cause the
carriers to scatter against the surface & also reduce the carrier
mobility µ
• This effect is called Mobility Degradation
• It can be modelled by replacing µ with a smaller µeff that is a
function of Vgs

K.SUJATHA , Associate Professor, BMSCE

 (1)Velocity Saturation and Mobility Degradation
• Compute the effective mobilities for nMOS and pMOS transistors
when they are fully ON . Threshold voltage = 0.3 V and gate oxide
thickness = 10.5 Å.

• Use Vgs = 1.0 for ON transistors, remembering that we are treating

voltages as positive in a pMOS transistor. Substituting Vt = 0.3 V and tox
= 1.05 nm into EQ gives:

• µeff-n(Vgs = 1.0) = 96 cm2/V

• µeff-p (Vgs = 1.0) = 36 cm2/V

K.SUJATHA , Associate Professor, BMSCE

 (2)Channel Length Modulation
• Ideally, Ids is independent of Vds for a transistor in
saturation, making the transistor a perfect current source.
• The reversed biased p–n junction between the drain and
body forms a depletion region with a width Ld that
increases with Vdb as shown in fig below
• The depletion region effectively shortens the channel length
to
Leff = L- Ld (2.28)

K.SUJATHA , Associate Professor, BMSCE

 (2)Channel Length Modulation
• To avoid introducing body voltage into our calculations,
assume the source voltage is close to the body voltage so
Vdb ≈ Vds
• Hence, increasing Vds decreases the effective channel
length
• Shorter channel length
results in higher current;
thus, Ids increases with
Vds in saturation,
as shown in Figure

K.SUJATHA , Associate Professor, BMSCE

 (2) Channel Length Modulation
• This can be crudely modelled by multiplying EQ 2.10
by a factor of (1 + Vds / VA)
 In saturation region, we find (2.29)

VA is called the Early voltage

As the channel length gets shorter , the effect of the channel
modulation becomes relatively more important.
Hence VA is proportional tochannel length
• Channel length modulation model is a gross oversimplification
of nonlinear behaviour & is more useful for conceptual
understanding than for accurate device modelling
• Channel length modulation is very important to analog
designers because it reduces the gain of amplifiers
• It is generally unimportant for qualitatively
understanding the behaviour of digital circuits
K.SUJATHA , Associate Professor, BMSCE
 (3) Threshold Voltage Effects
• So far, we treated the threshold voltage as a constant
• Vt increases with the source voltage, decreases with body
voltage, decreases with drain voltage, & increases with
channel length
• model each of these effects

K.SUJATHA , Associate Professor, BMSCE

 (3) Threshold Voltage Effects: Body Effect
• Transistor : Three-terminal device with gate, source, &
drain - body is an implicit fourth terminal
• When voltage Vsb is applied between the source & body, it
increases amount of charge required to invert the channel,
- it increases the threshold voltage
• The threshold voltage can be modelled as

-----2.30

• where Vt0 is the threshold voltage when the source is at the body
potential, ɸs is the surface potential at threshold and γ (gamma) is the
body effect coefficient, typically in the range 0.4 to 1 V1/2.
• In turn, these depend on the doping level in the channel, NA
K.SUJATHA , Associate Professor, BMSCE
 (3) Threshold Voltage Effects: (i)Body Effect
• The body effect further degrades the performance of pass
transistors trying to pass the weak value (e.g., nMOS
transistors passing a ‘1’)
• Later section - How a body bias can intentionally be applied
to alter the threshold voltage, permitting trade-offs between
performance & subthreshold leakage current
• ɸs surface potential at threshold -γ body effect coefficient

----2.31

-----2.32

K.SUJATHA , Associate Professor, BMSCE

 (3) Threshold Voltage Effects: (i)Body Effect
• For small voltages applied to the source or body, EQ (2.30)
can be linearized to

• At room temperature, the thermal voltage vT = kT/q = 26 mV

and ni = 1.45 × 1010 cm–3
K.SUJATHA , Associate Professor, BMSCE
 (3) Threshold Voltage Effects: (i) Body Effect

• Consider the nMOS transistor in a 180 nm process with a

nominal threshold voltage of 0.4 V and a doping level of
8 × 1017 cm–3. The body is tied to ground with a substrate
contact. How much does the threshold change at room
temperature if the source is at 1.1 V instead of 0?

K.SUJATHA , Associate Professor, BMSCE

 (3) Threshold Voltage Effects: Body Effect
• SOLUTION: At room temperature, the thermal voltage
vT = kT/q = 26 mV and ni = 1.45 × 1010 cm–3
• The threshold increases by 0.28 V

• = 60 V1/2

• = 0.68V
K.SUJATHA , Associate Professor, BMSCE
(3)Threshold Voltage Effects : (ii)Drain-Induced Barrier Lowering
• drain voltage Vds creates an electric field that affects the threshold
voltage. This drain-induced barrier lowering (DIBL) effect is
especially pronounced in short-channel transistors. It can be
modeled as
Vt =Vt0 - ƞVds

• where ƞ is the DIBL coefficient, typically on the order of 0.1

(often expressed as 100 mV/V)
• Drain-induced barrier lowering causes Ids to increase with Vds in
saturation, in much the same way as channel length modulation
does

K.SUJATHA , Associate Professor, BMSCE

 (3) Threshold Voltage Effects : (iii)Short Channel Effect
• threshold voltage typically increases with channel length
• This phenomenon is especially pronounced for small L where the
source & drain depletion regions extend into a significant portion
of the channel, & hence is called the short channel effect or Vt
rolloff
• In some processes, a reverse short channel effect causes Vt to
decrease with length
• There is also a narrow channel effect in which Vt varies with
channel width; this effect tends to be less significant because the
minimum width is greater than the minimum length

K.SUJATHA , Associate Professor, BMSCE

 (4) Leakage
• Even when transistors are nominally OFF, they leak small
amounts of current
• Leakage mechanisms include subthreshold conduction
between source & drain, gate leakage from the gate to
body, & junction leakage from source to body & drain to
body

K.SUJATHA , Associate Professor, BMSCE

 (4) Leakage
• Subthreshold conduction is caused by thermal emission of
carriers over the potential barrier set by the threshold
• Gate leakage is a quantum-mechanical effect caused by
tunneling through the extremely thin gate dielectric
• Junction leakage is caused by current through the p-n
junction between the source/drain diffusions & body

K.SUJATHA , Associate Professor, BMSCE

 (4) Leakage
• In processes with feature sizes above 180 nm, leakage was
insignificant except in very low power applications

• In 90 & 65 nm processes, threshold voltage has reduced to

the point that subthreshold leakage reaches levels of 1 -
10 nA per transistor, which is significant when multiplied
by millions or billions of transistors on a chip

• In 45 nm processes, oxide thickness reduces to the point

that gate leakage becomes comparable to subthreshold
leakage unless high-k gate dielectrics are employed

• Overall, leakage has become an important design

consideration in nanometer processes
K.SUJATHA , Associate Professor, BMSCE
 (4) Leakage : (a)Subthreshold leakage
• Ideal transistor I-V model assumes current only flows
from source to drain when Vgs > Vt
• In real transistors, current does not abruptly cut off below
threshold, but rather drops off exponentially, as shown

K.SUJATHA , Associate Professor, BMSCE

 (4) Leakage : (a)Subthreshold leakage
• When gate voltage is high, transistor is strongly ON
• When gate falls below Vt , exponential decline in current appears as a
straight line on logarithmic scale- this regime of Vgs < Vt is called weak
inversion

• Subthreshold leakage current increases significantly with Vds because of

drain-induced barrier lowering (DIBL)
• There is a lower limit on Ids set by drain junction leakage that is
exacerbated by the negative gate voltage

K.SUJATHA , Associate Professor, BMSCE

 (4) Leakage : (a)Subthreshold leakage
• Subthreshold leakage current is described by EQ (2.42)
• Ids0 is the current at threshold & is dependent on process & device geometry
• It is typically extracted from simulation but can also be calculated from EQ (2.43);
the e1.8 term was found empirically
• n is a process-dependent term affected by the depletion region characteristics & is
typically in the range of 1.3–1.7 for CMOS processes
• Final term indicates that leakage is 0 if Vds = 0, but increases to its full value when
Vds is a few multiples of the thermal voltage vT (e.g., when Vds > 50 mV)
• More significantly, drain-induced barrier lowering effectively reduces the threshold
voltage, as indicated by the ɳVds term
• This can increase leakage by an order of magnitude for Vds = VDD as compared to
small Vds. The body effect also modulates Vt when Vsb ≈ 0

-----(2.42)

-----(2.43)
K.SUJATHA , Associate Professor, BMSCE
 (4) Leakage : (a)Subthreshold leakage
• Subthreshold conduction is used to advantage in very-
low-power analog circuits
• It is also particularly important for dynamic circuits &
DRAMs, which depend on the storage of charge on a
capacitor
• Conduction through an OFF transistor discharges the
capacitor unless it is periodically refreshed or a trickle of
current is available to counter the leakage
• Leakage also contributes to power dissipation in idle
circuits
• Leakage increases exponentially as Vt decreases or as
temperature rises , so it is becoming a major problem for
chips using low supply & threshold voltages & for chips
operating at high temperature
K.SUJATHA , Associate Professor, BMSCE
 (4) Leakage : (a)Subthreshold leakage
• subthreshold current fits a straight line on a semilog plot
• inverse of the slope of this line is called the subthreshold
slope, S

• subthreshold slope indicates how much the gate voltage must drop
to decrease the leakage current by an order of magnitude
• A typical value is 100 mV/decade at room temperature
• EQ (2.42) can be rewritten using the subthreshold slope as

K.SUJATHA , Associate Professor, BMSCE

 (4) Leakage : (a)Subthreshold leakage
• Find the subthreshold leakage current of an inverter at
room temperature if the input A = 0. Let βn = 2βp = 1
mA/V2, n = 1.0, and |Vt| = 0.4 V. Assume the body effect
and DIBL coefficients are γ = ƞ = 0.

• vT = 26 mV at room temperature
• nMOS will be OFF & will see Vds = VDD, so its leakage
is

K.SUJATHA , Associate Professor, BMSCE

 (4) Leakage : (b)Gate leakage
• According to quantum mechanics, the electron cloud surrounding an atom has a
probabilistic spatial distribution
• For gate oxides thinner than 15–20 Å, there is a nonzero probability that an
electron in the gate will find itself on the wrong side of the oxide, where it will
get whisked away through the channel
• This effect of carriers crossing a thin barrier is called tunneling, & results in
leakage current through the gate
• Two physical mechanisms for gate tunneling are called Fowler-Nordheim (FN)
tunneling & direct tunneling
• FN tunneling is most important at high voltage & moderate oxide thickness & is
used to program EEPROM memories
• Direct tunneling is most important at lower voltage with thin oxides & is the
dominant leakage component. direct gate tunneling current can be estimated as

• where A and B are technology constants.

K.SUJATHA , Associate Professor, BMSCE
 (4) Leakage : (b)Gate leakage
• Transistors need high
Cox to deliver good ON
current, driving the
decrease in oxide
thickness
• Tunneling current
drops exponentially
with the oxide
thickness and has only
recently become
significant
• Figure 2.21 plots gate
leakage current density
(current/area) JG
against voltage for
various oxide
thicknesses

K.SUJATHA , Associate Professor, BMSCE

 (4) Leakage : (b)Gate leakage
• Gate leakage increases by a factor of 2.7 or more per angstrom
reduction in thickness
• Large tunneling currents impact not only dynamic nodes but also
quiescent power consumption & thus limits equivalent oxide
thicknesses tox to at least 10.5 Å to keep gate leakage below 100 A/cm2
• To keep these dimensions in perspective, recall that each atomic layer
of SiO2 is about 3 Å, so such gate oxides are a handful of atomic layers
thick
• innovations in gate insulators with higher dielectric constants that offer
good Cox while reducing tunneling
• Tunneling current can be an order of magnitude higher for nMOS than
pMOS transistors with SiO2 gate dielectrics because the electrons
tunnel from the conduction band while the holes tunnel from the
valence band and see a higher barrier
• Different dielectrics may have different tunneling properties
K.SUJATHA , Associate Professor, BMSCE
 (4) Leakage : (c) Junction leakage
• p–n junctions between diffusion & substrate or well form diodes, as
shown in Fig2.22
• well-to-substrate junction is another diode
• substrate & well are tied to GND or VDD to ensure these diodes do not
become forward biased in normal operation
• However, reverse-biased diodes still conduct a small amount of current
ID

K.SUJATHA , Associate Professor, BMSCE

 (4) Leakage : (c) Junction leakage
• Reverse-biased diodes still conduct a small amount of current ID

• where IS depends on doping levels & on the area & perimeter of the
diffusion region & VD is the diode voltage (e.g., –Vsb or –Vdb)

• When a junction is reverse biased by significantly more than the

thermal voltage, the leakage is just –IS, generally in the 0.1–0.01
fA/µm2 range, which is negligible compared to other leakage
mechanisms
• More significantly, heavily doped drains are subject to band-to-band
tunneling (BTBT) and gate-induced drain leakage (GIDL)
K.SUJATHA , Associate Professor, BMSCE
 (5) Temperature Dependence
• Transistor characteristics are influenced by temperature
• Carrier mobility decreases with temperature
• An approximate relation is

• where T is the absolute temperature, Tr is room temperature, and kµ

is a fitting parameter with a typical value of about 1.5.
• vsat also decreases with temperature, dropping by about 20% from
300 to 400 K
• Magnitude of the threshold voltage decreases nearly linearly with
temperature & may be approximated by

• where kvt is typically about 1–2 mV/K

K.SUJATHA , Associate Professor, BMSCE
 (5) Temperature Dependence
• Ion at high VDD decreases with temperature. Subthreshold leakage
increases exponentially with temperature. BTBT increases slowly with
temperature, and gate leakage is almost independent of temperature.
• The combined temperature effects are shown in Fig 2.23
• ON current Idsat normally decreases with temperature, as shown in Fig
2.24, so circuit performance is worst at high temperature

K.SUJATHA , Associate Professor, BMSCE

 (5) Geometry Dependence
• Layout designer draws transistors with width & length Wdrawn Ldrawn
• Actual gate dimensions may differ by some factors XW XL
• eg : manufacturer may create masks with narrower polysilicon or may
over etch the polysilicon to provide shorter channels (negative XL)
without changing the overall design rules or metal pitch
• source & drain tend to diffuse laterally under the gate by LD, producing
a shorter effective channel length that the carriers must traverse
between source & drain
• WD accounts for other effects that shrink the transistor width
• Putting these factors together, we can compute effective transistor
lengths & widths that should be used in place of L and W in the current
& capacitance equations
• Factors of two come from lateral diffusion on both sides of the channel

K.SUJATHA , Associate Professor, BMSCE

 (5) Geometry Dependence
• Therefore, a transistor drawn twice as long may have an effective length
that is more than twice as great
• Similarly, two transistors differing in drawn widths by a factor of two may
differ in saturation current by more than a factor of two
• Threshold voltages also vary with transistor dimensions because of the short
& narrow channel effects
• Combining threshold changes, effective channel lengths, channel length
modulation, and velocity saturation effects, Idsat does not scale exactly as
1/L
• In general, when currents must be precisely matched (e.g., in sense
amplifiers or A/D converters), it is best to use the same width & length for
each device
• Current ratios can be produced by tying several identical transistors in
parallel
• In processes below 0.25 µm, the effective length of the transistor also
depends significantly on the orientation of the transistor
• Amount of nearby polysilicon also affects etch rates during manufacturing
& thus channel length
• Transistors that must match well should have the same orientation. Dummy
polysilicon wires can be placed nearby to improve etch uniformity
K.SUJATHA , Associate Professor, BMSCE
VLSI Design Flow

K.SUJATHA , Associate Professor, BMSCE

 System Specification
(a)The algorithm to be implemented in detail with
mathematical representation –determines the complexity of the
design & gives idea of number of gates required.
(b)Number of inputs & outputs in the design & the
number of bits in each of them- type of interfacing to be used
with the chip & determines the number of pins to be used in the chip
(c)Number of bits used in the internal arithmetic
operation-this is generally kept higher than the input bus size in order
to avoid chances of overflow & underflow
(d)Number of clock signals to be used in the design-
clock routing requires dedicated channels, which must be considered
during fabrication of the chip
(e)Maximum clock frequency to be used
(f)Area of the chip
(g)Power dissipation in the chip
K.SUJATHA , Associate Professor, BMSCE
 Architectural Design
Design Engineers design the Architecture according to
the system design.

K.SUJATHA , Associate Professor, BMSCE

 Functional and Logic Design
Functionality of the design is identified:
Specify the hardware implementation of the system functionality
Outcome of the functional design is usually a timing diagram
Logic Design : register allocation , logic and arithmetic
operations of the design that represent the functional design are
derived and tested - this description – RTL description- system
specification is expressed in hardware description language
RTL is used for simulation to test the functionality with the help of
EDA tools
Functional verification is performed to ensure the RTL design is
done according to the specifications
RTL code is converted to gate level netlist using synthesis tools
.Netlist is a description of the circuit in terms of gates and
connections between them
To verify whether the synthesis tool has correctly generated the
gate-level netlist a verification should be done.
K.SUJATHA , Associate Professor, BMSCE
 Design Entry
In design entry all architectural decisions like number of sub-
blocks to be used with their functionality & interconnects such as
adders, multipliers, dividers, type of processing , serial or parallel,
in each sub-blocks and whether the sub-blocks will be pipelined,
number of stages pipeline and operation in each stage , to be taken.

Design entry is of two types-

(a) Schematic Entry

(b) Hardware description language(HDL) Entry

K.SUJATHA , Associate Professor, BMSCE

 Design Entry-Schematic
In schematic entry, schematics are drawn on schematic sheets
using Graphical User Interface(GUI).
Schematic library is available which consists symbol of basic gates
and flip-flops that are termed as primitive cells
The cells required to make a design are invoked on the sheet.
Each cell dragged on the sheet is given specific instance name .
Interconnection between components is done using nets for single
bit-line and busses for multiple bit-line and nets and buses are also
given name.
Then the naming of inputs & outputs is done.
A symbol can be created from the design with the same input &
output naming convention and can be kept in the cell library as a
macro cell.
Vendors also provide some macro cells in the cell library.

K.SUJATHA , Associate Professor, BMSCE

 Design HDL
The two dominant hardware description languages that are used
largely today are

(i) VHDL
(ii) Verilog HDL

Both languages are aimed at describing digital hardware.

A digital design can be expressed either structurally, in a dataflow
style or in a sequential behaviour.

K.SUJATHA , Associate Professor, BMSCE

Design Entry

K.SUJATHA , Associate Professor, BMSCE

 Functional simulation
For schematics and HDL designs , functional simulation is
performed before implementation to verify that the logic created is
correct or not.

K.SUJATHA , Associate Professor, BMSCE

 Circuit Design
Circuit is designed based on the logic design. The Boolean
expressions are converted into circuit representation by taking into
consideration the power and speed requirement of the original
design.
Circuit simulation is used to verify the correctness and timing of
each component
Diagram consists of circuit element like gates and transistors.

K.SUJATHA , Associate Professor, BMSCE

 Physical Design - Planning Placement and Routing(PPR)
This part is referred as the VLSI physical design or layout phase.
This is the process to determine the physical location of the
devices and make interconnection between them inside the
boundary of VLSI chip.
Since the cost of circuit fabrication increases in proportion with
circuit area , so one of the main aims in layout phase is to minimize
the circuit area so that cost of the chip is reduced.

If the chip area is smaller, it will have fewer defects also, which in
turn increases the yield .
The other criteria to be filled are wire length minimization, delay
minimization, power minimization, via minimization.
Automated design process using Computer Aided Design(CAD)
tools

K.SUJATHA , Associate Professor, BMSCE

 Physical Design - Planning Placement and Routing(PPR)

The various phases in layout process are as follows:

Partitioning is the task of dividing a circuit in such a

way so that area of each sub-circuits is well within
prescribed range and number of interconnection between
sub-circuits is also minimized.

In VLSI Physical design , partitioning is the first step of

solving a large problem by converting it to smaller sub-
problems of manageable size.

K.SUJATHA , Associate Professor, BMSCE

 Physical Design - Planning Placement and Routing(PPR)
Floor planning is the step to determine the shape of
each subcircuit module and pin locations at their
boundary and find out the approximate location of each
module in a rectangular chip.
A good floor planning aims to reduce the chip area ,
make the subsequent routing phase simpler and improve
performance like signal delay reduction.

K.SUJATHA , Associate Professor, BMSCE

 Physical Design - Planning Placement and Routing(PPR)

Placement is the problem of determining of the best position of

each module , when each module has a fixed shape, area and
terminals.
Floor planning and placements are very closely related and
sometimes combined in a computer aided design automation
process.

K.SUJATHA , Associate Professor, BMSCE

 Physical Design - Planning Placement and Routing(PPR)
Routing is the method of interconnection of different
circuit components , with an aim to minimize the chip
area and also reduction of total wire-length
Routing consists of a two step approach: Global routing
is done first and then followed by channel routing
The main aim of global routing is to develop a routing
plan so that each net is assigned a particular region
It partitions routing region to disjoint rectilinear
subregions and also give estimation of total wire- length.
Then detailed routing is done to effectively realize the
interconnections .

K.SUJATHA , Associate Professor, BMSCE

 Planning Placement and Routing(PPR)

After planning placement & routing there is a possibility

that all components may not fit in a given chip size or if
they fit, the design may not be routed.

Then a few iterations of planning , placement & routing

is done to achieve successful routing.

If it still fails , then design entry is revisited by changing

some parallel processors to serial processors, since serial
processor needs lesser components than parallel
processing.

K.SUJATHA , Associate Professor, BMSCE

 Timing Simulation
After the design is fitted into chip, net delays and gate
delays come into account.

Net delays are delays encountered by a signal for

traversing from output of one gate to the input of other
gate.
Gate delays are delays from input of one gate to the
output of the same gate.

Timing simulation is done with the clock speed as per

mentioned in design specification.

K.SUJATHA , Associate Professor, BMSCE

 Physical Verification and sign off
Physical verification check like layout vs schematic
(LVS) and Design Rule Check (DRC)

DRC verifies whether the given layout satisfies the

design rules provided by the fabrication team

DRC rules – physical checks of spacing rules between

metals , minimum width rules, via rules

LVS- layout is compared schematic for verifying

whether their functionality match

K.SUJATHA , Associate Professor, BMSCE

 Fabrication
Tape out is the final result of the design process for
integrated circuits before they are sent for
manufacturing

Tape out is specifically the point at which the graphic

for photo mask of the circuit is sent to foundry

Fabrication process consists of several steps – wafer

growth, epitaxial growth, masking, doping, deposition
and diffusion of various materials on the wafer. One
mask is used during each step

K.SUJATHA , Associate Professor, BMSCE

 Packaging and Testing
Each of the wafers contains hundreds of chips . These
chips are separated and packaged by a method called
scribing and cleaving . Chips that fail the electrical test
are discarded.
Each chip is packaged and tested to ensure that it meets
all the design specifications and functions properly

K.SUJATHA , Associate Professor, BMSCE

 Exercise2.2
• 2.2Show that the current through two transistors in
series is equal to the current through a single transistor
of twice the length if the transistors are well described
by the Shockley model. Specifically, show that
IDS1 = IDS2 in Figure 2.32 when the transistors are in
their linear region: VDS < VDD – Vt , VDD > Vt (this is
also true in saturation).
• Hint: Express the currents of the series transistors in
terms of V1 and solve for V1.

K.SUJATHA , Associate Professor, BMSCE

Exercise2.2

K.SUJATHA , Associate Professor, BMSCE

 Exercise2.3
• In Exercise 2.2, the body effect was ignored. If the body effect is
considered, will IDS2 be equal to, greater than, or less than IDS1? Explain.

The body effect does not change (a) because Vsb = 0

Body effect raises the threshold of the top transistor in (b) because Vsb > 0
This lowers the current through the series transistors, so IDS1 > IDS2

K.SUJATHA , Associate Professor, BMSCE

 Example 2.5
• Consider the nMOS transistor in a 65 nm process with a nominal threshold
voltage of 0.3 V and a doping level of 8 × 1017 cm–3. The body is tied to
ground with a substrate contact. How much does the threshold change at
room temperature if the source is at 0.6 V instead of 0?.

K.SUJATHA , Associate Professor, BMSCE

 Example 2.5
• SOLUTION: At room temperature, the thermal voltage vT = kT/q = 26
mV and ni = 1.45× 1010 cm–3. The threshold increases by 0.04 V.

K.SUJATHA , Associate Professor, BMSCE

 Exercise 2.10
• An nMOS transistor has a threshold voltage of 0.4 V and a supply voltage
of VDD =1.2 V. A circuit designer is evaluating a proposal to reduce Vt by
100 mV to obtain faster transistors.
a) By what factor would the saturation current increase (at Vgs = Vds = VDD) if
the transistor were ideal?
b) By what factor would the subthreshold leakage current increase at room
temperature at Vgs = 0? Assume n = 1.4.
c) By what factor would the subthreshold leakage current increase at 120 °C?
Assume the threshold voltage is independent of temperature.

K.SUJATHA , Associate Professor, BMSCE

 Question bank
1)Examine the effects of Subthreshold Conduction.
An nMOS transistor has a threshold voltage of 0.4 V and a supply voltage of
VDD = 1.2 V. A circuit designer is evaluating a proposal to reduce Vt by 100
mV to obtain faster transistors.
(i) By what factor would the saturation current increase (at Vgs = Vds = VDD)
if the transistor were ideal?
(ii) By what factor would the subthreshold leakage current increase at room
temperature at Vgs = 0? Assume n = 1.4
2) With neat diagrams , examine the effects of the following.
i) Body effect ii)Tunnelling iii)Velocity saturation
iv)Mobility degradation v)Channel Length Modulation
vi) Subthreshold Leakage vii) Junction Leakage
viii) Temperature Dependence iX)Geometry Dependence
3) Consider an NMOS transistor in 180 nm process with nominal VT of 0.4 V
and doping levels of 8*1017/cm3. Estimate the new VT if the source is at 1.1V
instead of 0 V. Given: Tox=40 Å, thermal voltage at room temp=26mV,
ni=1010/cm3, q=1.6*10-19C & εsi=11.7.
K.SUJATHA , Associate Professor, BMSCE
 Question bank
3. Using a flow chart and an example, explain the general overview of the
design hierarchy in VLSI.

4. With a neat diagram, Explain the physical structure of a MOSFET.

5.Construct the CMOS logic gate for the functions

(a) h = (b) g =

(c) Three input NAND gate

6. Designa transistor-level schematic for a compound CMOS logic gate for

each of the following functions:

(i) Y =
(ii) Y =
K.SUJATHA , Associate Professor, BMSCE
 Question bank
7. A 90 nm long transistor has a gate oxide thickness, tox of 16 Å. Estimate its
gate capacitance per micron of width? Given: εsio2=3.9, εo=8.854*10-14F/cm.

8. Compute the effective mobilities for nMOS and pMOS transistors when
they are fully ON . Threshold voltage = 0.3 V and gate oxide thickness = 10.5
Å.
9. Analyze the three non-ideal threshold voltage effects in submicron
transistor (below 1 micron channel length)
10. Illustrate with a neat schematic, the current flow in an FET.
11. Derive a Shockley model ( long channel / Ideal /first-order) relating
current & voltage (I-V) for an nMOS transistor in different regions.
12. Discuss the C-V characteristics based on simple MOS Capacitance Model.
13. Discuss the C-V characteristics based on detailed MOS Capacitance
Model.
14. Compare the simulated I-V characteristics of a 1-micron wide nMOS
transistor in a 65 nm process to the ideal characteristics .
K.SUJATHA , Associate Professor, BMSCE