GOVERNMENT POLYTECHNIC, AHEMDABAD

EC DEPARTMENT
6th SEM
Subject : VLSI Subject Code :- 3361104
Lecture Notes for CH-3
COMBINATIONAL LOGIC MOS CIRCUITS

 Combinational logic circuits or gates, which perform Boolean operations on multiple input variables and
determine the outputs as Boolean functions of the inputs, are the basic building blocks of all digital systems

 Node voltages, referenced to the ground potential, represent all input variables.
 Using positive logic convention, the Boolean (or logic) value of "1" can be represented by a high voltage of VDD,
and the Boolean (or logic) value of "0" can be represented by a low voltage of 0.
 The output node is loaded with a capacitance CL, which represents the combined capacitances of the parasitic
device in the circuit.

Q- Explain two input NAND Gate with depletion NMOS load

 Following figure shows logic symbol and truth table of NAND Gate.
 The Boolean AND operation is performed by the series connection of the two enhancement type nMOS driver
transistors
 Here, as a load, the depletion-type nMOS transistor is used.
 There is a conducting path between the output node and the ground only if the input voltage VA and the input
voltage VB are at high logic level.
 So when both VA and VB are high, the series-connected both driver transistors are turned on and hence the
output voltage will be low.

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  When any one or both of the input are low then either one or both of the driver transistors will be off, and the
output voltage will be pulled to a logic- high level by the depletion-type nMOS load transistor.

 Consider the NAND2 gate with both of its inputs equal to VOH. In this case, the drain currents of all transistors
in the circuits are equal to each other.

 Generalized NAND structure with multiple inputs

 Following Figure shows generalized n-input NAND gate, which consist of n series-connected driver transistor.

 Neglecting the substrate bias effect and assuming that the threshold voltages of all transistors are equal to V TO
the driver current ID in the linear region and in Saturation region is as below.


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  Hence, the (W/L) ratio of the equivalent driver transistor is

 In series-connected transistors are identical, i.e. (W/L)1 = (W/L)2 = ………… = (W/L).

 The width-to-length ratio of the equivalent transistor becomes

 Hence when all inputs are at logic- high level, the series structure consisting of n driver transistors has an
equivalent (W/L) ratio of (W/L) driver .

[ (W/L) ratio of all NAND driver transistor is (W/L)1=(W/L)2 = …….n (W/L) driver.].

 So for a two-input NAND Gate, each driver transistor must have a (W/L) ratio twice that of the equivalent
inverter driver.
 If the area occupied by the depletion-type load transistor is negligible, the resulting NAND2 structure will
occupy approximately four time the area occupied by the equivalent inverter.

Q- Explain two input NOR Gate with depletion NMOS load

 The circuit diagram, the logic symbol and the corresponding truth table of the NOR gate is as given below.
 Note that the substrate bias of all the transistors are connected to ground.

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  The Boolean OR operation is performed by the parallel connection of the two enhancement-type nMOS driver
transistors.
 If the input voltage VA or the input voltage VB is equal to the logic-high level, the corresponding driver transistor
turns on and provides a conducting path between the output node and the ground.
 Hence the output voltage becomes low.
 When both VA and VB are low, both driver transistors remains cut-off and the output node voltage is pulled to
a logic-high level by the depletion-type nMOS load transistor.

 Generalized NOR structure with multiple inputs

 Following Figure shows generalized n-input NOR gate, which consist of N parallel -connected driver transistor.

 The combined current ID in this circuit is supplied by the driver transistors which are turned on, i.e., transistors
which have gate voltages higher than the threshold voltage VTO.

 The combined pull-down current can be expressed as follows :

 Assuming that the input voltages of all driver transistor are identical
VGS,k = VGS for k = 1,2,3,……,n
 The multiple-input NOR gate can also be reduced to an equivalent inverter as shown in following
Figure. The (W/L) ratio of the driver transistor is

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 Figure : Equivalent inverter circuit corresponding to the n-input NOR gate

 Note that the source terminal of all enhancement-type nMOS driver transistors in the NOR gate are
connected to ground. Thus the drivers do not experience any substrate-bias effect.
 The depletion-type nMOS load transistor, however, is subject to substrate-bias effect, since its source is
connected the the output node, and its source-to-substrate voltage is VSB = Vout.

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CMOS Logic Circuits

There are mainly two CMOS Logic Circuits widely used

(1) CMOS Two input NOR Gate and

(2) CMOS Two input NAND Gate

For the design of any circuit with the CMOS technology; We need parallel or series connections of nMOS and pMOS
with a nMOS source tied directly or indirectly to ground and a pMOS source tied directly or indirectly to Vdd. A basic
CMOS structure of any 2-input logic gate can be drawn as follows:

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Q- Explain Two input NAND Gate using CMOS logic
 The circuit consists of a Series-connected n-net and a Parallel-connected complementary p-net. The input
voltages VA and VB are applied to the gates of one nMOS and one pMOS transistor.
 Following figure shows Two input NOR gate using CMOS logic and truth table of NOR gate.

 Now let’s understand how this circuit will behave like a NAND gate. The circuit output should follow the same
pattern as in the truth table for different input combinations.
1. CASE 1 : VA =0 AND VB =0
 As VA and VB both are low, both the pMOS will be ON and both the nMOS will be OFF.
 So the output Vout will get two paths through two ON pMOS to get connected with Vdd.
 The output will be charged to the Vdd level.
 The output line will not get any path to the GND as both the nMOS are off.
 So, there is no path through which the output line can discharge. The output line will maintain the
voltage level at Vdd; so, High.
2. CASE 2 : VA = 0 AND VB = 1
 VA – 0 : pMOS1 – ON; nMOS1 – OFF
 VB – 1 : pMOS2 – OFF; nMOS2 - ON
 pMOS1 and pMOS2 are in parallel. Though pMOS2 is OFF, still the output line will get a path through
pMOS1 to get connected with Vdd.
 nMOS1 and nMOS2 are in series. As nMOS1 is OFF, so Vout will not be able to find a path to GND to
get discharged.
 This in turn results the Vout to be maintained at the level of Vdd; so, High

3. CASE 3 : VA = 1 AND VB =0

• VA – 1 : pMOS1 – OFF; nMOS1 – ON

• VB – 0 : pMOS2 – ON; nMOS2 – OFF
Vout will be high as explained above.

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 4. CASE 4 : VA = 1 AND VB =1

• VA – 1 : pMOS1 – OFF; nMOS1 – ON

• VB – 1 : pMOS2 – OFF; nMOS2 – ON
 In this case, both the pMOS are OFF. So, Vout will not find any path to get connected with Vdd.
 As both the nMOS are ON, the series connected nMOS will create a path from Vout to GND.
 Since, the path to ground is established, Vout will be discharged; so, Low.

In all the 4 cases we have observed that Vout is following the exact pattern as in the truth table for the corresponding
input combination.

 The output voltage of the CMOS, two input NOR gate will get a logic-low voltage of VOL = 0 and a logic-high
voltage of VOH = VDD. The equation of the switching threshold voltage Vth is given by

Q- Explain Two input NOR Gate using CMOS logic

• The circuit consists of a parallel-connected n-net and a series-connected complementary p-net. The input voltages VA
and VB are applied to the gates of one nMOS and one pMOS transistor.

• Following figure shows Two input NOR gate using CMOS logic and truth table of NOR gate.

• Now let’s understand how this circuit will behave like a NOR gate. The circuit output should follow the same pattern
as in the truth table for different input combinations.

1. CASE 1 : VA =0 AND VB =0

• VA – 0 : pMOS1 – ON; nMOS1 – OFF

• VB – 0 : pMOS2 – ON; nMOS2 – OFF
 Path establishes from Vdd to Vout through the series connected ON pMOS transistors and Vout gets charged to
Vdd level. No path from Vout to GND. Therefore, no discharging and hence Vout will be High.

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 2. CASE 1 : VA =0 AND VB =1

 VA – 0 : pMOS1 – ON; nMOS1 – OFF

• VB – 1 : pMOS2 – OFF; nMOS2 – ON
 In this case path establishes from Vout to GND through nMOS2, but no path to Vdd. So, Vout would get
discharged and will be at level Low.

3. CASE 1 : VA = 1 AND VB = 0

• VA – 1 : pMOS1 – OFF; nMOS1 – ON

• VB – 0 : pMOS2 – ON; nMOS2 – OFF
 The explanation is similar as case-2. Vout will be at level Low.

4. CASE 1 : VA = 1 AND VB = 0

• VA – 0 : pMOS1 – OFF; nMOS1 – ON

• VB – 1 : pMOS2 – OFF; nMOS2 – ON
 No path to Vdd. Path establishes from Vout to GND. So, Vout will be at level Low.

 In all the 4 cases we have observed that Vout is following the expected value as in 2 input NOR gate truth table.

 The equation of the switching threshold voltage Vth is given by

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Complex Logic Circuits
NMOS Depletion Load Complex Logic Gate

Q- Realize ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝒁 = 𝑷(𝑺 + 𝑻) + 𝑸𝑹 Using nMOS Logic

 To realize complex functions of multiple input variables, the basic circuit structures and design principles
developed for NOR and NAND can be extended to complex logic gates.
 The ability to realize complex logic functions, using a small number of transistors is one of the most attractive
features of nMOS and CMOS logic circuits.
 Consider the following Boolean function as an example.

 The nMOS depletion-load complex logic gate used to realize this function is shown in figure.

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  In this figure, the left nMOS driver branch of three driver transistors is used to perform the logic function P (S
+ T), while the right-hand side branch performs the function QR.
 By connecting the two branches in parallel, and by placing the load transistor between the output node and
the supply voltage VDD, we obtain the given complex function.
 Each input variable is assigned to only one driver.
 simple design principles of the pull-down network is :−

o OR operations are performed by parallel-connected drivers.

o AND operations are performed by series-connected drivers.
o Inversion is provided by the nature of MOS circuit operation.

 If all input variables are logic-high in the circuit realizing the function, the equivalent driver (W/L) ratio of the
pull-down network consisting of five nMOS transistors is

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Q- Realize XOR Function using NMOS Depletion Load Complex Logic Gate

 For XOR gate, logic symbol and Boolean function and truth table is is :

A B F
0 0 0
0 1 1
1 0 0
1 1 0

 Above circuit is equivalent to

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  Now we will restructure the above logic
XOR = ̅̅̅̅̅̅̅̅
𝑋𝑁𝑂𝑅

A𝐵̅ + 𝐴̅B = ̅̅̅̅̅̅̅̅̅̅̅̅

𝐴𝐵 + 𝐴̅𝐵̅
 Here we require NORing of AB and 𝐴̅𝐵̅.
 So operations are performed by parallel-connected drivers for AB and 𝐴̅𝐵̅

Q- Realize XNOR Function using NMOS Depletion Load Complex Logic Gate

 For XNOR gate, logic symbol and Boolean function and truth table is :

 The above circuit is equivalent to

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  Now we will restructure the above logic
 XNOR = ̅̅̅̅̅̅
𝑋𝑂𝑅
 AB + 𝐴̅𝐵̅ = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
( 𝐴𝐵̅ + 𝐴̅𝐵 )

 ̅ 𝑎𝑛𝑑 𝐴̅𝐵
Here we require NORing of 𝐴𝐵

 ̅ and 𝐴̅𝐵
So operations are performed by parallel-connected drivers for 𝐴𝐵

Complex CMOS Logic Gates

 The realization of the n-net, or pull-down network, is based on the same basic design principles examined for
nMOS depletion-load complex logic gate.
 The pMOS pull-up network must be the dual network of the n-net.
 It means all parallel connections in the nMOS network will correspond to a series connection in the pMOS
network, and all series connection in the nMOS network corresponds to a parallel connection in the pMOS
network.
 The figure shows a simple construction of the dual p-net (pull-up) graph from the n-net (pull-down) graph for

Vout = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴(𝐷 + 𝐸) + 𝐵𝐶

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 o Rules for Logic Formation
o Rule 1: nMOS transistors in series implement the AND operation
o Rule 2: nMOS transistors in parallel implement the OR operation

 First the logic nMOS transistors are structured according to the rules above. The output of the function is the
complement of the nMOS logic. Now the pMOS transistor network has to be structured according to the
following rules:
o Rule 3: Parallel connections of nMOS transistors have to be transformed to serial connections of
pMOS transistors. The input literals applied to the pMOS transistors are identical with the gate
inputs of the nMOS transistors (no inversion needed)
o Rule 4 : Serial connections of nMOS transistors have to be transformed to parallel connections of
pMOS transistors. Input literals remain unchanged.

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Q- Realize F = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝑨. 𝑩 + 𝑪. 𝑫) Function using CMOS Logic

 Logic diagram of the above equation is

 We can understood as follow for Pull-down network we will arrange nMOS transistors as below

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  Now for Pull-Up network we will connect pMOS transistors as below

 So finally we can realize the function F = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅

(𝐴. 𝐵 + 𝐶. 𝐷) as below.

Q- Realize F = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝑨(𝑩𝑪 + 𝑫) ) Function using CMOS Logic

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 Q- Realize F = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝑨 (𝑩 + 𝑪)) using CMOS Logic

VDD

Q- Realize XOR Function using CMOS Logic

 Boolean equation and logic diagram for XOR function is given by

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  Now we will restructure the above logic
F = XOR = ̅̅̅̅̅̅̅̅
𝑋𝑁𝑂𝑅

F = A𝐵̅ + 𝐴̅B = ̅̅̅̅̅̅̅̅̅̅̅̅

𝐴𝐵 + 𝐴̅𝐵̅
 Here we require NORing of AB and 𝐴̅𝐵̅.
 So operations are performed by parallel-connected drivers for AB and 𝐴̅𝐵̅ in pull-down network .

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Q Explain Pseudo nMOS Logic

 In Pseudeo nMOS logic the pMOS network is substituted by one PMOS load transistor with its gate
grounded.
 Since the pMOS is not driven by signals, it is always ‘ON’.
 The effective gate voltage seen by the pMOS transistor is Vdd.
 It consists of a single pMOS load per gate and a nMOS pull-down network.
 An n-device pull-down or driver is driven with the input signal.
 This roughly equivalent to use of a depletion load is Nmos technology and is thus called ‘Pseudo-
NMOS’.
 The circuit is used in a variety of CMOS logic circuits.
 In this, PMOS for most of the time will be linear region. So resistance is low and hence RC time
constant is low.
 When the nMOS is turned ‘on', a direct path between supply and ground exists and static power will
be drawn. However, the dynamic power is reduced due to lower capacitive loading.

Features of pseudo-NMOS logic
o Advantages
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  Low area cost
 only N+1 transistors are needed for an N input gate
 Low input gate-load capacitance
o Disadvantage
 It dissipates static power, when pull-down network is on

 Following figure shows CMOS inverter circuit using pseudo-NMOS logic

CMOS Inverter using pseudo-NMOS logic

 Realization of Z = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑨𝑩 + 𝑪(𝑫 + 𝑬) Using pseudo nMOS logic

 XOR Function realization with pseudoNMOS logic

The XOR is defined

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 VLSI Design - Sequential MOS Logic Circuits
 Logic circuits are divided into two categories − (a) Combinational Circuits, and (b) Sequential Circuits.
 In Combinational circuits, the output depends only on the condition of the latest inputs.
 In Sequential circuits, the output depends not only on the latest inputs, but also on the condition of earlier
inputs. Sequential circuits contain memory elements.

 Sequential circuits are of three types −

 Bistable − Bistable circuits have two stable operating points and will be in either of the states. Example −
Memory cells, latches, flip-flops and registers.
 Monostable − Monostable circuits have only one stable operating point and even if they are temporarily
perturbed to the opposite state, they will return in time to their stable operating point. Example: Timers, pulse
generators.
 Astable − circuits have no stable operating point and oscillate between several states. Example − Ring
oscillator.

CMOS Logic Circuits

(1) SR Latch based on NOR Gate

 If the set input (S) is equal to logic "1" and the reset input is equal to logic "0." then the output Q will be forced
to logic "1". While 𝑄̅ is forced to logic "0". This means the SR latch will be set, irrespective of its previous state.

 Similarly, if S is equal to "0" and R is equal to "1" then the output Q will be forced to "0" while 𝑄̅ is forced
to "1". This means the latch is reset, regardless of its previously held state.

 Finally, if both of the inputs S and R are equal to logic "1" then both output will be forced to logic "0" which
conflicts with the complementarity of Q and 𝑄̅

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  Therefore, this input combination is not allowed during normal operation. Truth table of NOR based SR Latch
is given in table.

S R Q 𝑄̅ Operation

0 0 Q 𝑄̅ Hold

1 0 1 0 Set

0 1 0 1 Reset

1 1 0 0 Not allowed
 CMOS SR latch based on NOR gate is shown in the figure given below.

 If the S is equal to VOH and the R is equal to VOL, both of the parallel-connected transistors M1 and M2 will be
ON. The voltage on node 𝑄̅ will assume a logic-low level of VOL = 0.
 At the same time, both M3 and M4 are turned off, which results in a logic-high voltage VOH at node Q. If the R
is equal to VOH and the S is equal to VOL, M1 and M2 turned off and M3 and M4 turned on
.

(2) SR Latch based on NAND Gate

Block diagram and gate level schematic of NAND based SR latch is shown in the figure. The small circles at the S and
R input terminals represents that the circuit responds to active low input signals. The truth table of NAND based SR
latch is given in table

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 S R Q Q′ Operation

0 0 NC NC No change. Latch remained in present state.

1 0 1 0 Latch SET.

0 1 0 1 Latch RESET.

1 1 0 0 Invalid condition.

 If S goes to 0 (while R = 1), Q goes high, pulling 𝑄̅ low and the latch enters Set state
S = 0 then Q = 1 (if R = 1)
 If R goes to 0 (while S = 1), Q goes high, pulling 𝑄̅ low and the latch is Reset
R = 0 then Q = 1 (if S = 1)
 Hold state requires both S and R to be high. If S = R = 0 then output is not allowed, as it would result in an
indeterminate state.
 CMOS SR Latch based on NAND Gate is shown in figure.

(3) Clocked SR Latch

 The figure shows a NOR-based SR latch with a clock added. The latch is responsive to inputs S and R only
when CLK is high.

 When CLK is low, the latch retains its current state. Observe that Q changes state −
o When S goes high during positive CLK.
o On leading CLK edge after changes in S & R during CLK low time.
o A positive glitch in S while CLK is high
o When R goes high during positive CLK.

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  CMOS AOI implementation of clocked NOR based SR latch is shown in the figure. Note that only 12 transistors
required.
 When CLK is low, two series terminals in N tree N are open and two parallel transistors in tree P are ON, thus
retaining state in the memory cell.
 When clock is high, the circuit becomes simply a NOR based CMOS latch which will respond to input S and R.

(4) Clocked SR Latch based on NAND Gate

Circuit is implemented with four NAND gates. If this circuit is implemented with CMOS then it requires 16 transistors.

 The latch is responsive to S or R only if CLK is high.

 If both input signals and the CLK signals are active high: i.e., the latch output Q will be set when CLK = "1" S =
"1" and R = "0"
 Similarly, the latch will be reset when CLK = "1," S = "0," and
When CLK is low, the latch retains its present state.

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