Applied Soft Computing 13 (2013) 3285–3297

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Applied Soft Computing

journal homepage: www.elsevier.com/locate/asoc

Variable-Order Ant System for VLSI multiobjective floorplanning

Chyi-Shiang Hoo, Kanesan Jeevan ∗ , Velappa Ganapathy, Harikrishnan Ramiah
Department of Electrical Engineering, Faculty of Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia

a r t i c l e i n f o a b s t r a c t

Article history: Floorplanning is crucial in VLSI chip design as it determines the time-to-market and the quality of the
Received 24 September 2012 product. In this work, Variable-Order Ant System (VOAS) is developed and combined with a floorplan
Received in revised form model namely Corner List (CL) to optimize the area and wirelength. CL is used to represent the floorplan
10 December 2012
layout. Although CL has proven to have the same search space and time complexity as Corner Sequence
Accepted 23 February 2013
(CS), comparatively, CL has more corners to be selected. This compensates the sequence weakness, where
Available online 14 March 2013
modules can be placed freely onto the corners, which are not bounded by the floorplan contour. Two
groups of ants, namely VOAS and reconnaissance ants, which will collaborate with each other to deter-
Keywords:
Ant colony optimization
mine the local information, are introduced. Through this cooperation, VOAS ant can ascertain its local
Corner List representation information greedily, based on the local search space information carried out by reconnaissance ants.
VLSI Subsequently, VOAS ant proposes a new variable-order property to prioritize the global and local explo-
Floorplanning rations. The variable-order property enables the ants in VOAS to weigh a better choice of modules for
Physical design the floorplanning, based on the local and global information. The update rules of VOAS are modified in
order to handle two-dimensional problem, such as VLSI floorplanning. VOAS shows improved results in
terms of purely area optimization as well as composite function of area and wirelength, as compared to
other state-of-the-art and recent floorplanning/placement algorithms based on Microelectronics Centre
of North Carolina (MCNC) and Gigascale Systems Research Center (GSRC) benchmarks.
Crown Copyright © 2013 Published by Elsevier B.V. All rights reserved.

1. Introduction Floorplan layouts are modeled in a graph-based [3–9], tree-

based [10–13] or sequence-based representation [14–16] and
In modern integrated circuit (IC) design, a floorplan of an IC is optimized using tools such as mathematical programming [17]
a schematic representation of its major functional blocks. As tech- or artificial intelligence (AI) technique [16,18,19]. Although there
nology advances, the number of transistors in a very-large-scale are a number of metaheuristic algorithms adapted in VLSI floor-
integration (VLSI) design has increased rapidly obeying Moore’s planners such as Genetic Algorithm (GA) [20], and Evolutionary
law [1] whereas the features of IC have progressively scaled down. Algorithm (EA) [16] and many more, Simulated Annealing (SA) [21]
Moore’s law states the number of transistors in a chip doubles is preferred due to its easiness and flexibility to be adapted in differ-
in approximately every two years. This encourages the extension ent type of floorplan models. However, fairly huge computational
of the chip’s functions while maintaining the size of the chip. resources are required in SA due to its semi-exhaustive nature [22]
Hence, the circuit density and VLSI design complexity of an IC and thus unable to handle large scale VLSI floorplanning problems
have increased rapidly. As the features of the VLSI chip shrinks [23]. In Hierarchical Congregated Ant System (H-CAS) [19], SA opti-
over-time, many factors such as the total wire length, time delay, mization results are validated to be only marginally better than
routing congestion and overall power consumption, will affect the random-based searching algorithm’s as the number of modules in
reliability and performance of the chip. To regulate these issues, the VLSI floorplanning problem increases. This is due to the high
efficient floorplanning is required as it dictates the quality of dependency of SA approach on the initial solution generated and
the VLSI design. VLSI floorplanning design is a well-known Non- the size of the problem. SA tends to be trapped into local optima
deterministic Polynomial-time hard (NP-hard) problem [2,3] and when the scale of the problems increases.
thus, it is difficult to find ideal optimal solutions in practical appli- Swarm intelligence is a relatively new metaheuristics approach
cations. However, near-optimal solutions are attainable with the inspired by the sociable nature behaviors of insects or ani-
aid of combinatorial optimization. mals. Subsequently, ants have inspired a number of techniques
in optimizing the problem solving. After the first ant-based
metaheuristics, namely Ant System (AS) [24] was developed, AS
∗ Corresponding author. Tel.: +60 3 7967 5205; fax: +60 3 7967 5316. was further improved in [25] and was called as Ant Colony
E-mail addresses: [email protected], [email protected] System (ACS) algorithm. As a promising and fruitful metaheuris-
(C.-S. Hoo), [email protected], [email protected] (K. Jeevan). tics, ant-based metaheuristic algorithms have been successfully

1568-4946/$ – see front matter. Crown Copyright © 2013 Published by Elsevier B.V. All rights reserved.
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3286 C.-S. Hoo et al. / Applied Soft Computing 13 (2013) 3285–3297

adapted in many types of NP-hard problems such as Traveling priority of VOAS not only enables the ant to search for possible
Salesman Problem (TSP) [26], asymmetric TSP [27], minimum near-optimal solutions but also completes the floorplanning effec-
weight vertex cover problem [28], and structural topology tively. Analogically, the global information is represented by the
optimization [29]. pheromone while the instant local information is found through
the cooperation between the VOAS ant and reconnaissance ants
1.1. Our contributions (RAs) where RAs search for the instant local search information
greedily. An experiment is carried out to compare the efficiency
In this paper, a new metaheuristic algorithm namely Variable- of VOAS with commonly used ant-based metaheuristics, namely
Order Ant System (VOAS) is proposed to handle VLSI standard cells AS. VOAS shows improved results in terms of area and wirelength
floorplanning with optimized utilization of chip area or compo- optimization.
sition of both chip area utilization and wirelength. As a start of, a This article is organized as follows: Section 2 reviews the newly
sequence-based representation called Corner List (CL) is developed developed CL representation where the properties of the CL are
to model the floorplan layouts where the transformation between proven mathematically. Section 3 discusses the characteristics of AS
the representation and the layouts can be carried out in a linear algorithm. Section 4 highlights the proposed VOAS algorithm and
runtime. CL characteristics such as computational complexity and how VOAS handles VLSI floorplanning problem. In Section 5, the
search space are compared to the existing sequence-based state- experimental results are compared with the state-of-the-art and
of-the-art representations, namely Corner Sequence (CS) [14] and recent floorplanning algorithms. Finally, the conclusion is drawn
Moving Block Sequence (MBS) [15,16]. With a larger search space, in Section 6.
CL can perform the transformation between floorplan layout and
representation n times faster, as compared to MBS. Even though
the search space and time complexity of CL are same as CS, CL 2. Floorplan layout modeling
introduces more corners than CS as the latter only considers the
corners bounded by the floorplan contour. Thus, CL can search In this section, a new floorplan representation is presented,
more corners than CS within same period of time. Since contour namely corner list (CL). For the ease of understanding, the technical
is generated by previously placed modules, CL allows compensa- notations used in CL are defined below:
tion of sequence weakness, where modules can be placed freely
Definition 1. Two dummy modules mbottom and mleft are assumed
onto any corners, including those which are unbounded by the
to be located at bottom and left boundaries of the floorplan, with the
contour. This CL modeling is very important as it enables ant-based
dimensions of (width, height) equal to (∝, 0] and [0, ∝) respectively.
metaheuristics to search for near-optimal solution in a large search
space. Definition 2. Given a set of selected modules S ⊂ M, and arbitrary
Inheriting the major properties of Ant System (AS), VOAS has corner in the set of corner list C, namely [Cleft , Cbottom ], then C = {Cleft ,
adapted a unique variable-order property in route selection mech- Cbottom } ⊂ (S ∪ {mleft , mbottom }).
anism and modified the pheromone update rule, in order to handle
VLSI floorplanning. This variable-order property of VOAS utilizes Definition 3. For arbitrary corner [Cleft , Cbottom ] with corner mod-
the inter-dependency of the local and global information in order ules Cleft and Cbottom , assume the coordinates of the top-right
to ensure the later modules selected in the sequence list will corners of Cleft and Cbottom are denoted as (xTR-left , yTR-left ) and
always be greedily placed onto the floorplan. High dependency (xTR-bottom , yTR-bottom ) respectively, then, the corner is realizable
on global information at the beginning of the module floorplan- under the conditions of xTR-bottom ≥ xTR-left and yTR-left ≥ yTR-bottom .
ning is crucial as the ants in the floorplanning can make a better
decision based on the previous experience. This property allows a Definition 4. CL consists of two tuples where the first tuple repre-
perturbation which might lead to a better near-optimal solution. sents the sequence of modules chosen and the second tuple denotes
The importance of the global information will decrease gradu- the sequence of the corners chosen by the corresponding modules.
ally as the floorplanning approaches the final stage. Emphasizing CL can be represented as:
on the local information during the finalization of the floorplan-
ning, greedy VOAS ant completes the floorplanning by choosing CL = (˝, )
the remaining corner with less whitespace/wirelength. A wrong
choice by the ant in area-based problem will result in an unac- where
ceptable huge whitespace being created especially approaching
the end of the process, as shown in Fig. 1. Similarly, an improper ˝ = (˝1 , ˝2 , . . . , ˝n ); ˝i = mi ∈ M, ˝i =
/ ˝j , 0 ≤ i, j ≤ n,
choice in wirelength-based VLSI floorplanning problem will lead
 = (1 , 2 , . . . , n ); 0 ≤ i, j ≤ n,
to a floorplan layout with higher wirelength. This interchangeable

[mleft , mbottom ]; i=1
i =
Option 1 [Cleft−i , Cbottom−i ]; 2≤i≤n

Option 2

Option 1 Option 2 2.1. CL matrix representation

In the CL representation, modules are placed one at a time

Whitespace
according to a predefined sequence. After numerous permutations
generated
of modules placement, a CL matrix is formed. Let us consider an
(n × 3) CL matrix, shown in matrix (1), where n is the number
Zero whitespace
of modules placed in the layout. There are 3 configurations con-
cluding the placement of a particular module. The first column
Fig. 1. Whitespaces created for different final module selection by ant. represents the first tuple which is the sequence of modules to be
 C.-S. Hoo et al. / Applied Soft Computing 13 (2013) 3285–3297 3287

advantage of updating the corner coordinates’ is to ensure that

there is no overlap occurring in the floorplan layout. The condi-
tions of floorplan layout violating the overlapping constraint are
discussed in [30]. The property and theorems of CL are discussed
below:

Property 3.1. If the instant modules placed onto the floorplan are q,
the possible corners in the corner list are (q + 1).

Proof. When the first module is inserted, two corners arise, giv-
ing two choices for the second module. After the second module is
placed, the previous selected corner edges will be ignored and two
new corners are added into the corner list, leading to three cor-
ners to be placed for the third module. As the modules’ placements
proceed until the number of modules in the floorplan is equal to q,
there are always (q + 1) corners in the corner list and hence, (q + 1)
possible choices for the next module.

Theorem 3.1. If n denotes the number of modules in a placement,

the solution space of CL is bounded by O((n!)2 ).

Proof. Let us consider that there are n modules to be placed

in a chip. Hence, there are n! of permutations in the placement
Fig. 2. Examples of CL-layout transformation (dotted lines denote the contours) sequence. As depicted in Property 3.1, there is always (q + 1) possi-
where modules are placed in the sequence of (a)–(e).
ble corners in the corner list when the number of modules placed
onto the floorplan is q. Therefore, the solution search space of the
placed, whereas the second tuple is represented by the second and CL is bounded by:
the third columns.
⎛m ⎞ (n!) × 1 × 2 × 3 × · · · × n = (n!)2
3 mleft mbottom
n−1
⎜m m m ⎟
⎜ 2 3 bottom ⎟
⎜ ⎟
CL = ⎜
⎜ m1 m3 m2 ⎟ ⎟ (1) Theorem 3.2. The placement packing evaluation time of CL is
⎜ ⎟ bounded by O(n) time, where n is the number of modules.
⎝ m4 mleft m1 ⎠
Proof. The CL algorithm takes a constant time to insert a mod-
m5 m4 m1 ule into the corners in corner list. If there are n modules in a corner
sequence, the time complexity to insert the modules is O(n). In fact,
2.2. CL-placement transformation the elimination of a single corner after every placement of a mod-
ule costs less than O(n) time. Thus, the time complexity of the CL
Suppose a CL matrix is given as in matrix (1). Initially, we have placement is O(n).
two dummy modules, namely mleft and mbottom , and one corner cre-
ated by these dummy modules, namely [mleft , mbottom ]. Based on 2.4. Search and computational complexities comparisons
the first row in (1), module m3 is placed onto the contour edge at
the corner [mleft , mbottom ]. Through corner update as discussed in A summary of the search spaces and computational complex-
Section 2.3, two corners, namely [mleft , m3 ] and [m3 , mbottom ] are ities of state-of-the-art floorplan models are shown in Table 1. In
generated, as shown in Fig. 2(a). Subsequently, in Fig. 2(b), mod- Table 1, it is evident that CL possesses the largest search space and
ule m2 is inserted onto the corner of [m3 , mbottom ], leading to three the smallest computational complexity. It is to be noted that Chan
arising corners, which are [mleft , m3 ], [m3 , m2 ] and [m2 , mbottom ]. et al. [31] have studied that O(n) is the lowest linear evaluation
During the third module placement, module m1 is placed onto the complexity reported and this indicates that by using CL, a possi-
corner edge of [m3 , m2 ] where a new contour and an updated corner ble optimal solution can be evaluated within the shortest period
list are created, as demonstrated in Fig. 2(c). It is to be noted that of time. Even though CS has the same search space and computa-
corner [mleft , m1 ] is created in corner list instead of [m3 , m1 ]. This tional complexity as compared to CL, CL will consider (q + 1) instant
is because CL representation will compact the floorplan by consid- corner selections during every placement while the number of cor-
ering the leftmost and the bottommost edges which are parallel ners considered in CS is less than (q + 1). This indicates that even
to the newly generated corners. This process is repeated until all though CL and CS have the same bound of search space and com-
the modules are placed as shown in Fig. 2(d) and (e). The conver- putational complexity, CL is able to search more corners within the
sion between CL matrix and floorplan layout is reversible as the same period of time. This unique characteristic of CL allows it to
matrix-layout transition is direct and straight forward. compensate the weakness of sequence representation, where the
placements of modules highly depend on the contour constructed
2.3. Incremental CL’s corner update by previously selected modules.
In reference to another state-of-the-art sequential floorplan rep-
For every placement, the coordinates of the corners have to be resentation which is MBS, CL has a much lower computational
constantly updated so that the algorithm can recognize the exact complexity. In Table 1, it is observed that the computational com-
location of the placement. The corner coordinates are crucial since plexities of CL and MBS are O(n) and O(n2 ) respectively which
the algorithm identifies the coordinates before the module is placed concludes that CL can evaluate the packing within a runtime of n
onto its respective corner. In the event that the coordinates are times faster. On top of that, the search space of MBS is limited and
erroneous, the placement might not be aligned with the desired less as compared to CL where some possible optimal solutions are
locations, hence causing overlaps or gaps between modules. The excluded from the search. In conclusion, CL has an advantage in the
3288 C.-S. Hoo et al. / Applied Soft Computing 13 (2013) 3285–3297

Table 1
Summary of search spaces and computational complexity.

Floorplan representations Search space Computational complexity

Ordered Binary-Tree (B*-Tree) [10] O[(n!22n−1 )/n1.5 ] O(n)

Ordered tree (O-Tree) [11] O[(n!22n−1 )/n1.5 ] O(n)
Enhanced Ordered Tree (Enh. O-Tree) [12] O[(n!22n−1 )/n1.5 ] O(n2 )
Transitive Closure Graph (TCG) [6] O((n!)2 ) O(n2 )
Transitive Closure Graph-Sequence (TCG-S) [5] O((n!)2 ) O(n·log n)
Sequence Pair (SP) [3] O((n!)2 ) O(n2 )
Fast Sequence Pair (Fast-SP) [7] O((n!)2 ) O(n·log(log n))
Twin Binary Sequence (TBS) [13] O[(n!23n )/n1.5 ] –
Corner Block List (CBL) [4] O[(n!23n−3 )/n1.5 ] O(n)
Moving Block Sequence (MBS) [15,16] O(n!22n−2 ) O(n2 )
Enhanced Quadrate-state Sequence (Enh. Q-Seq.) [8] O[(26n ·(2n)!)/n1.5 ] O(n)
Corner Sequence (CS) [14] O((n!)2 ) O(n)
CL O((n!)2 ) O(n)

context of the search space and computational complexity while Problems data fetch
enabling the compensation the weaknesses of sequence-based rep-
resentation.
Initialization
Parameters settings.
stage
3. Ant-based metaheuristics
City selection and instant path construction
through statistical computation. Construction
In nature, ant colony is a well-known successful swarm of stage
insects where the swarm works cooperatively to find food and Instant travel of ant to the selected city.
defend their own colony. Impressively, ants are unique insects with
sociable ability where this intelligence enables them to identify No Tour done?
food source in shortest path which leads more colonial ants to the
Yes Feedback
same path of food search. This effective and converging food for- stage
aging behavior is an outcome of the cooperative work of all the Pheromone update.
ants. In biological nature, ants explore the food source randomly
at the initial stage and will deposit a chemical compound namely Loop done? No
pheromone on their trails between the nest and the food source. The
pheromone level on the trails contains the previous travel experi- Yes
ence about the particular food source and based on the pheromone Problem outcome.
trail, the other colonial ant will choose the path. The path with the
Fig. 3. Overview of ant-based metaheuristic algorithms.
higher pheromone level is preferred as it indicates a larger amount
of food source and higher frequency of ant traversing in the path.
As more ants travel on the particular path, more pheromone will 3.2. Ant System
be deposited and the pheromone deposition on this particular path
will undergo a snowball effect. Nevertheless, all the pheromone will Inspired by the ant colony foraging behavior, the first ant-based
start to evaporate over time and thus, the old pheromone trail will metaheuristics namely Ant-System (AS) was introduced [24]. Con-
vanish if it is not reinforced by the other ants after certain period serving the main properties of AS, other ant-based algorithms
of time. At the end, all the ants will take the same path to the food were developed by introducing some meaningful and necessary
source, as a consequence of snowball effect. modifications in order to suit the problems on hand. The main char-
acteristic of AS is that, artificial ants choose the espousing city to be
3.1. Ant-based metaheuristics optimization visited by employing a random mechanism during the constitution
of the problem solutions. When the ant z at city-i with executable
Inspired by the ant colony foraging behaviors, many ant-based partial solution set N, the probability Pz (i, j) of the ant z to go to
metaheuristic algorithms have been developed targeting optimiza- city-j is:
tion problems, such as ACS applied in TSP [26] and symmetric and ⎧
asymmetric TSPs [25]. The entire artificial ants in these ant-based ⎪
⎪
˛
(i, j) (i, j)
ˇ
⎨  ˛ ˇ
, if e(i, j) ∈ N
metaheuristics have the same foraging behaviors as the real ants. (i, j) (i, j)
Pz (i, j) = (2)
The ant-based metaheuristic algorithms consist of three general ⎪
⎪
stages, which are the initialization, the construction and the feed- ⎩ e(i,j) ∈ N
0, otherwise
back. The initialization stage involves the parameters settings such
as the number of colonies and number of ants. Then, the artifi- where (i, j) is the pheromone intensity of the trails at the edges
cial ants will be guided by the pheromone-based probability in e(i, j), while the edges e(i, j) are the unvisited edges by the ant z.
constructing the path. Eventually, the feedback phase deals with The parameters ˛ and ˇ are employed to control the impacts of the
the extraction and the reinforcement of the ants traveling experi- pheromone (i, j) and the heuristic information (i, j) on the ant
ences obtained during the previous searching path. This update is destination selection, regarded as the global and local information
important as it will assist the optimal solution exploration of the respectively. It is recommended that these parameters are fixed to
accompanying ants. Through these robust ant-based metaheuristic be ˛ = 1 and ˇ ∈ [3, 5]. The heuristic data (i, j) is defined as:
backbone stages, ant-based metaheuristic algorithms are able to
deliver fruitful and beneficial results in many fields. The backbone 1
(i, j) = (3)
of ant-based metaheuristic algorithm is shown in Fig. 3. d(i, j)
 C.-S. Hoo et al. / Applied Soft Computing 13 (2013) 3285–3297 3289

where d(i, j) is the distance between cities i and j. Based on the prob- 4.1. VOAS’s greedy local search
ability calculated, a Roulette-based selection mechanism is adopted
to assist the ant to choose the next city-j. This section presents the greedy local search conducted by coop-
After every iteration of the path construction, the pheromone eration between VOAS and reconnaissance ants. Let the corners in
level of the trails traveled by the ant z is updated by: the CL corner list to be considered as the local search options. Dur-
ing greedy local search, a group of ant, namely reconnaissance ant

n
(RA) is employed. Let the number of visited cities (placed module)
(i, j) = (1 − ) · (i, j) + z (i, j) (4) denoted as q, the number of RA in a troop is equal to (q + 1). Each RA
z=1 in the troop will travel to all the local search options in order to get
the instant local information (whitespace/wirelength) for specific
where  is the evaporation rate, n is the total number of ants unvisited city (unplaced module). By referring to this instant local
involved, and  z (i, j) is the amount of pheromone deposited on information, VOAS will greedily choose the local search option with
the edges e(i, j) undertaken by ant z which is defined as: the lowest whitespace/wirelength to be its local information (i, j).
 The number of VOAS ants is equal to the unvisited cities.
Q/Costz , if e(i, j) ∈ path taken by ant z In Fig. 4, two types of ants, namely VOAS ants and RA, with dif-
z (i, j) = (5)
0, otherwise ferent roles in VOAS are shown. Before computing probability for
VOAS ant to travel to the next unvisited city, VOAS ants are assigned
where Q is a constant determined by the user during initialization into the city-i and each VOAS ant will dispatch a troop of RA to
stage and Costz is the length of the tour traversed by the ant z. explore and identify the shortest path to particular unvisited city.
This is because there is always more than one path to travel to
a specific unvisited city. In other words, there are always at least
4. Variable-Order Ant System two local search options, which are (the number of visited city + 1)
corners available, as stated in Property 3.1. From all the paths trav-
Inspired by the foraging behavior of ant colony, ant-based meta- eled by RA, VOAS ant will select the shortest path to represent the
heuristics approaches [19,24–28] are well-known to be a powerful local information in (3). This concurrently shared experience dis-
searching method, which can deliver fruitful and promising out- courages VOAS ants from traveling through suboptimal paths and
comes. Based on the report by Shtovba [32], there are a couple of speed up the runtime to reach the near-optimal solution. As an
weaknesses in AS algorithm discussed: analogous floorplan example by considering the instant floorplan
layout shown in Fig. 2(c), the visited cities are the modules m1 , m2 ,
and m3 while the modules m4 and m5 remain as unvisited cities.
(a) The best solutions might disappear due to the probabilistic rule
By referring to this example where the objective of the floorplan-
used in the routing selection.
ning is set to minimize area, a greedy local search to determine the
(b) The convergence of the solutions closed to the optimum is low
instant local information for these two unvisited cities is shown in
as the contributions of the best and worst solutions almost the
Fig. 5. The respective local information (i, j) in choosing the cities
same. This is because the pheromone levels are approximately
m4 and m5 , are equal to the lowest whitespace found by the RAs.
the same, which means that pheromone values have insignifi-
The instant whitespace found in these two cities may be different
cant influence on the ant route choice.
as different groups of RA are employed. Assuming RA2 of unvisited
city m4 locates the lowest instant whitespace, then, VOAS ant will
In order to tackle these critical constraints, other ant-based place m4 onto the corner [mleft , m1 ] in the event m4 is chosen dur-
algorithms are developed by modifying the pheromone update ing the Roulette-based selection, as shown in Fig. 2(d). As discussed
mechanism and route selection rules, while retaining the anchor in Section 2.2, RA2 represents the corner [mleft , m1 ] instead of [m3 ,
of AS algorithm. m1 ]. The relationship between local search options and the number
In this paper, we introduce a new ant-based meta-heuristics,
called as Variable-Order Ant System (VOAS) for VLSI floorplan-
ning problems. Without altering the main properties of AS, VOAS
is implanted with a higher ability in the prioritization of global and
local searches. VOAS imposes a high dependency on the previous
food foraging experience at the initial stage of the path construction
while gradually switching to the local search preference toward the
end of the path. This enables VOAS to accommodate some degree
of randomness on the selection of the modules yet offering con-
vergence to the best possible solution. The basic concept of VOAS
is that the ants’ behavior pattern is affected by the relative vari-
able orders of the parameters ˛ and ˇ. Basically, the behaviors of
the ants grouped into two types, where the first type tends to for-
age food based on previous experience and be more adventurous
in seeking different possible optimal solutions while the second
type is more prudential and tends to complete the path construc-
tion to near perfection. On top of that, there is another group of
ant, namely reconnaissance ant, that is dispatched to search instant
local information greedily, which will be discussed in detail in Sec-
tion 4.1. Penalty will be imposed if a bad path is chosen. These
are the major property of VOAS which is different from the other
ant-based metaheuristics approaches, where they do not have the
different tendency on the path selection or different groups of ants
with different functionalities and the introduction of penalty. Fig. 4. Operations of VOAS and reconnaissance ants.
 3290 C.-S. Hoo et al. / Applied Soft Computing 13 (2013) 3285–3297

where (xi , yi ), (xj , yj ) and (X, Y) are the coordinate of the center
points of modules mi , mj , and floorplan layout respectively, and
average is the average value of wirelength . The parameter ı in iii
imposes the normalized weights of both objectives. The constraints
of iv and v are incorporated to avoid the modules overlapping. The
parameter ˛ in VOAS is set to be:

0, p=1
˛= (7)
1, 2≤p≤n

Fig. 5. Four RAs of particular city in VOAS searching the best instant local informa- where p indicates the pth module that is to be selected and n is the
tion greedily in floorplan with number of visited cities = 3.
number of modules in the floorplanning problem. By referring to
the notations in (7), the parameter ˇ is set to be:
of unvisited cities are discussed in Property 5.1 whereas the com- 
0, p=1
putational complexity of VOAS greedy local search is bounded by ˇ= (8)
5p
O(n2 ), as proven in Theorem 5.1. , 2≤p≤n
n
Property 5.1. The number of local search options and the number of The parameter ˛ is set to be zero or unity based on Dorigo [33]
unvisited cities are related linearly. and Dorigo et al. [25]. Their works have suggested that for a value
˛ more than unity leads to a rapid growth of pheromone where all
Proof. Let the total numbers of cities and the number of unvisited
ants will follow the same path and construct the same tour, and
cities be denoted as n and u respectively, resulting into a local search
hence, a suboptimal solution is generated. The parameters ˛ and
equal to (the number of visited cities + 1), which is (n − u + 1).
ˇ are set to be zero in (7) and (8) while choosing the first module
Theorem 5.1. The computational complexity of VOAS’s greedy local in order to prevent the same module to be repeatedly selected in
search is bounded by O(n2 ). new path selection as this may also lead to suboptimal solution. The
repeated selection will increase the pheromone level of a particular
Proof. In reference to the notations in Property 5.1, the computa- module and results in the permutation of first module to be limited.
tional cost for instant floorplan is the product of unvisited city and Inline to this, the first module is selected randomly to obtain more
number of local search options, which is (u)(n − u + 1). By carry- possible solutions, which might lead to better global optimal solu-
ing out the first and second order differentiations, we can find the tions, as the probability of an ant to visit more unexplored vertices
maximum value of the computational cost when u = (n + 1)/2. By is increased.
substituting u, the computational cost will be [(n + 1)/2]2 = O(n2 ). The order of parameter ˇ is varied in VOAS, as local informa-
tion gets more priority during the finalization of the floorplanning.
4.2. Variable order property of VOAS Based on the experimental studies carried out in AS [24], Elitist Ant
System (EAS) [33], ACS [26] and MAX-MIN Ant System (MMAS)
Though VOAS is similar to other ant-based metaheuristic algo- [34], the value of ˇ is suggested to be a constant ranging from two
rithms, VOAS is unique in selection operation. In other ant-based to five. As the parameter ˇ can be an arbitrary constant, the maxi-
metaheuristics, the probability-based selection on the unvisited mum value of ˇ in VOAS is set to be five so that the impact of local
city depends on the global and local information with constant information will be more significant when more cities have been
indexes of exponentiation. Even though these two indexes of expo- visited. The value of d(i, j) in (3) is defined in (6), which highly relies
nentiation are experimentally proven to be perfectly matched in on the objective(s) of the floorplan. Subsequently, the probability
NP-hard problem, it falls short in dealing with VLSI area driven calculated in (2) is employed in Roulette wheel mechanism to select
floorplanning, which is a two dimensional problem. the next city-j.
By retaining the main properties of AS, ants in VOAS will be
significantly affected by the pheromone (global search) at the 4.3. Pheromone updates rules of VOAS
beginning of every search as compared to instant information (local
search). This effect is reduced subsequently in every step after As discussed in Section 4, Shtovba [32] has reported that the
the placement of the first module. Since the number of VOAS ant pheromone level of the best and worst path in AS algorithm are
involved is equal to the number of unvisited cities, indicating that approximately the same which is not adequate to assist the ant to
the lesser the ants involved in the path construction, the greater select the best path accurately. Hence, a pheromone update rules
the impact of local search as compared to global search. with the bad solution penalty is adapted in VOAS. After a complete
In VOAS, ant z at city-i will choose the next unvisited city-j based route is generated, the pheromone values of the trail traversed by
on the probability relation in (2) and (3). However, the local infor- ant are updated by using (9).
mation, (i, j) is defined as 1/d(i, j), where d(i, j) is the cost function 
(6) found by the RA for city-j. In VOAS, optimized cost metric (6) is (1 − )(i, j) +  · z (i, j), if (i, j) ≤ Xdesired
defined as:  (i, j) = (9)
(1 − )(i, j) −  · z (i, j), if (i, j) > Xdesired
Minimize : D = ı · Darea + (1 − d) · Dwirelength (6)
where  is the evaporation rate such that 0 <  < 1 in order to avoid
Subject to: unconstrained accretion of the pheromone. Meanwhile, Xdesired is a
constant which corresponds to the desired relative whitespace of
n the floorplanning.  z (i, j) is the amount of pheromone deposited
(H×W )− ai
i. Darea = H×W
i=1
× 100% on the edges e(i, j) traveled by ant z which is defined as:
ii. Dwirelength = (( / average ) − 1) × 100% ⎧
iii. 0≤ı≤1 ⎨ 100 , if e(i, j) ∈ path taken by ant z
z (i, j) = Costz (10)
iv. (xi − xj ) − (wi + wj )/2 < 0 ∀i, j; 1 ≤ i, j ≤ n, and i =/ j
⎩ 0,
v. (yi − yj ) − (hi + hj )/2 < 0 ∀i, j; 1 ≤ i, j ≤ n, and i =
/ j otherwise
 C.-S. Hoo et al. / Applied Soft Computing 13 (2013) 3285–3297 3291

where Costz is the total final floorplan whitespace. all the experimental simulations by using MCNC and GSRC bench-
To minimize bad solutions, outputs with a floorplan whitespace mark circuits, the VOAS’s parameters used are specified in Sections
larger than Xdesired are penalized as per (9) and thus, VOAS con- 4.2 and 4.3.
verges to the possible best solution in a short time. In update rule The comparisons are made on the following state-of-the-art and
(11), the pheromone of the ant is restricted to be at least unity, as recent floorplanning/placement algorithms: O-Tree [11], Enh. O-
described: Tree [12], B*-Tree [10], TCG [6], TCG-S [5], CBL [4], FAST-SP [7],
⎧ n Enh. Q-Seq. [8], TBS [13], Moving Block Sequence-Organizational
⎪
⎪ 1− z (i, j)
Evolutionary Algorithm (MBS-OEA) [16], Multi-agent Evolution-
⎨  (i, j), if (i, j) ≥ z=1
1− ary Algorithm-Moving Block Sequence (MAEA-MBS) [15], Adjacent
 (i, j) = n (11)
⎪
⎪ 1− z (i, j) Constraint Graph (ACG) [9], Evolutionary Search (ES) [36], Block-
⎩ 1, if (i, j) < z=1
packing with Branch-and-Bound (BloBB) [37], Parquet [21,37],
1−
Elitist Non-Dominated Sorting based Genetic Algorithm Floorplan-
This is because mathematically, a positive base number which ner (ENDSGA) [38], Discrete Particle Swarm Optimization (DPSO)
is less than unity with power more than unity, will generate an [39], Evolutionary Simulated Annealing (ESA) [40], Hybrid Algo-
outcome less than the base number, i.e. 0.93 = 0.729 (<0.9) and rithm (HA) [41], Greedy Insertion Technique (GIT) [42], Improved
0.95 = 0.59 (<0.93 ). This will generate a misleading probability com- Simulated Spheroidizing Annealing Algorithm (ISSAA) [43], and
putation in (2). The value of  is selected to be 0.02 as suggested Hybrid Simulated Annealing (HSA) [18]. The near-optimal solu-
in MMAS [34] whereas Xdesired is 1% of relative whitespace. The tions of these floorplanning algorithms are extracted directly from
pheromone evaporation rate  is set to a low value as this will respective published reports. For each benchmark problems, cost
increase the number of tours explored during the initial search. function (6) is employed to evaluate the quality of the floorplan lay-
A high pheromone evaporation rate will cause the pheromone out solutions generated by VOAS every iteration, where the number
trails of optimal solution diminish in the early stage resulting in of iteration for each benchmark circuitry is set to be 300. The
a suboptimal solution. The value of Xdesired is selected with the whitespace of a floorplan layout is obtained by calculating the dif-
goal of relaxing the tolerance. A tight tolerance of zero whites- ference between the minimum area of the rectangle which covers
pace will cause the VOAS to be trapped into local optima where all the modules and the sum of all the modules’ areas. Meanwhile,
many pheromone trails disappear before reaching optimal solution relative whitespace is defined as the ratio of whitespace to the
as they are always subjected to a pheromone reduction penalty. minimum area of the rectangle which encapsulates all the mod-
In VLSI floorplanning, VOAS not only selects the module but ules. To provide a relative comparison, normalization of results is
also places the modules onto the appropriate corner. Hence, VOAS used to calibrate and compare VOAS results with other benchmark
floorplanner does not only search for possible optimal solutions algorithms in terms of area and wirelength. For any benchmark
(minimum wirelength/area) but also completes the floorplanning cases, the normalization is a ratio of ‘the results of other floorplan-
in a compact manner (area minimization). ning/placement algorithms’ to the results of VOAS algorithm. For
the convenience of reference, some abbreviations are defined as
5. Empirical validations and discussions below:
RW Relative whitespace (%)
VOAS was compiled using GNU GCC compiler on a Linux Ubuntu nRW Normalized relative whitespace
Wirelength
OS-based PC platform with Intel Pentium IV 2.4 GHz CPU and 256- n Normalized wirelength
MB memory and tested under the commonly used Microelectronics RT Runtime (s)
Center of North Carolina (MCNC) and Gigascale Systems Research nRT Normalized runtime
Center (GSRC) [35] benchmark circuits. The details of MCNC and
GSRC benchmark circuits are shown in Table 2. In line with the 5.1. Comparisons of VOAS and AS
accentuation on the significance on the number of independent
runs by Chan et al. [31], VOAS is executed 50 times independently By employing AS with the parameters of ˛ = 1, ˇ = 3, and  = 0.02,
for each benchmark circuitry to obtain the near-optimal solution. In comparisons are made with VOAS, as shown in Table 3. In order

Table 2
Floorplanning problems (MCNC and GSRC benchmarks).

Problems Benchmark type # Modules # Nets # Terminals # Pins Areas of all modules (mm2 )

apte MCNC 9 97 73 287 46.5616

xerox MCNC 10 203 2 698 19.3503
hp MCNC 11 83 45 309 8.8306
ami33 MCNC 33 123 42 522 1.1564
ami49 MCNC 49 408 22 953 35.4454
n10a GSRC 10 118 69 248 22.1679
n10b GSRC 10 133 86 274 22.1177
n10c GSRC 10 119 68 246 22.8770
n30a GSRC 30 349 212 723 20.8591
n30b GSRC 30 350 227 725 19.7781
n30c GSRC 30 390 271 818 22.2522
n50a GSRC 50 485 209 1050 19.8579
n50b GSRC 50 511 269 1105 20.3053
n50c GSRC 50 515 243 1097 20.1512
n100a GSRC 100 885 334 1873 17.9501
n100b GSRC 100 806 374 1797 16.0126
n100c GSRC 100 855 323 1830 17.1966
n200a GSRC 200 1585 564 3599 17.5696
n200b GSRC 200 1714 624 3640 17.4593
n200c GSRC 200 1532 533 3513 17.0129
n300 GSRC 300 1893 569 4358 27.3170
3292 C.-S. Hoo et al. / Applied Soft Computing 13 (2013) 3285–3297

2.3

0.98
1.33

0.98

1.13
1.22

1.18
1.35
1.11
1.06

1.05
1.06
1.10

1.03

1.07
1.05
n 2.1 AS

1
1
1

1
1
1
1.9 VOAS
nRW

1.44
0.87

1.46

1.17
1.19
1.12
1.32

1.16
1.19

1.17
1.02
1.08

1.03

1.09

1.06
1.7

nRW
1
1
1

1
1
1
AS
1.5
2.15
3.41

2.56
2.01

2.10

2.04
VOAS
RT (s)

139
159

120
117
112
177
146
170
264
261
273
512
538
526
6190
1.3
1.1
0.9
Cost metric

0 100 200 300 400

Number of modules
0.26
1.93
2.95
2.57
1.95
1.28

2.14
5.17
1.85

3.29
3.87
5.49
4.45
4.52
4.32

4.71
3.78
1.09
1.30

3.03

5.30
(6)

Fig. 6. Normalized relative whitespaces of AS and VOAS in area optimization floor-

planning.
(mm)

59.48

40.48

39.58
95.46
43.20
245.9
379.6
149.8

103.8
125.4
181.1
190.8
173.1
212.9
243.1
222.8
438.1
419.6
413.3
606.3
667.0

to investigate the capability of AS and VOAS in handling area opti-

mization and multiobjective floorplanning, the parameter ı is set to
be unity and half respectively. In area minimization floorplanning,
(mm2 )
VOAS

9.46
1.22

it is evident that VOAS’s optimization results are always compa-

Area

47.1
20.3

37.8

22.9
23.7
22.1
22.8
23.4
21.5
22.2
22.4
20.8

19.4
19.7
20.1
19.3
30.7
23.0

18.0

rable with AS when the number of modules in the benchmark

problems is maximally ten. But, when the number of modules is
1.78
2.36
3.35

2.17

2.44
2.60
RT (s)

more than ten, the near-optimal area of VOAS shows better result.
123
167

113
109
120
172
158
163
256
269
260
503
511
520
6056

Fig. 6 shows that the normalized area of AS is increasing linearly

with respect to VOAS when the number of module increases. This
indicates the better scalability of VOAS in handling floorplanning
Cost metric

with optimized area as compared to AS. This is because VOAS can

complete the floorplan layout with a better choice of placement
0.27
1.94

1.91
1.42
1.24
1.36

5.27

3.53
3.88
4.31
7.14
4.47
5.22
5.13
5.77
5.46
3.99
3.01
3.70

3.10

2.00
(6)

and thus, reducing the near-optimal areas. In reference to Table 3,

it is to be highlighted that VOAS shows better or same results in
(mm)

terms of cost metric (6) in all the benchmark cases as compared

58.37

40.48

39.58
43.20
245.9
379.6
149.8

888.7

100.9
101.6
131.9
192.7
210.2
196.3
259.1
249.7
263.1
589.3
463.8
440.7
637.4

to AS. The runtime results of VOAS and AS in obtaining respec-

tive near-optimal solutions are comparable as they are employing
the same floorplan representation and similar ant-based algorithm
(mm2 )

complexity.
ı = 0.5

9.46
1.25
Area

47.1
20.3

37.5

22.9
23.7
22.7
22.9
23.5
21.8
22.6
22.7

19.8
20.2
20.4
19.7
30.9
23.0

22.0
18.0

Referring to the multiobjective floorplanning results, it is

AS

observed that VOAS shows better and equal results in terms of

area and wirelength in 12 and 6 cases respectively, out of in total
nRW

1.53
1.41
2.12

1.29
1.31

2.19
1.54
1.67
1.49
1.56
1.52
1.34

1.41
1.46
1.30

21 benchmark circuits as compared to AS. Compared to AS, VOAS

1
1

1
1
1

shows 85.7% of better and equal results in solving multiobjective

1.18

1.75
1.89
1.99
1.01
1.04

80.5

75.8
77.6
71.3

83.6
87.0

floorplanning problem. It is to be noted that VOAS generates same

RT (s)

102

114

179
170
189
430
478
488
6018

near-optimal area and wirelength results when the number of mod-

ules is less than 12 and while VOAS’s near-optimal results are
always better than AS in optimizing both objectives when the num-
Cost metric

ber of modules is more than 49. By referring to Table 3, it is observed

that VOAS shows 95.2% better cost metric (6) as compared to AS.
0.76
2.27

2.19

1.96
2.15
3.34
1.41

2.42
2.89
2.75
4.87
4.91
4.73
6.49
6.88
7.53
7.31
1.30

3.07

2.40
2.00
(6)

Similar to the area optimization floorplanning, the runtime results

of VOAS and AS are comparable.
Fig. 7 shows the results of the proposed VOAS and AS in mul-
(mm2 )
VOAS

8.95
1.18
Area

tiobjective floorplanning problems by using the MCNC and GSRC

46.9
19.8

36.2
22.9
22.6
23.4
21.6
20.1
22.8
20.4
20.9
20.7
18.9
16.8
18.1
18.8
18.8
18.4
29.5

benchmark circuits. From the trendlines in Fig. 7, VOAS’s and AS’s

1.75
1.96
1.06
1.08
1.06

2.04
98.2

69.1
79.5

98.8
83.6
78.0
RT (s)

125

102

184
162
188
418
452
468
5956

1.35 nψ (AS)
1.3 nRW (AS)
nψ (VOAS)
Normalized data

1.25
Cost metric

1.2 nRW (VOAS)

nψ (AS)
0.76
2.27
1.99
2.82
4.67

1.96
2.15
4.31
1.85

4.45
4.59
7.28
7.66

8.73
8.92
3.08

2.40
5.30

7.20

1.15
10.6
10.7
(6)

nRW (AS)
1.1
VOAS and AS comparisons.

nψ (VOAS)
1.05 nRW (VOAS)
(mm2 )

1
9.01
1.20
Area

46.9
19.8

37.2
22.9
22.6
23.4
21.8
20.2
22.8

21.3
21.1
19.4
17.3
18.5
19.3
19.2

30.6
21.0

19.0
ı=1

AS

0.95
0 200 400
Number of modules
Circuits

n100b

n200b
n100a

n200a
ami33
ami49

n100c

n200c
Table 3

xerox

n300
n10b

n30b

n50b
n10a

n30a

n50a
n10c

n30c

n50c
apte

hp

Fig. 7. Normalized relative whitespaces and wirelengths of AS and VOAS in multi-

objective floorplanning.
 C.-S. Hoo et al. / Applied Soft Computing 13 (2013) 3285–3297 3293

Table 4
Comparisons using MCNC floorplanning benchmark circuits.

Algorithms apte xerox hp ami33 ami49

Area nRW Area nRW Area nRW Area nRW Area nRW

O-Tree 47.1 1.50 20.1 1.64 9.21 3.16 1.25 3.74 37.6 2.61
Enh. O-Tree 46.92 1 20.21 1.87 9.16 2.75 1.25 3.74 37.73 2.76
B*-Tree 46.92 1 19.83 1.07 8.947 1 1.27 4.47 36.80 1.68
TCG 46.92 1 19.83 1.07 8.947 1 1.20 1.82 36.77 1.64
TCG-S 46.92 1 19.80 1 8.947 1 1.185 1.21 36.40 1.20
FAST-SP 46.92 1 19.80 1 8.947 1 1.21 2.02 36.50 1.32
Enh. Q-Seq. 46.92 1 19.93 1.28 9.03 1.69 1.19 1.57 36.75 1.62
ACG 47.08 1.44 20.16 1.77 9.33 4.40 1.20 1.82 36.92 1.82
CS 46.92 1 19.83 1.07 8.947 1 1.18 1 36.28 1.05
CBL – – 20.96 3.38 – – 1.20 1.82 38.58 3.71
BloBB 47.30 2.04 20.31 2.08 9.26 3.55 1.25 3.74 38.18 3.27
Parquet 51.81 13.3 22.09 5.46 9.59 6.06 1.25 3.74 38.89 4.04
MAEA-MBS 46.92 1 19.83 1.07 8.947 1 1.19 1.41 36.75 1.62
ES 46.92 1 20.26 1.98 9.15 2.67 1.19 1.41 36.30 1.07
MBS-OEA 46.92 1 19.80 1 8.947 1 1.175 0.79 36.35 1.14
ENDSGA – – – – – – 1.20 1.82 37.81 2.85
DPSO 47.31 2.07 20.20 1.85 9.50 5.39 1.28 4.83 38.80 3.94
HA 46.92 1 20.10 1.64 9.17 2.85 1.21 2.41 37.28 2.24
ESA 47.37 2.23 19.83 1.07 8.937 0.92 1.24 3.37 36.50 1.32
GIT 50.02 9.05 20.80 3.07 9.33 4.10 1.28 4.83 36.88 1.77
HSA 46.90 0.94 20.01 1.45 9.01 1.53 1.20 1.82 36.48 1.29
VOAS 46.92 1 19.80 1 8.947 1 1.18 1 36.24 1

normalized results for problems with larger number of modules can more than hundreds of modules. Therefore, further experiments
be predicted in advance as the relative whitespaces fairly remain are conducted by using GSRC circuits.
constant throughout. It is observed that both the normalized rela- Table 5 compares the GSRC benchmark results of VOAS with
tive whitespace and wirelengths of AS tend to saturate at a higher MAEA-MBS, MBS-OEA, ES, GIT, BloBB, Parquet, and DPSO. In
normalized value than VOAS’s. Both the area optimization and overall, VOAS shows improved results as compared to other floor-
multiobjective floorplanning result comparisons indicate that the planning/placement algorithms in terms of area minimization
proposed variable-order property and the modified update rules particularly for benchmark problems more than 30 modules. From
enable VOAS to handle VLSI floorplanning better than AS. It is also to Table 5, it is evident that VOAS results are better than 84% of the
be highlighted later that the VOAS’s results have an edge over other results obtained by other floorplanning algorithms. Through the
state-of-the-art and recent floorplanning/placement algorithms, in experimental comparisons based on GSRC benchmark circuits, it
terms of area and multiobjective optimization. is proven that VOAS has not only performed better in terms of
area, but also in terms of scalability and stability than the other
floorplanning algorithms.
5.2. Area optimization floorplanning (ı = 1)
The comparisons of VOAS with other floorplanning algorithms
for different benchmark circuits are illustrated in Fig. 8 and the
Table 4 compares the MCNC benchmark circuit results of VOAS
floorplanning algorithms’ results are considered successful if they
with O-Tree, Enh. O-Tree, B*-Tree, TCG, TCG-S, FAST-SP, Enh. Q-
are better, comparable if they are equal and unsuccessful if they are
Seq., ACG, CS, CBL, BloBB, Parquet, MAEA-MBS, ES, DPSO, MBS-OEA,
inferior. From Fig. 8, it is observed that for problems with more
ENDSGA, HA, ESA, GIT, and HSA. The normalized relative whites-
than 33 modules, the near-optimal results of VOAS give significant
paces results of all the floorplanning/placement algorithms with
improvements over the other algorithms. In reference to the defi-
respect to VOAS are shown as well. By defining test case as the
nitions of successful, unsuccessful and comparable discussed above,
result of a floorplanning algorithm in a benchmark circuit, it is
the comparisons of all the floorplanning algorithms with others
observed that in Table 4, VOAS shows improved results in terms of
by using MCNC and GSRC benchmark circuits are carried out and
area in 75 test cases and equal results in 22 test cases, out of in total
detailed distinctions amongst these various algorithms are brought
100 test cases when compared to other floorplanning/placement
out in Fig. 9. From Fig. 9, it is evident that VOAS shows the highest
algorithms. VOAS performs well over 75% and equal in 22% of
percentage of successful results and the lowest percentage of unsuc-
other algorithms in terms of whitespace. In other words, VOAS has
cessful results among all the floorplanning algorithms, which are
achieved 97% of improved or at least equal test case results as com-
pared with other algorithms. By referring to the bolded best area
results for different benchmark cases in Table 4, VOAS has an edge 100
over all the other floorplanning/placement algorithms in the largest 80 Successful cases
Percentage (%)

MCNC benchmark circuit, namely ami49. From the results of HSA, (better)
ESA and MBS-OEA, it is obvious that each one of these algorithms 60
Comparable cases
shows the best result in only one of the benchmark circuits. As com- (equal)
40
pared to HSA and ESA, VOAS shows better outcome in four of the Unsuccessful
remaining benchmark circuits. Even though VOAS results are the 20 cases (bad)
same in three smallest benchmark circuits (maximally 11 modules
only) and inferior in ami33 benchmark circuit as compared to MBS- 0
9 10 11 30 33 49 50 100 200 300
OEA, VOAS has a better result in the largest scale MCNC benchmark
Number of modules
circuit. On top of that, limited number of modules (up to 49 mod-
ules only) in all MCNC benchmark circuits cannot wholly deal with Fig. 8. Percentages of successful, comparable and unsuccessful benchmark circuit
the modern VLSI floorplanning problems on hand with typically cases of VOAS.
3294 C.-S. Hoo et al. / Applied Soft Computing 13 (2013) 3285–3297

Table 5
Comparisons using GSRC floorplanning benchmark circuits.

Benchmark circuits MAEA-MBS MBS-OEA ES GIT DPSO BloBB Parquet VOAS

Area nRW Area nRW Area nRW Area nRW Area nRW Area nRW Area nRW Area nRW
(mm2 ) (mm2 ) (mm2 ) (mm2 ) (mm2 ) (mm2 ) (mm2 ) (mm2 )

n10a 22.77 0.86 22.61 0.63 – – – – – – – – – – 22.87 1

n10b 22.56 1 22.56 1 – – – – – – – – – – 22.56 1
n10c 23.18 0.60 23.18 0.60 – – – – – – – – – – 23.38 1
n30a 21.91 1.46 21.46 0.83 – – – – 23.4 3.52 – – – – 21.58 1
n30b 20.43 2.31 20.12 1.21 – – – – – – – – – – 20.06 1
n30c 23.51 2.30 22.82 1.04 – – – – – – – – – – 22.80 1
n50a 20.59 1.49 20.41 1.12 – – – – 22.2 4.76 – – – – 20.35 1
n50b 21.32 1.68 20.93 1.03 – – – – – – – – – – 20.91 1
n50c 20.99 1.47 20.76 1.07 – – – – – – – – – – 20.72 1
n100a 19.40 1.58 18.98 1.12 18.96 1.10 19.45 1.64 – – 19.22 1.38 20.03 2.26 18.87 1
n100b 17.05 1.25 16.98 1.17 – – – – – – 17.53 1.83 17.89 2.27 16.84 1
n100c 18.28 1.27 18.27 1.26 – – – – – – – – – – 18.05 1
n200a – – 19.24 1.37 18.84 1.04 18.90 1.09 – – 19.10 1.25 19.78 1.81 18.79 1
n200b – – 19.06 1.24 – – – – – – 18.78 1.02 19.79 1.81 18.75 1
n200c – – 18.76 1.26 – – – – – – – – – – 18.40 1
n300 – – 30.24 1.36 – – 29.53 1.03 – – 29.70 1.11 31.02 1.72 29.47 1

100 Unsuccessful cases (bad)

90 Comparable cases (equal)

Successful cases (better)
80

70
Percentages (%)

60

50

40

30

20

10

Floorplanning/placement algorithms

Fig. 9. Percentages of successful, comparable and unsuccessful benchmark circuit cases of different floorplanning/placement algorithms.

77.93% and 5.52% respectively. From Figs. 8 and 9, the robustness, GSRC floorplanning benchmark circuits, namely ami49 and n300,
scalability, and reliability of VOAS are validated. by using VOAS.
Even though all the floorplanning algorithms are tested in dif-
ferent PCs with different architecture and operating frequency, the 5.3. Multiobjective floorplanning (ı = 0.5)
recent works with runtime report (from 2007 onwards) which are
implemented in C/C++ are simulated on the PCs with single-cored In multiobjective floorplanning optimization, the linear com-
CPU speed ranging from 2.0 GHz to 3.0 GHz, and 1GB RAM memory bination is the most commonly used method, which refers to the
(except HSA with 512MB RAM memory). VOAS’s runtime results cost metric (6) in this case. Jagannathan et al. [44] have revealed the
are compared to the recent algorithms, namely MBS-OEA, MAEA-
MBS, HA and HSA, by simulating VOAS on a slower PC to carry out to
indicate the improved performance of VOAS in terms of runtimes. 100
Table 6 shows the runtimes of VOAS and the recent floorplanning Better
80 runtimes
algorithms in solving the MCNC and GSRC benchmark circuits. It
Percentage (%)

is observed that VOAS shows 82%, 57%, 80% and 100% of better 60 Same
runtime results as compared to MAEA-MBS, MBS-OEA, HA, and runtimes
HSA respectively. Fig. 10 shows the percentages of better, same 40
and worse runtime results of VOAS as compared to these floor- 20 Worse
planning algorithms. It is to be noted that VOAS always performs runtimes
better as compared to these algorithms when the number of mod- 0
ules is equal or more than 49, which again, proves the scalability of 9 10 11 30 33 49 50 100 200 300
Number of modules
VOAS in handling VLSI area optimization floorplanning problems.
Fig. 11 shows the best floorplan layout result of largest MCNC and Fig. 10. Percentages of better, same and worse runtimes of VOAS.
 C.-S. Hoo et al. / Applied Soft Computing 13 (2013) 3285–3297 3295

Table 6
Runtime comparisons using MCNC and GSRC floorplanning benchmark circuits.

Circuits MAEA-MBS MBS-OEA HA HSA VOAS

RT (s) nRT RT (s) nRT RT (s) nRT RT (s) nRT RT (s) nRT

apte 1.45 1.435 0.5 0.495 2.093 2.072 1271.9 1259 1.01 1
xerox 2.86 2.750 1.1 1.058 1.047 1.007 738.9 710.5 1.04 1
hp 3.02 2.559 1 0.847 0.437 0.370 240.1 203.5 1.18 1
ami33 81.20 1.009 45 0.559 95.187 1.182 117.5 1.460 80.5 1
ami49 286.8 2.811 173.2 1.698 115.438 1.132 1907.0 18.70 102 1
n10a 2.739 1.565 0.9 0.514 – – – – 1.75 1
n10b 2.951 1.561 1.2 0.635 – – – – 1.89 1
n10c 3.029 1.522 1.1 0.553 – – – – 1.99 1
n30a 59.00 0.778 25.6 0.338 – – – – 75.8 1
n30b 60.00 0.773 29.4 0.379 – – – – 77.6 1
n30c 52.51 0.736 25.5 0.358 – – – – 71.3 1
n50a 338.3 2.968 132.2 1.159 – – – – 114 1
n50b 271.9 3.125 121.0 1.391 – – – – 87.0 1
n50c 290.4 3.474 137.0 1.639 – – – – 83.6 1
n100a 2153 12.03 1706.1 9.531 – – – – 179 1
n100b 2469 14.52 1065.4 6.267 – – – – 170 1
n100c 2570 13.60 1319.0 6.979 – – – – 189 1
n200a – – 12,114 28.17 – – – – 430 1
n200b – – 14,217 29.74 – – – – 478 1
n200c – – 11,211 22.97 – – – – 488 1
n300 – – 80,984 13.46 – – – – 6018 1

Fig. 11. Best layouts of VOAS in benchmark circuits: (a) ami49 and (b) n300.

relationship of the linear combination with Pareto Curve where the floorplanning/placement algorithms. It can be seen in Table 7 that
points on the lower convex hull can only be found by using the suit- VOAS shows improved results in terms of area only in 18 out of 25
able coefficients. Hence, for fair comparison, VOAS’s parameter ı is test cases, and in terms of wirelength only in 21 out of 25 test cases,
set to 0.5 to ensure equal weightage is assigned to both area and as compared to other algorithms. Meanwhile, VOAS shows better
wirelength optimizations in multiobjective floorplanning, where composite objectives of area and wirelength results in 14 out of 25
this common setting is also employed by ISSAA, ES, DPSO, ESA, and test cases. These marked improvements by VOAS are very evident
HSA. The comparison of the multiobjective floorplanning results of as can be seen from Table 8, VOAS performs well over 72%, 84%
these algorithms is shown in Table 7. Table 8 shows the normalized and 56% compared to other floorplanning/placement algorithms
relative whitespaces and wirelengths of VOAS along with the other in terms of area, wirelength as well as both area and wirelength

Table 7
Multiobjective optimization results using MCNC floorplanning benchmark circuits.

Benchmark ES DPSO ESA HSA ISSAA VOAS

circuits

Area (mm) Area (mm) Area (mm) Area (mm) Area (mm) Area (mm)
(mm2 ) (mm2 ) (mm2 ) (mm2 ) (mm2 ) (mm2 )

apte 47.57 631.13 47.31 263 49.38 205.54 47.12 480.0 48.47 408.64 47.05 246
xerox 21.01 488.03 20.2 477 20.54 621.05 20.89 513 20.42 387.64 20.34 379.6
hp 9.85 204.66 9.5 136 9.36 510.24 9.47 144.3 9.40 153.05 9.46 149.8
ami33 1.40 71.56 1.28 69 1.25 108.53 1.21 61.2 1.26 49.28 1.22 59.5
ami49 38.38 1049.36 38.8 880 36.73 1371.36 37.80 1020.3 37.76 824.49 37.82 667
3296 C.-S. Hoo et al. / Applied Soft Computing 13 (2013) 3285–3297

Table 8
Normalized results comparisons using MCNC floorplanning benchmark circuits.

ES DPSO ESA HSA ISSAA VOAS

nRW n nRW n nRW n nRW n nRW n nRW n

apte 2.04 2.57 1.52 1.07 5.50 0.84 1.14 1.95 3.79 1.66 1 1
xerox 1.62 1.29 0.84 1.26 1.19 1.64 1.51 1.35 1.08 1.02 1 1
hp 1.56 1.37 1.06 0.91 0.85 3.41 1.01 0.96 0.91 1.02 1 1
ami33 3.34 1.20 1.85 1.16 1.44 1.82 0.85 1.03 1.58 0.83 1 1
ami49 1.22 1.57 1.38 1.32 0.56 2.06 0.99 1.53 0.98 1.24 1 1

Average 1.956 1.600 1.330 1.144 1.908 1.954 1.004 1.364 1.668 1.154 1 1

70
60 Unsuccessful
(RW + ψ)
Percentage (%)

50
Successful
40 (RW)
30 Successful (ψ)
20
10 Successful
(RW + ψ)
0
ES ESA HSA DPSO ISSAAVOAS
Floorplanning/placement algorithms

Fig. 12. Percentage of successful (RW + ), successful (RW), successful ( ) and unsuc-
cessful (RW + ) of different algorithms.
Fig. 13. Best layouts of VOAS in benchmark circuits: (a) ami33 and (b) ami49.

respectively. From Table 8, it is to be noted that VOAS shows better

results in all the test cases in terms of area, wirelength or both. handling multiobjective floorplanning problems within a shorter
The comparisons of all the floorplanning/placement algorithms runtime. Fig. 13 shows the best floorplan layout result of the two
with others by using MCNC benchmark are carried out and detailed largest MCNC floorplanning benchmark circuits, namely ami33 and
distinctions amongst various floorplanning/placement algorithms ami49, by using VOAS.
are brought out in Fig. 12. The floorplanning/placement algorithms’
results are considered successful (RW + ) if they are better in both 6. Conclusion
area and wirelength optimization, successful (RW) if they are only
better in area optimization, successful ( ) if they are only better A new floorplanner, namely Variable-Order Ant System (VOAS)
in wirelength optimization and unsuccessful (RW + ) if they are is proposed to handle VLSI floorplanning design. VOAS transforms
inferior in both objectives’ optimization. It is evident that VOAS parameter ˇ in Ant System (AS) to a variable and these varying
shows the highest percentage of successful (RW + ) results and local and global factors enable the ant to make the best possi-
lowest percentage of unsuccessful (RW + ) results in optimizing ble choice. The collaboration between two groups of ants, namely
both objectives. It is to be noted from Table 8 that VOAS shows the VOAS and reconnaissance ants, during local information determi-
better results in terms of average normalized relative whitespace nation helps VOAS ant to determine its local information greedily.
and wirelengths amongst all the floorplanning/placement algo- The pheromone update rules in AS is modified and adapted in
rithms. In reference to the average normalized relative whitespaces VOAS. This modified pheromone update rules encourage the ants
and wirelengths in Table 8 and the observation in Fig. 12, it is to escape from being trapped in local optima. While retaining the
evident that VOAS can handle multiobjective floorplanning more same search space and time complexity as the state-of-the-art rep-
effectively compared to the recent floorplanning/placement algo- resentation, namely Corner Sequence (CS), CL has more corners to
rithms. be selected. Beyond that, CL reduces sequence dependence, where
In Table 9, VOAS’s runtime results are compared to the recent modules can be placed independent of its sequence onto the cor-
algorithms, namely HSA and ISSAA, where these algorithms are ners which are not bounded by the contour. The properties of
simulated in PCs with CPU of 2.0 GHz and 2.10 GHz respectively VOAS and CL are shown mathematically. Experimental results by
with 512MB and 1GB memory respectively. It is to be noted that using MCNC and GSRC benchmark circuits show that VOAS gives
VOAS performs better in 4 out of 5 and 5 out of 5 benchmark improved results in terms of area and composited function of area
circuits, as compared to HSA and ISSAA respectively. This signif- and wirelength, as compared to other state-of-the-art and recent
icant improvement by VOAS has shown the capability of VOAS in floorplanning/placement algorithms. The robustness of VOAS is
evident as depicted in the graphs plotted. As VOAS is developed
Table 9 to optimize the floorplan layout’s area as well as wirelength only,
Runtime comparisons using MCNC floorplanning benchmark circuits. further research on the application of VOAS in VLSI floorplanning
Circuits HSA ISSAA VOAS problem with different objectives and constraints such as power
minimization and thermal optimization is ongoing.
RT (s) nRT RT (s) nRT RT (s) nRT

apte 468.9 233.3 164.4 81.79 2.01 1

xerox 482.0 224.2 323.8 150.6 2.15 1
Acknowledgement
hp 214.3 62.84 196.5 57.62 3.41 1
ami33 59.8 0.430 197.5 1.421 139 1 The authors would like to thank Mr. Gin Xian Kok for sharing
ami49 899.0 5.654 403.4 2.537 159 1 the benchmark circuitry data.
 C.-S. Hoo et al. / Applied Soft Computing 13 (2013) 3285–3297 3297

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