Computer Organization and Architecture

(BCS – 352)
Lab Manual
Session: 2024- 2025

Department of Information Technology

BBDITM Lucknow, Uttar Pradesh
 Vision of Department of Information Technology

Vision of the department to transform the students to be skilled IT professionals,

Innovative leader, and environmentally receptive citizens.
 Mission of Department of Information Technology

M1. To develop and deliver quality academic program in emerging & innovative
field of engineering to empower the students to meet industry standards.

M2. To provide students with the, ethical and professional tools to become
productive & become continuous Learner.

M3. To inculcate professional behavior, positive attitude, and communication

skills.
Departmental PEO’s (Program Educational Objectives)

PEO.1. To develop the ability among students to understand the concept of core
Information Technology subjects that will facilitate understanding of new
technology.
PEO.2. To embed a strong foundation in the engineering fundamentals to solve,
analyze and design real time engineering products.
PEO.3. To give exposures to emerging edge technologies, adequate training and
opportunities to work as team on multidisciplinary projects with effective
communication skills and leadership qualities.
 PROGRAMME OUTCOMES (POs)

Engineering Graduates will be able to:

PO1. Engineering Knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering
problems.
PO2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
PO3. Design/development of solutions: Design solutions for complex engineering problems
and design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
PO4. Conduct investigations of complex problems: Use research-based knowledge including
design of experiments, analysis and interpretation of data, and synthesis of the information to
provide valid conclusions.
PO5. Modern Tool Usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex engineering
activities with an understanding of the limitations.
PO6. The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal, and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.
PO7. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
for sustainable development.
PO8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
PO9. Individual and Team work: Function effectively as an individual, and as a member or
leader in teams, and in multidisciplinary settings.
PO10. Communication: Communicate effectively with the engineering community and with
society at large. Be able to comprehend and write effective reports documentation. Make
effective presentations, and give and receive clear instructions.
PO11. Project management and finance: Demonstrate knowledge and understanding of
engineering and management principles and apply these to one’s own work, as a member and
leader in a team. Manage projects in multidisciplinary environments.
PO12. Life-long learning: Recognize the need for, and have the preparation and ability to
engage in independent and lifelong learning in the broadest context of technological change.
 Course Outcomes (CO’s)
Computer Organization and Architecture (BCS-352)

S.No. Course Outcome BTL

1. To Understand working of basic Logic Gates. L2,L4
2. To understand Hardwired and Micro programmed control in L2
Digital Computer System.
3. Analysis and Design of various combinational and L2,L4
Sequential Circuits.
4. To study the basic structure and operation of digital L1,L2
Computer system.
5. Implement the working of ALU in Digital Computer System. L3
Babu Banarasi Das Institute of Technology and Management, Lucknow

AKTU Syllabus for COA Lab (BCS -352)

 List of
Experiments
S.No. Name of Experiment CO BTL
1. To verify the truth table of basic Logic gates CO1 L2
2. To implement Half adder & full adder using Logic Gates CO1 L2
3. To implement Binary to Gray & Gray to Binary Decoder CO2 L2
4. To implement 3-8 Line Decoder CO2 L2
5. To implement 4x1 and 8x1 multiplexer CO2 L2
6. To verify the excitation table of various flip flops CO3 L3
7. To design an 8 Bit ALU circuit. CO3 L2
8. To implement Booth Multiplier CO3 L2
9. To implement Half Subtractor and Full Subtractor circuit. CO3 L3
10. Simple Instruction Set Computer with Control and Data CO4 L2
Path.
11. Design the data path from RTL Description CO4 L2
12. Design of Control unit using Hardwired or Micro CO5 L3
Programmed Control.
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DO’S AND DONT’S

DO’s

1. Conform to the academic discipline of the department.

2. Enter your credentials in the laboratory attendance register.
3. Read and understand how to carry out an activity thoroughly before coming to
the laboratory.
4. Ensure the uniqueness with respect to the methodology adopted for carrying out
the experiments.
5. Shut down the machine once you are done using it.

DONT’S

1. Eatables are not allowed in the laboratory.

2. Usage of mobile phones is strictly prohibited.
3. Do not open the system unit casing.
4. Do not remove anything from the computer laboratory without permission.
5. Do not touch, connect or disconnect any plug or cable without your
faculty/laboratory technician’s permission.

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GENERAL SAFETY INSTRUCTIONS

1. Know the location of the fire extinguisher and the first aid box and how to use them
in case of an emergency.

2. Report fires or accidents to your faculty /laboratory technician immediately.

3. Report any broken plugs or exposed electrical wires to your

faculty/laboratory technician immediately.

4. Do not plug in external devices without scanning them for computer viruses.

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EXPERIMENT 1

Aim: Verification of logic gates

Equipment Required & Component Required:

S.No. Equipments Specification Quantity

1 Digital IC Trainer kit - 1
2 Digital Multimeter 1

S.No. Components Specification Quantity

7400, 7402, 7404,
1 each
1 Digital ICs 7408, 7432, 7486.
- 6
2 Patch cords

Theory:
 Details of IC used and pin configurations.
 Working of logic gates.

1. OR GATE:
VCC
1413
14 13 12 11
11 10
10 99 88

11 22 33 44 55 66 77
GND
PIN CONFIGURATION OF
74LS32
TRUTH TABLE OBSERVATION TABLE
INPUT A INPUT B OUTPUT Y INPUTS OUTPUT USING USING LED
A B VOLTMETER
0 0 0
0 1 1 - - -
- - -
1 0 1
- - -
1 1 1
- - -

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2. AND GATE:
VCC
V
1413
141414 131313 11 121212 111111
12 10 9 8
101010999 888

11 22 33 44 55 66 77

PIN CONFIGURATION OF 74LS08

GND
TRUTH TABLE OBSERVATION TABLE
INPUT A INPUT B OUTPUT Y INPUTS OUTPUT USING USING
A B VOLTMETER LED
0 0 0
0 1 0 - - -
1 0 0 - - -
1 1 1 - - -
- - -

3. NOT GATE:
VCC
1413
12 11 10 9 8

1 2 3 4 5 6 7

GND
PIN CONFIGURATION OF 74LS04

TRUTH TABLE OBSERVATION TABLE

OUTPUT INPUTS OUTPUT USING USING LED
INPUT A
Y A B VOLTMETER
0 1 - - -
1 0 - - -

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4. NOR GATE

TRUTH TABLE OBSERVATION TABLE

INPUT INPUT OUTPUT INPUTS OUTPUT USING LED
A B Y USING
0 0 1 A B
VOLTMETER
0 1 0 - - -
1 0 0 - - -
1 1 0 - - -
- - -

5. NAND GATE:

PIN CONFIGURATION OF
74LS00
TRUTH ATION TABLE
USING LED
TABLE
A B
INPUT INPUT OUTPUT
A B Y
- - -
0 0 1 - - -
0 1 1 - - -
1 0 1 - - -
1 1 0
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6. EX-OR GATE:

PIN CONFIGURATION OF 7486

TRUTH TABLE OBSERVATION TABLE

INPUT INPUT OUTPUT INPUTS OUTPUT USING LED
A B Y USING
A B
0 0 0 VOLTMETER
0 1 1 - - -
1 0 1 - - -
1 1 0 - - -
- - -

Pre-Experiment Questions:-
Q.1 What are the different types of logic gates?
Q.2 Give the truth table of all the basic gates.
Q.3 Which gates are known as universal Gates? And why?
Q.4 Differentiate between NAND and AND Gate.

Procedure:
1. Identify the pin no’s of the given IC.
2. From the IC No. Find out the type of gate.
3. Check for the proper working of the gate.
4. Connect the circuit as per circuit diagram.
5. For all combination of input condition. Tabulate the output voltage by connecting a
voltmeter at the output end.
6. Verify it with truth Table.
7. Repeat the above procedure for all gates.

Result & Conclusion: All Logic Gates are verified.

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Post Experiment Questions: -

Q.1 How do you implement the gates using diodes?
Q.2 Implement the basic gates using universal gates.
Q.3 What do you understand the word IC?
Q.4 What is a chip?

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EXPERIMENT 2

Aim: Design and implementation of HALF ADDER, FULL ADDER using basic
logic gates

Equipment & Components Required:

S.No. Equipments Specification Quantity

1 Digital IC Trainer kit - 1
2 Digital Multimeter 1

S.No. Components Specification Quantity

7400, 7402,
7404,
1 each
1 Digital ICs 7408, 7432,
7486.
- 6
2 Patch cords

Theory:

a) To design and implement half adder using logic gates

HALF ADDER
OUTPUTS
INPUT A INPUT B
S C

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

CIRCUIT DIAGRAM TRUTH TABLE

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b) To design and implement full adder using logic gates

FULL ADDER

CIRCUIT DIAGRAM

TRUTH TABLE

Pre-Experiment Questions:
Q.1 Explain the truth table of half adder.
Q.2 How many Ex-or and or or gate can be used to make a half adder?

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Q.3 How do we convert half adder to full adder?

Q.4 Explain the characteristics of half adder.

Procedure:
 Identify the pins.
 Connect the circuit as per circuit diagram.
 Obtain outputs with various input combinations.
 Verify it with the Boolean function using truth table

Result & Conclusion: All logical circuits have been implemented & verified through
truth table.

Post-Experiment Question:
Q.1 What are the applications of half adder?
Q.2 What are the applications of full adder?
Q.3 Explain the advantages of half adder?
Q.4 Ellaborate the advantages of full adder over half adder.

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EXPERIMENT 3

Aim: Design and implementation of Binary to Gray, Gray to Binary Code conversions

Equipment & Components Required:

1S.No. Equipments Specification Quantity

1 Digital IC Trainer kit - 1
2 Digital Multimeter 1

S.No. Components Specification Quantity

7400, 7402,
7404,
1 each
1 Digital ICs 7408, 7432,
7486.
- 6
2 Patch cords

Theory:

a) To design and implement Binary to Gray Code conversions

Pin diagram of Binary to gray code converter using 7486 Ic(Ex-Or Gate)

INPUTS OUTPUTS
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A B C D G4 G3 G2 G1
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
Circuit Diagram of Binary to Gray Code 1 0 0 1 1 1 0 1
Converter 1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

Truth Table

b) To design and implement Binary to Gray Code conversions

Pin diagram of Gray to Binary code converter using 7486 Ic(Ex-Or Gate)

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INPUTS OUTPUTS

A B C D B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
Circuit Diagram for Gray to Binary Code 1 1 1 1 1 0 1 0
Converter 1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0T 0 0 1 1 1 1

Truth Table
Pre-Experiment Questions:
Q.1 What is a code converter?
Q.2 Differentiate between translator and code converter.
Q.3 Explain the primary usage of grey code.
Q.4 Illustrate the reasons for using grey code.

Procedure:
 Collect the components necessary to accomplish this experiment.
 Plug the IC chip into the breadboard.
 Connect the supply voltage and ground lines to the chips. PIN7 = Ground and PIN14
= +5V.
 Make connections as shown in the respective circuit diagram.
 Connect the inputs of the gate to the input switches of the LED.
 Connect the output of the gate to the output LEDs.
 Once all connections have been done, turn on the power switch of the breadboard

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 Operate the switches and fill in the truth table (Write "1" if LED is ON and "0" if L1
is OFF Apply the various combination of inputs according to the truth table and
observe the condition of Output LEDs.

Result & Conclusion: Binary to gray and gray to binary code converter has been
designed using EXOR gate and its truth table verified.

Post-Experiment Question:
Q.1 What are the advantages of code converter?
Q.2 What are the properties of gray code?
Q.3 Describe a way by which we can convert BCD to binary using hardware approach.
Q.4 List the process to generate n bit gray codes.

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EXPERIMENT 4

Aim: Design and implementation of 3-8 line DECODER, 4x1 MUX and 8x1
MULTIPLEXERS

Equipment’s & Components Required :

S.No. Equipment’s Specification Quantity

1 Digital IC Trainer kit - 1
2 Digital Multimeter 1

S.No. Components Specification Quantity

7400, 7402,
7404,
1 Digital ICs 1 each
7408, 7432,
7486.
2 Patch cords - 6

Theory:
a) 4 to 2 encoder using logic gates:

Truth Table Logic Diagram:

I3 I2 I1 I0 O1 O0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

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b) 3 to 8 decoder using logic gates:

Symbol: Truth table:

Logic Diagram of 3 to 8 decoder

c) 4 to 1 Multiplexer:
Symbol: Truth table:

Addressing Input
b a Selecte
d
0 0 A
0 1 B
1 0 C
1 1 D

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Logic Diagram:

d) 8x1 Multiplexer

Pin diagram of 8:1 Mux using two 4:1 Mux

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Circuit of 8:1 Mux using dual 4:1 Mux

Truth Table of 8:1 Mux Using Dual 4:1 Mux

Select Lines Inputs Output

Ea S0 S1 Io I1 I2 I3 I4 I5 I6 I7 Za Zb Y
0 0 0 0 × × × × × × × 0 × 0
0 0 0 1 × × × × × × × 1 × 1
0 0 1 × 0 × × × × × × 0 × 0
0 0 1 × 1 × × × × × × 1 × 1
0 1 0 × × 0 × × × × × 0 × 0
0 1 0 × × 1 × × × × × 1 × 1
0 1 1 × × × 0 × × × × 0 × 0
0 1 1 × × × 1 × × × × 1 × 1
1 0 0 × × × 0 × × × × 0 0
1 0 0 × × × × 1 × × × × 1 1
1 0 1 × × × × × 0 × × × 0 0
1 0 1 × × × × × 1 × × × 1 1

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1 1 0 × × × × × × 0 × × 0 0
1 1 0 × × × × × × 1 × × 1 1
1 1 1 × × × × × × × 0 × 0 0
1 1 1 × × × × × × × 1 × 1 1

Pre-Experiment Questions:
Q.1 Difference between Encoder and Decoder.
Q.2 Explain the need of multiplexer.
Q.3 Which is the major functioning responsibility of the multiplexing combinational circuit?
Q.4 How many NOT gates are required for the construction of a 4-to-1 multiplexer?

Procedure:
 Collect the components necessary to accomplish this experiment.
 Plug the IC chip into the breadboard.
 Connect the supply voltage and ground lines to the chips. PIN7 = Ground
 and PIN14 = +5V.
 Make connections as shown in the respective circuit diagram.
 Connect the inputs of the gate to the input switches of the LED.
 Connect the output of the gate to the output LEDs.
 Once all connections have been done, turn on the power switch of the breadboard
 Operate the switches and fill in the truth table ( Write "1" if LED is ON and "0" if
L1 is OFF Apply the various combination of inputs according to the truth table and
observe the condition of Output LEDs.

Result & Conclusion: 3-8 line decoder, 4x1 and 8x1 Mux have been implemented &
verified through truth table.

Post Experiment Questions:

Q.1 Design a 5 to 32 decoder using one 2 to 4 and four 3 to 8 decoder IC’S.
Q.2 Write a note on BCD to decimal decoder.
Q.3 In 1-to-4 de-multiplexer, how many select lines are required?
Q.4 Which IC is used for the implementation of 1-to-16 DEMUX?

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EXPERIMENT 5

Aim: Verify the excitation table of various FLIP-FLOPS

Equipments & Components Required:

S.No. Equipments Specification Quantity

1 Digital IC Trainer kit - 1
2 Digital Multimeter 1
3. Components Required:
S.No. Components Specification Quantity
7400, 7402,
7404,
1 Digital ICs 1 each
7408, 7432,
7486.
2 Patch cords - 6

Theory:
Flip-flops are synchronous bi-stable devices. The term synchronous means the output changes
state only when the clock input is triggered. That is, changes in the output occur in
synchronization with the clock. A flip-flop circuit has two outputs, one for the normal value
and one for the complement value of the stored bit. Since memory elements in sequential
circuits are usually flip-flops, it is worth summarizing the behaviour of various flip-flop types
before proceeding further. All flip -flops can be divided into four basic types: SR, JK, D and
T. They differ in the number of inputs and in the response invoked by different value of input
signals. The four types of flip -flops are defined in the Table below.

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Circuit Diagram

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Pre-Experiment Questions:
Q.1 Difference between Latch and Flip Flop.
Q.2 Differentiate between combinational and sequential circuits.
Q.3 The truth table for an S-R flip-flop has how many VALID entries?
Q.4 What is a trigger pulse?

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Procedure:
 Collect the components necessary to accomplish this experiment.
 Plug the IC chip into the breadboard.
 Connect the supply voltage and ground lines to the chips. PIN7 = Ground
 and PIN14 = +5V.
 Make connections as shown in the respective circuit diagram.
 Connect the inputs of the gate to the input switches of the LED.
 Connect the output of the gate to the output LEDs.
 Once all connections have been done, turn on the power switch of the breadboard
 Operate the switches and fill in the truth table ( Write "1" if LED is ON and "0" if
L1 is OFF Apply the various combination of inputs according to the truth table and
observe the condition of Output LEDs.

Result & Conclusion: Verified excitation table of various flip flops.

Post Experiment Questions:

Q.1 How is a JK Flip Flop made to toggle?
Q.2 How many stable states does a Flip Flop has?
Q.3 What is the significance of the J and K terminals on the J-K flip-flop?
Q.4 Determine the output frequency for a frequency division circuit that contains 12 flip-
flops with an input clock frequency of 20.48 MHz.

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EXPERIMENT 6

Aim: Design and implement 8-bit Input/Output System with four 8-bit internal registers

Equipment’s & Components Required :

S.No. Equipments Specification Quantity

1 Logic Simulator - 1

S.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 15

Theory:
A register is capable of shifting its binary information in one or both directions is known as
shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with
output of one flip flop connected to input of next flip flop. All flip flops receive common
clock pulses which causes the shift in the output of the flip-flop. The simplest possible shift
register is one that uses only flip flop. The output of a given flip flop is connected to the input
of next flip flop of the register. Each clock pulse shifts the content of register one bit position
to right.

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LOGIC DIAGRAM:
8-bit Input/Output System with four 8-bit internal register

Pre-Experiment Questions:
Q.1 What are the functions of a bus?
Q.2 State the features of multiplexers.
Q.3 What is the difference between register and counter?
Q.4 Explain serial shifting method.

Procedure:
 Connections are given as per circuit diagram.
 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.
Result & Conclusion: Verified 8-bit Input/Output System with four 8-bit internal
registers on simulator.

Post-Experiment Questions:
Q.1 What are the advantages of using bus interface?

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Q.2 Define an Internal register?

Q.3 How many types of registers are there?
Q.4 What is a binary register?

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EXPERIMENT 7

Aim: Design of an 8- bit ARITHMETIC LOGIC UNIT.

Equipment’s & Components Required :

S.No. Equipments Specification Quantity

1 Logic Simulator - 1

Theory:
ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic operations like addition,
subtraction, division, multiplication and logical operations like and, or, xor, nand, nor etc. A
simple block diagram of a 4 bit ALU for operations and, or, xor and Add is shown in the
Logic diagram.

LOGIC DIAGRAM:
Block diagram of a 4 bit ALU

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Design Issues :
The circuit functionality of a 1 bit ALU is shown here, depending upon the control signal S1
and S0 the circuit operates as follows:
for Control signal S1 = 0 , S0 = 0, the output is A And B,
for Control signal S1 = 0 , S0 = 1, the output is A Or B,
for Control signal S1 = 1 , S0 = 0, the output is A Xor B,
for Control signal S1 = 1 , S0 = 1, the output is A Add B.
The truth table for 16-bit ALU with capabilities similar to 74181 is shown here:
Required functionality of ALU (inputs and outputs are active high)
Mode Select Fn for active HIGH operands
Inputs Logic Arithmetic (note
2) S3 S2 S1 S0 (M = H) (M = L) (Cn=L)
L L L L A' A
L L L H A'+B' A+B
L L H L A'B A+B'
L L H H Logic 0 minus 1
L H L L (AB)' A plus AB'

L H H L A⊕ B
L H L H B' (A + B) plus AB'
A minus B minus 1
L H H H AB' AB minus 1

H L L H (A ⊕ B)'
H L L L A'+B A plus AB
A plus B
H L H L B (A + B') plus AB
H L H H AB AB minus 1
H H L L Logic 1 A plus A (Note 1)
H H L H A+B' (A + B) plus A
H H H L A+B (A + B') plus A
H H H H A A minus 1

The L denotes the logic low and H denotes logic high.

Pre-Experiment Questions:
Q.1 What are the functions of a an ALU?
Q.2 How does an ALU work?
Q.3 Describe the components of ALU.
Q.4 What are the basic operations of I/O unit?

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Procedure:
 Connections are given as per circuit diagram.
 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.

Result & Conclusion: Verified the design of an 8 bit ALU.

Post-Experiment Questions:
Q.1 What are the functions of a CPU?
Q.2 What are the components of CPU and how are they interconnected?
Q.3 What are the basic operations of memory unit?
Q.4 How many ALU’s a computer can have?

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EXPERIMENT 10

Aim: Design and implementation of HALF SUBTRACTOR, FULL

SUBTRACTOR using basic logic gates

Equipment & Components Required:

S.No. Equipments Specification Quantity

1 Digital IC Trainer kit - 1
2 Digital Multimeter 1

S.No. Components Specification Quantity

7400, 7402,
7404,
1 each
1 Digital ICs 7408, 7432,
7486.
- 6
2 Patch cords

Theory:

a) To design and implement half Subtractor using logic gates

HALF SUBTRACTOR

OUTPUTS
INPUT X INPUT Y
D B

0 0 0 0
0 1 1 1
1 0 1 0

CIRCUIT 1 1 0 0
DIAGRAM TRUTH TABLE

b) To design and implement full subtractor using logic gates

FULL SUBTRACTOR

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INPUTS OUTPUTS
A B BIN D BOUT
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

CIRCUIT DIAGRAM TRUTH TABLE

.
Pre-Experiment Questions:
Q.1 Explain the truth table of half subtractor.
Q.2 How many Ex-or and or or gate can be used to make a half subtractor?
Q.3 Why XOR gate is called an inverter?
Q.4 How many outputs are required for the implementation of a subtractor?

Procedure:
 Identify the pins.
 Connect the circuit as per circuit diagram.
 Obtain outputs with various input combinations.
 Verify it with the Boolean function using truth table

Result & Conclusion: All logical circuits have been implemented & verified through
truth table.

Post-Experiment Question:
Q.1What are the applications of half subtractor?
Q.2 What are the applications of full subtractor?
Q.3 What does minuend and subtrahend denotes in a subtractor?
Q.4 How can a full subtractor be implemented?

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EXPERIMENT 11

Aim: Design and implementation of SISO and SIPO shift registers

Equipments & Components Required:

SL.No. Equipments Specification Quantity

1 Logic Simulator -

Sl.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
3. IC TRAINER KIT - 1
4. PATCH CORDS - 15

Theory:
A register is capable of shifting its binary information in one or both directions is known as
shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with
output of one flip flop connected to input of next flip flop. All flip flops receive common
clock pulses which causes the shift in the output of the flip flop. The simplest possible shift
register is one that uses only flip flop. The output of a given flip flop is connected to the input
of next flip flop of the register. Each clock pulse shifts the content of register one bit position
to right.

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LOGIC DIAGRAM:

SERIAL IN SERIAL OUT:

TRUTH TABLE:
Serial in Serial out
CLK
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

SERIAL IN PARALLEL OUT:

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TRUTH TABLE:
OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

Pre-Experiment Questions:
Q.1 State the features of Shift Registers.
Q.2 What is the main functionality of Shift Registers?
Q.3 How can parallel data be taken out of a shift register simultaneously?
Q.4 What is meant by parallel load of a shift register?

Procedure:
 Connections are given as per circuit diagram.
 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.

Result: All Shift registers have been implemented & verified through truth table.

Post-Experiment Questions:
Q.1 How can we use shift registers in serial communications? Explain.
Q.2 List the ICs which are used as 8 bit SISO, SIPO modes and as a bidirectional shift
register.
Q.3 Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store
the nibble 1100. What will be the 4-bit pattern after the second clock pulse?
Q.4 List the categories for classification of shift registers.

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EXPERIMENT 12

Aim: Design and implementation of PISO and PIPO shift registers

E q u ip men t’s & Co mp o n en ts Req u ired :

S.No. Equipment’s Specification Quantity

1 Logic Simulator -

S.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
3. IC TRAINER KIT - 1
4. PATCH CORDS - 15

Theory:
A register is capable of shifting its binary information in one or both directions is known as
shift register. The logical configuration of shift register consist of a D-Flip flop cascaded
with output of one flip flop connected to input of next flip flop. All flip flops receive
common clock pulses which causes the shift in the output of the flip flop.The simplest
possible shift register is one that uses only flip flop. The output of a given flip flop is
connected to the input of next flip flop of the register. Each clock pulse shifts the content of
register one bit position to right.

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LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:

TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

PARALLEL IN PARALLEL OUT:

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TRUTH TABLE:
DATA INPUT OUTPUT
CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

Pre-Experiment Questions:
Q.1 State the features of Parallel Shift Registers.
Q.2 Differentiate between serial and parallel Shift Registers.
Q.3 How many clock pulses will be required to completely load serially a 5-bit shift register?
Q.4 What are the three output conditions of a three-state buffer?

Procedure:
 Connections are given as per circuit diagram.
 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.

Result & Conclusion: All shift registers have been implemented & verified through
truth table.

Post-Experiment Questions:
Q.1 What are the differences between serial loading and parallel loading?
Q.2 In what type of register do we have access to only left most or right most flip flops
Q.3 How many clock pulses are required to serially enter a byte of data into an 8-bit register?
Q.4 List the ICs which are used as 8 bit PISO, PIPO modes and as a bidirectional shift
register.

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References

1. Patterson, “ Computer Organization and Design” Elsevier Pub. 2009

2. William Stalling, “ Computer Organization”, PHI
3. Logic Simulator - https://www.kolls.net/gatesim
4. COA virtual lab - cse10-iitkgp.virtual-labs.ac.in

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