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Verilog Info

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Anindita Dash
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7 views

Verilog Info

Uploaded by

Anindita Dash
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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OM MAA

1. Verilog full case Vs Verilog Parallel Case


2. Difference Between “==” and “===”
3. What does Wire refer to?
4. What is reg in Verilog?
5. What are blocking and non-blocking in Verilog?
6. Difference between Task and Function.
7. What is the sensitivity list?
8. Explain $monitor, $display and $strobe.
9. What is transport delay?
10. What is the inertial delay?
11. What are the ways of writing FSM code?
12. Explain Deposit and Force command.
13. Explain Freeze and Drive.
14. What does `timescale 1ns/1ps mean?
15. Within variable and signal which will be updated First?
16. What is PLI?
17. What is a continuous assignment?
18. Explain the repeat loop.
19. What is DPI Call?
20. What is the difference between casex and casez.
21. Write a Verilog program to switch the contents of two registers with and without a temporary
register.
22. How can a sine wave be produced using Verilog coding?
23. Can race conditions occur in Verilog?
24. Difference between Inter statement and intra statement delay?
25. What is Delta Simulation Time?
26. What is meant by inferring latches and how can we avoid it?
27. Difference Between Synchronous and Asynchronous Reset?
28. In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? if yes,
why?
29. Can you tell me some of system tasks and their purpose?
30. What are the different types of data types in Verilog?
31. How do you specify input and output ports in Verilog?
32. How do you specify a conditional statement in Verilog?
33. What is an always block in Verilog and when is it used?
34. What is a module in Verilog and how is it used?
35. How do you implement a bidirectional ports in Verilog HDL?
36. What does it mean in Verilog case(1’b1)?
37. Why is it that “if(2’b01 & 2’b10)” doesn’t run the true case?
38. What are different types of Verilog simulaors?
39. Difference between while and do-while loop?
40. What is an automatic keyword in the task?
41. Difference between flip-flop and latch.
42. Explain the difference between a static and automatic variable with example.
43. Difference between $stop and $finish.
44. Difference between $random and $urandom
45. What is the default value of wire and reg?
46. What is #0 in Verilog and its usage?
47. Write a Verilog code for D-Latch.
48. How can you override the existing parameter value?
49. Difference between `define and `include.
50. What will be output of the following code
always@(clock) begin
a = 0;
a <= 1;
$display(a);
end
51. What will happen if there is no else part in if-else?
52. How can you define strength in Verilog?
53. What is parameter overriding in Verilog?
54. Can you talk about the Verilog event scheduler?
55. What will be the output of x, y, z if c is the clock?
logic m = c;
reg n = c;
wire o = c;

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