CSC 315: Computer Organization and Architecture (3 Units)

The Arithmetic and Logic Unit

The ALU is that part of the computer that actually performs arithmetic and logical operations on data.
All of the other elements of the computer system—control unit, registers, memory, I/O—are there
mainly to bring data into the ALU for it to process and then to take the results back out. We have, in a
sense, reached the core or essence of a computer when we consider the ALU. An ALU and indeed, all
electronic components in the computer, are based on the use of simple digital logic devices that can
store binary digits and perform simple Boolean logic operations. Figure 1 indicates, in general terms,
how the ALU is interconnected with the rest of the processor.

Figure 1: ALU Inputs and Outputs

Operands for arithmetic and logic operations are presented to the ALU in registers, and the results of
an operation are stored in registers. These registers are temporary storage locations within the
processor that are connected by signal paths to the ALU. The ALU may also set flags as the result of
an operation. For example, an overflow flag is set to 1 if the result of a computation exceeds the length
of the register into which it is to be stored. The flag values are also stored in registers within the
processor. The processor provides signals that control the operation of the ALU and the movement of
the data into and out of the ALU.

Integer Representation

In the binary number system,1 arbitrary numbers can be represented with just the digits zero and one,
the minus sign (for negative numbers), and the period, or radix mpoint (for numbers with a fractional
component).

For purposes of computer storage and processing, however, we do not have the benefit of special
symbols for the minus sign and radix point. Only binary digits (0 and 1) may be used to represent
numbers. If we are limited to nonnegative integers, the representation is straightforward.

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There are several alternative conventions used to represent negative as well as positive integers, all of
which involve treating the most significant (leftmost) bit in the word as a sign bit. If the sign bit is 0, the
number is positive; if the sign bit is 1, the number is negative.
The simplest form of representation that employs a sign bit is the sign-magnitude representation. In an
n-bit word, the rightmost n - 1 bits hold the magnitude of the integer.

The general case can be expressed as follows:

……………………..(1)

There are several drawbacks to sign-magnitude representation. One is that addition and subtraction
require a consideration of both the signs of the numbers and their relative magnitudes to carry out the
required operation. Another drawback is that there are two representations of 0:

This is inconvenient because it is slightly more difficult to test for 0 (an operation performed frequently
on computers) than if there were a single representation. Because of these drawbacks, sign-magnitude
representation is rarely used in implementing the integer portion of the ALU. Instead, the most common
scheme is twos complement representation.2

Twos Complement Representation

Like sign magnitude, twos complement representation uses the most significant bit as a sign bit,
making it easy to test whether an integer is positive or negative. It differs from the use of the sign-
magnitude representation in the way that the other bits are interpreted. Table 1 highlights key

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characteristics of twos complement representation and arithmetic, which are elaborated in this section
and the next. Most treatments of twos complement representation focus on the rules for producing
negative numbers, with no formal proof that the scheme is valid. The advantage of this treatment is
that it does not leave any lingering doubt that the rules for arithmetic operations in twos complement
notation may not work for some special cases.

Table 1: Characteristics of Twos Complement Representation and Arithmetic

Consider an n-bit integer, A, in twos complement representation. If A is positive, then the sign bit, an-1,
is zero. The remaining bits represent the magnitude of the number in the same fashion as for sign
magnitude:

The number zero is identified as positive and therefore has a 0 sign bit and a magnitude of all 0s. We
can see that the range of positive integers that may be represented is from 0 (all of the magnitude bits
are 0) through 2n-1 - 1 (all of the magnitude bits are 1). Any larger number would require more bits.
Now, for a negative number A(A 6 0), the sign bit, an-1, is one. The remaining n - 1 bits can take on
any one of 2n-1 values. Therefore, the range of negative integers that can be represented is from -1 to
-2n-1. We would like to assign the bit values to negative integers in such a way that arithmetic can be
handled in a straightforward fashion, similar to unsigned integer arithmetic. In unsigned integer
representation, to compute the value of an integer from the bit representation, the weight of the most
significant bit is +2n-1. For a representation with a sign bit, it turns out that the desired arithmetic
properties are achieved, if the weight of the most significant bit is -2n-1. This is the convention used in
twos complement representation, yielding the following expression for negative numbers:

………………………………………………(2)

Equation (2) defines the twos complement representation for both positive and negative numbers. For
and the equation defines a nonnegative integer. When
is subtracted from the summation term, yielding a negative integer.
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Table 2: Alternative Representations for 4-Bit Integers

Table 2 compares the sign-magnitude and twos complement representations for 4-bit integers.
Although twos complement is an awkward representation from the human point of view, we will see
that it facilitates the most important arithmetic operations, addition and subtraction. For this reason, it is
almost universally used as the processor representation for integers.
A useful illustration of the nature of twos complement representation is a value box, in which the value
on the far right in the box is 1 (20) and each succeeding position to the left is double in value, until the
leftmost position, which is negated.
As you can see in Figure.2a, the most negative twos complement number that can be represented is -
2n-1; if any of the bits other than the sign bit is one, it adds a positive amount to the number. Also, it is
clear that a negative number must have a 1 at its leftmost position and a positive number must have a
0 in that position. Thus, the largest positive number is a 0 followed by all 1s, which equals 2n-1 - 1.
The rest of Figure .2 illustrates the use of the value box to convert from twos complement to decimal
and from decimal to twos complement.

Range Extension

It is sometimes desirable to take an n-bit integer and store it in m bits, where m 7 n. This expansion of
bit length is referred to as range extension, because the range of numbers that can be expressed is
extended by increasing the bit length.

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Figure 10.2 Use of a Value Box for Conversion between Twos Complement Binary and Decimal

In sign-magnitude notation, this is easily accomplished: simply move the sign bit to the new leftmost
position and fill in with zeros.

This procedure will not work for twos complement negative integers. Using the same example,

The next to last line is easily seen using the value box of Figure 2. The last line can be verified using
Equation (2) or a 16-bit value box.
Instead, the rule for twos complement integers is to move the sign bit to the new leftmost position and
fill in with copies of the sign bit. For positive numbers, fill in with zeros, and for negative numbers, fill in
with ones. This is called sign extension.

To see why this rule works, let us again consider an n-bit sequence of binary digits
as a twos complement integer A, so that its value is

If A is a positive number, the rule clearly works. Now, if A is negative and we want to construct an m-bit
representation, with m >n. Then
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In going from the first to the second equation, we require that the least significant n - 1 bits do not
change between the two representations. Then we get to the next to last equation, which is only true if
all of the bits in positions n - 1 through m - 2 are 1. Therefore, the sign-extension rule works.

Fixed-Point Representation

Finally, we mention that the representations discussed in this section are sometimes referred to as
fixed point. This is because the radix point (binary point) is fixed and assumed to be to the right of the
rightmost digit. The programmer can use the same representation for binary fractions by scaling the
numbers so that the binary point is implicitly positioned at some other location.

Integer Arithmetic

Negation
In sign-magnitude representation, the rule for forming the negation of an integer is simple: invert the
sign bit. In twos complement notation, the negation of an integer can be formed with the following
rules:
1. Take the Boolean complement of each bit of the integer (including the sign bit). That is, set each
1 to 0 and each 0 to 1.
2. Treating the result as an unsigned binary integer, add 1.
This two-step process is referred to as the twos complement operation, or the taking of the twos
complement of an integer.

As expected, the negative of the negative of that number is itself:

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We can demonstrate the validity of the operation just described using the definition of the twos
complement representation in Equation (2). Again, interpret an n-bit sequence of binary digits
as a twos complement integer A, so that its value is

The preceding derivation assumes that we can first treat the bitwise complement of A as an unsigned
integer for the purpose of adding 1, and then treat the result as a twos complement integer. There are
two special cases to consider. First, consider A = 0. In that case, for an 8-bit representation:

There is a carry out of the most significant bit position, which is ignored. The result is that the negation
of 0 is 0, as it should be. The second special case is more of a problem. If we take the negation of the
bit pattern of 1 followed by n - 1 zeros, we get back the same number. For example, for 8-bit words,

Some such anomaly is unavoidable. The number of different bit patterns in an n-bit word is 2n, which is
an even number. We wish to represent positive and negativeintegers and 0. If an equal number of
positive and negative integers are represented (sign magnitude), then there are two representations for
0. If there is only one representation of 0 (twos complement), then there must be an unequal number of

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negative and positive numbers represented. In the case of twos complement, for an n-bit length, there
is a representation for

Addition and Subtraction

Addition in twos complement is illustrated in Figure 3. Addition proceeds as if the two numbers were
unsigned integers. The first four examples illustrate successful operations. If the result of the operation
is positive, we get a positive number in twos complement form, which is the same as in unsigned-
integer form. If the result of the operation is negative, we get a negative number in twos complement
form. On any addition, the result may be larger than can be held in the word size being used. This
condition is called overflow. When overflow occurs, the ALU must signal this fact so that no attempt is
made to use the result. To detect overflow, the following rule is observed:

Figure 3: Addition of Numbers in Twos Complement Representation

Figures 3e and f show examples of overflow. Note that overflow can occur whether or not there is a
carry.

Subtraction is easily handled with the following rule:

Subtraction rule: To subtract one number (subtrahend) from another (minuend), take the twos
complement (negation) of the subtrahend and add it to the minuend.
Thus, subtraction is achieved using addition, as illustrated in Figure 4. The last two examples
demonstrate that the overflow rule still applies.

Some insight into twos complement addition and subtraction can be gained by looking at a geometric
depiction as shown in Figure 5. The circle in the upper half of each part of the figure is formed by
selecting the appropriate segment of the number line and joining the endpoints. Note that when the
numbers are laid out on a circle, the twos complement of any number is horizontally opposite that
number (indicated by dashed horizontal lines). Starting at any number on the circle, we can add
positive k (or subtract negative k) to that number by moving k positions clockwise, and we can subtract
positive k (or add negative k) from that number by moving k positions counter clockwise. If an
arithmetic operation results in traversal of the point where the endpoints are joined, an incorrect
answer is given (overflow).
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Figure 4: Subtraction of Numbers in Twos Complement Representation (M - S)

Figure 5: Geometric Depiction of Twos Complement Integers

NOTE: All of the examples of Figures 3 and 4 are easily traced in the circle of Figure 5.

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Figure 6 suggests the data paths and hardware elements needed to accomplish addition and
subtraction. The central element is a binary adder, which is presented two numbers for addition and
produces a sum and an overflow indication. The binary adder treats the two numbers as unsigned
integers. For addition, the two numbers are presented to the adder from two registers, designated in
this case as A and B registers. The result may be stored in one of these registers or in a third. The
overflow indication is stored in a 1-bit overflow flag (0 = no overflow; 1 = overflow). For subtraction, the
subtrahend (B register) is passed through a twos complementer so that its twos complement is
presented to the adder. Note that Figure 6 only shows the data paths. Control signals are needed to
control whether or not the complementer is used, depending on whether the operation is addition or
subtraction.

Figure 6 Block Diagram of Hardware for Addition and Subtraction

Multiplication
Compared with addition and subtraction, multiplication is a complex operation, whether performed in
hardware or software. A wide variety of algorithms have been used in various computers. The purpose
of this subsection is to give the reader some feel for the type of approach typically taken. We begin
with the simpler problem of multiplying two unsigned (nonnegative) integers, and then we look at one
of the most common techniques for multiplication of numbers in twos complement representation.
UNSIGNED INTEGERS: Figure 7 illustrates the multiplication of unsigned binary integers, as might be
carried out using paper and pencil. Several important observations can be made:
1. Multiplication involves the generation of partial products, one for each digit in the multiplier.
These partial products are then summed to produce the final product.
2. The partial products are easily defined. When the multiplier bit is 0, the partial product is 0. When
the multiplier is 1, the partial product is the multiplicand.
3. The total product is produced by summing the partial products. For this operation, each
successive partial product is shifted one position to the left relative to the preceding partial
product.
4. The multiplication of two n-bit binary integers results in a product of up to 2n bits in length (e.g.,
11 * 11 = 1001).
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Figure 7: Multiplication of Unsigned Binary Integers

Compared with the pencil-and-paper approach, there are several things we can do to make
computerized multiplication more efficient. First, we can perform a running addition on the partial
products rather than waiting until the end. This eliminates the need for storage of all the partial
products; fewer registers are needed. Second, we can save some time on the generation of partial
products. For each 1 on the multiplier, an add and a shift operation are required; but for each 0, only a
shift is required.

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Figure 8a shows a possible implementation employing these measures. The multiplier and multiplicand
are loaded into two registers (Q and M). A third register, the A register, is also needed and is initially
set to 0. There is also a 1-bit C register, initialized to 0, which holds a potential carry bit resulting from
addition. The operation of the multiplier is as follows. Control logic reads the bits of the multiplier one at
a time. If Q0 is 1, then the multiplicand is added to the A register and the result is stored in the A
register, with the C bit used for overflow. Then all of the bits of the C, A, and Q registers are shifted to
the right one bit, so that the C bit goes into An-1, A0 goes into Qn-1, and Q0 is lost. If Q0 is 0, then no
addition is performed, just the shift. This process is repeated for each bit of the original multiplier.
The resulting 2n-bit product is contained in the A and Q registers. A flowchart of the operation is shown
in Figure 9, and an example is given in Figure 8b. Note that on the second cycle, when the multiplier
bit is 0, there is no add operation.

TWOS COMPLEMENT MULTIPLICATION We have seen that addition and subtraction can be
performed on numbers in twos complement notation by treating them as unsigned integers. Consider:

If these numbers are considered to be unsigned integers, then we are adding 9 (1001) plus 3 (0011) to
get 12 (1100). As twos complement integers, we are adding - 7(1001) to 3 (0011) to get - 4(1100).

Figure 10: Multiplication of Two

Unsigned 4-Bit Integers ielding an

8-Bit Result

Figure 9: Flowchart for Unsigned Binary Multiplication

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Figure 13: Example of Booth’s Algorithm (7 * 3)

Figure 12 Booth’s Algorithm for Twos Complement

Multiplication

Division
Division is somewhat more complex than multiplication but is based on the same general principles. As
before, the basis for the algorithm is the paper-and-pencil approach, and the operation involves
repetitive shifting and addition or subtraction.
Figure 15 shows an example of the long division of unsigned binary integers. It is instructive to
describe the process in detail. First, the bits of the dividend are examined from left to right, until the set
of bits examined represents a number greater than or equal to the divisor; this is referred to as the
divisor being able to divide the number. Until this event occurs, 0s are placed in the quotient from left
to right. When the event occurs, a 1 is placed in the quotient and the divisor is subtracted from the
partial dividend. The result is referred to as a partial remainder.

Figure 14: Example of Division of Unsigned Binary Integers

From this point on, the division follows a cyclic pattern. At each cycle, additional bits from the dividend
are appended to the partial remainder until the result is greater than or equal to the divisor. As before,

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the divisor is subtracted from this number to produce a new partial remainder. The process continues
until all the bits of the dividend are exhausted.
Figure 15 shows a machine algorithm that corresponds to the long division process. The divisor is
placed in the M register, the dividend in the Q register. At each step, the A and Q registers together are
shifted to the left 1 bit. M is subtracted from A to determine whether A divides the partial remainder.3 If
it does, then Q0 gets a 1 bit. Otherwise, Q0 gets a 0 bit and M must be added back to A to restore the
previous value. The count is then decremented, and the process continues for n steps. At the end, the
quotient is in the Q register and the remainder is in the A register.

Figure 15: Flowchart for Unsigned Binary Division

Figure 16: Example of Restoring Twos

Complement Division (7/3)
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