CSC 315: Computer Organization and Architecture (3 Units)

INTEL x86 AND ARM DATA TYPES

x86 Data Types: The x86 can deal with data types of 8 (byte), 16 (word), 32 (doubleword), 64
(quadword), and 128 (double quadword) bits in length. To allow maximum flexibility in data structures
and efficient memory utilization, words need not be aligned at even-numbered addresses; doublewords
need not be aligned at addresses evenly divisible by 4; quadwords need not be aligned at addresses
evenly divisible by 8; and so on. However, when data are accessed across a 32-bit bus, data transfers
take place in units of doublewords, beginning at addresses divisible by 4. The processor converts the
request for misaligned values into a sequence of requests for the bus transfer. As with all of the Intel
80x86 machines, the x86 uses the little-endian style; that is, the least significant byte is stored in the
lowest address.
The byte, word, doubleword, quadword, and double quadword are referred to as general data types. In
addition, the x86 supports an impressive array of specific data types that are recognized and operated
on by particular instructions. Table 1 summarizes these types. Figure 1 illustrates the x86 numerical
data types. The signed integers are in twos complement representation and may be 16, 32, or 64 bits
long. The floating-point type actually refers to a set of types that are used by the floating-point unit and
operated on by floating-point instructions. The floating-point representations conform to the IEEE 754
standard. The packed SIMD (single-instruction-multiple-data) data types were introduced to the x86
architecture as part of the extensions of the instruction set to optimize performance of multimedia
applications. These extensions include MMX (multimedia extensions) and SSE (streaming SIMD
extensions). The basic concept is that multiple operands are packed into a single referenced memory
item and that these multiple operands are operated on in parallel. The data types are as follows:
 Packed byte and packed byte integer: Bytes packed into a 64-bit quadword or 128-bit double
quadword, interpreted as a bit field or as an integer.
 Packed word and packed word integer: 16-bit words packed into a 64-bit quadword or 128-
bit double quadword, interpreted as a bit field or as an integer.
 Packed doubleword and packed doubleword integer: 32-bit doublewords packed into a 64-it
quadword or 128-bit double quadword, interpreted as a bit field or as an integer.
 Packed quadword and packed quadword integer: Two 64-bit quadwords packed into a 128-
bit double quadword, interpreted as a bit field or as an integer.
 Packed single-precision floating-point and packed double-precision floatingpoint: Four
32-bit floating-point or two 64-bit floating-point values packed into a 128-bit double quadword.
ARM Data Types:- ARM processors support data types of 8 (byte), 16 (halfword), and 32 (word) bits in
length. Normally, halfword access should be halfword aligned and word accesses should be word
aligned. For onaligned access attempts, the architecture supports three alternatives.
 Default case:
– The address is treated as truncated, with address bits[1:0] treated as zero for word accesses,
and address bit[0] treated as zero for halfword accesses.
– Load single word ARM instructions are architecturally defined to rotate right the word-aligned
data transferred by a non word-aligned address one, two, or three bytes depending on the value
of the two least significant address bits.
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 CSC 315: Computer Organization and Architecture (3 Units)
Table 1: x86 Data Types

Figure 1: x86 Numeric Data Formats

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 CSC 315: Computer Organization and Architecture (3 Units)
 Alignment checking: When the appropriate control bit is set, a data abort signal indicates an
alignment fault for attempting unaligned access.
 Unaligned access: When this option is enabled, the processor uses one or more memory
accesses to generate the required transfer of adjacent bytes transparently to the programmer.
For all three data types (byte, halfword, and word) an unsigned interpretation is supported, in which the
value represents an unsigned, nonnegative integer. All three data types can also be used for twos
complement signed integers.
The majority of ARM processor implementations do not provide floating-point hardware, which saves
power and area. If floating-point arithmetic is required in such processors, it must be implemented in
software. ARM does support an optional floating-point coprocessor that supports the single-and
double-precision floating point data types.
ENDIAN SUPPORT
A state bit (E-bit) in the system control register is set and cleared under program control using the
SETEND instruction. The E-bit defines which endian to load and store data. Figure 2, illustrates the
functionality associated with the E-bit for a word load or store operation. This mechanism enables
efficient dynamic data load/store for system designers who know they need to access data structures
in the opposite endianness to their OS/environment. Note that the address of each data byte is fixed in
memory. However, the byte lane in a register is different.

Figure 2: ARM Endian Support—Word Load/Store with E-Bit

TYPES OF OPERATIONS
The number of different opcodes varies widely from machine to machine. However, the same general
types of operations are found on all machines. Table 2 lists common instruction types in each category
with a brief discussion of the actions taken by the processor to execute a particular type of operation
(summarized in Table 3. A useful and typical categorization is the following:
Data transfer, Arithmetic, Logical, Conversion, I/O, System control and Transfer of control

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 CSC 315: Computer Organization and Architecture (3 Units)
Table 2: Common Instruction Set Operations

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 CSC 315: Computer Organization and Architecture (3 Units)
Table 3: Processor Actions for Various Types of Operations

Data Transfer
The most fundamental type of machine instruction is the data transfer instruction. The data transfer
instruction must specify several things. First, the location of the source and destination operands must
be specified. Each location could be memory, a register, or the top of the stack. Second, the length of
data to be transferred must be indicated. Third, as with all instructions with operands, the mode of
addressing for each operand must be specified.
The choice of data transfer instructions to include in a instruction set exemplifies the kinds of trade-offs
the designer must make. For example, the general location (memory or register) of an operand can be
indicated in either the specification of the opcode or the operand. Table 4 shows examples of the most
common IBM EAS/390 data transfer instructions. Note that there are variants to indicate the amount of
data to be transferred (8, 16, 32, or 64 bits). Also, there are different instructions for register to register,
register to memory, memory to register, and memory to memory transfers. In contrast, the VAX has a
move (MOV) instruction with variants for different amounts of data to be moved, but it specifies
whether an operand is register or memory as part of the operand. The VAX approach is somewhat
easier for the programmer, who has fewer mnemonics to deal with. However, it is also somewhat less
compact than the IBM EAS/390 approach because the location (register versus memory) of each
operand must be specified separately in the instruction.
In terms of processor action, data transfer operations are perhaps the simplest type. If both source and
destination are registers, then the processor simply causes data to be transferred from one register to
another; this is an operation internal to the processor. If one or both operands are in memory, then the
processor must perform some or all of the following actions:
1. Calculate the memory address, based on the address mode.
2. If the address refers to virtual memory, it translate from virtual to real memory address.
3. Determine whether the addressed item is in cache.
4. If not, issue a command to the memory module.
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 CSC 315: Computer Organization and Architecture (3 Units)
Table 4: Examples of IBM EAS/390 Data Transfer Operations

Arithmetic
Most machines provide the basic arithmetic operations of add, subtract, multiply, and divide. These are
invariably provided for signed integer (fixed-point) numbers. Often they are also provided for floating-
point and packed decimal numbers. Other possible operations include a variety of single-operand
instructions; for example,
 Absolute: Take the absolute value of the operand.
 Negate: Negate the operand.
 Increment: Add 1 to the operand.
 Decrement: Subtract 1 from the operand.
The execution of an arithmetic instruction may involve data transfer operations to position operands for
input to the ALU, and to deliver the output of the ALU. Figure 2 illustrates the movements involved in
both data transfer and arithmetic operations. In addition, of course, the ALU portion of the processor
performs the desired operation.
Logical
Most machines also provide a variety of operations for manipulating individual bits of a word or other
addressable units, often referred to as “bit twiddling.” They are based upon Boolean operations.
Some of the basic logical operations that can be performed on Boolean or binary data are shown in
Table 5. The NOT operation inverts a bit. AND, OR, and Exclusive-OR (XOR) are the most common
logical functions with two operands.
EQUAL is a useful binary test. These logical operations can be applied bitwise to n-bit logical data
units.Thus, if two registers contain the data (R1) = 10100101
(R2) = 00001111 then
(R1) AND (R2) = 00000101
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 CSC 315: Computer Organization and Architecture (3 Units)
With one word set to all 1s, the XOR operation inverts all of the bits in the other word (ones
complement). In addition to bitwise logical operations, most machines provide a variety of shifting and
rotating functions. The most basic operations are illustrated in Figure 5. With a logical shift, the bits of
a word are shifted left or right. On one end, the bit shifted out is lost. On the other end, a 0 is shifted in.
Logical shifts are useful primarily for isolating fields within a word. The 0s that are shifted into a word
displace unwanted information that is shifted off the other end.

Figure 5: Shift and Rotate

Operations

Table 6: Examples of Shift and Rotate Operations

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 CSC 315: Computer Organization and Architecture (3 Units)

For example, suppose we wish to transmit characters of data to an I/O device 1 character at a time. If
each memory word is 16 bits in length and contains two characters, we must unpack the characters
before they can be sent. To send the two characters in a word;
1. Load the word into a register.
2. Shift to the right eight times. This shifts the remaining character to the righthalf of the register.
3. Perform I/O. The I/O module reads the lower-order 8 bits from the data bus.
The preceding steps result in sending the left-hand character. To send the right-hand character;
1. Load the word again into the register.
2. AND with 0000000011111111. This masks out the character on the left.
3. Perform I/O.
The arithmetic shift operation treats the data as a signed integer and does not shift the sign bit. On a
right arithmetic shift, the sign bit is replicated into the bit position to its right. On a left arithmetic shift, a
logical left shift is performed on all bits but the sign bit, which is retained. These operations can speed
up certain arithmetic operations. With numbers in twos complement notation, a right arithmetic shift
corresponds to a division by 2, with truncation for odd numbers. Both an arithmetic left shift and a
logical left shift correspond to a multiplication by 2 when there is no overflow. If overflow occurs,
arithmetic and logical left shift operations produce different results, but the arithmetic left shift retains
the sign of the number.
Because of the potential for overflow, many processors do not include this instruction, including
PowerPC and Itanium. Others, such as the IBM EAS/390, do offer the instruction. Curiously, the x86
architecture includes an arithmetic left shift but defines it to be identical to a logical left shift.
Rotate, or cyclic shift, operations preserve all of the bits being operated on. One use of a rotate is to
bring each bit successively into the leftmost bit, where it can be identified by testing the sign of the data
(treated as a number). As with arithmetic operations, logical operations involve ALU activity and may
involve data transfer operations. Table 6 gives examples of all of the shift and rotate operations
discussed earlier.
Conversion
Conversion instructions are those that change the format or operate on the format of data. An example
is converting from decimal to binary. An example of a more complex editing instruction is the EAS/390
Translate (TR) instruction. This instruction can be used to convert from one 8-bit code to another, and
it takes three operands: TR R1 (L), R2
The operand R2 contains the address of the start of a table of 8-bit codes. The L bytes starting at the
address specified in R1 are translated, each byte being replaced by the contents of a table entry
indexed by that byte. For example, to translate from EBCDIC to IRA, we first create a 256-byte table in
storage locations, say, 1000-10FF hexadecimal. The table contains the characters of the IRA code in
the sequence of the binary representation of the EBCDIC code; that is, the IRA code is placed in the
table at the relative location equal to the binary value of the EBCDIC code of the same character.
Thus, locations 10F0 through 10F9 will contain the values 30 through 39, because F0 is the EBCDIC

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 CSC 315: Computer Organization and Architecture (3 Units)
code for the digit 0, and 30 is the IRA code for the digit 0, and so on through digit 9. Now suppose we
have the EBCDIC for the digits 1984 starting at location 2100 and we wish to translate to IRA. Assume
the following: Locations 2100–2103 contain F1 F9 F8 F4.
R1 contains 2100.
R2 contains 1000.
Then, if we execute TR R1 (4), R2 locations 2100–2103 will contain 31 39 38 34.

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