Stack, Subroutines, Interrupts, I/O Control

and Serial Communication

The stack
A stack is a portion (continuous sequence of locations) of the main memory set aside for use as a last in first out (LIFO) storage
area. A register called a stack pointer is used to point to the last data item stored on the stack to enable tracking of the top of the
stack. A stack may be designed to grow upwards or downwards as items are added. Figure 6.1 shows the two types of stacks.

Stack growing
upwards
BASE

END SP
END

BASE
Stack growing
downwards

Figure 6.1. The stack.

For stacks that grow downwards, lower addresses on the stack contain newer data. For stacks that grow upwards, higher addresses
on the stack contain newer data.

A stack is used to store data and addresses that need to be accessed in a LIFO fashion, the major use being storing return addresses
following a branch to a subroutine or an interrupt service routine.

Push and Pop

The terms push and pop (or pull) are used to describe operations on the stack. Push refers to the addition of a data item to the
top of the stack while pop (pull) refers to the removal of the last data item from the stack. The stack pointer is automatically
adjusted to point to the last item on the stack following a push or a pop. Microprocessors have special instructions to push and
pop data from the stack. The common mnemonics for these instructions are PUSH and POP respectively.

The 8086 Stack

The 8086 stack starts from a higher address and grows downwards into the memory. It has a word length of 16 bits. This means
that data is pushed onto and popped from the stack as 16-bit values. The data items are stored using the little endian style. The
stack pointer, SP gives the offset of the last item stored on the stack relative to the base of the stack segment.

The 8086 push instruction can push data in a GPR, segment register or in memory onto the stack. The pop instruction can pop
data from the stack into any GPR, segment register or memory location. A value that has been pushed onto the stack can be
popped back into a different register or memory location, e.g. if DX was pushed onto the stack, it can be popped back into CX.

The 8086 Push Instruction

When a data item is pushed onto the 8086 stack, the following occurs:
1. The stack pointer is decremented by two to point to the next first free memory slot after last item on the stack.
2. The data is stored in the memory location now pointed by stack, i.e., next two free locations on the stack.
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The 8086 Pop Instruction
When a data item is popped from the 8086 stack, the following occurs:
1. The contents of the last two locations on the stack are loaded into a register or memory location.
2. The stack pointer is incremented by two so that it points to the last item on the stack.

Subroutines
A subroutine is a sub-program which can be branched to from a main program. On completion of its execution, instruction
execution can branch back (return) to the main program. A subroutine begins executing when a call to it is made. A call involves
execution of a call instruction in the calling (main) program. The call instruction is a special branch instruction which, in addition
to effecting a jump also pushes the memory address of the instruction following the call instruction to the stack. The return address
is thus preserved on the stack.

A return to the main program is achieved by execution of a return instruction in the subroutine. The return instruction is a special
branch instruction which pops the top of the stack into the instruction pointer so that program execution jumps to the instruction
at the memory location whose address is equal to the last data item on the stack, i.e., jumps to the return address. The return
instruction should always be the last instruction in a subroutine.

The 8086 supports near and far calls/returns. Near calls/returns are calls/returns to addresses within the same segment. Far
calls/returns are calls/returns to addresses in another segment. A near call specifies the call offset only; a far call specifies the
segment selector and the offset of the target instruction. A near return pops back the return offset only; a far return pops back
both the segment selector and the return instruction offset.

The 8086 Near Call Instruction

The following events take place when a near call instruction is executed:
 The IP is pushed onto the stack to preserve the address of the instruction following the call.
 The offset of the instruction to be branched to (relative to the code segment base) is loaded into the IP.
 The stack pointer is decremented by 2 to point to the new top of the stack.

The 8086 Near Return Instruction

The following events occur when a near return instruction is executed:
 The top of the stack is popped into IP (address previously saved in the last call).
 The stack pointer is incremented by 2 to point to the new top of the stack.

The 8086 Far Call Instruction

The following events take place when a far call instruction is executed:
 The CS is pushed onto the stack to preserve the segment selector for the instruction following the call.
 The IP is pushed onto the stack to preserve the offset of the instruction following the call.
 The offset of the instruction to be branched to (relative to segment base) is loaded into the IP.
 The segment selector for the address to be called is loaded into CS.
 The stack pointer is decremented by 4 to point to the new top of the stack.

The 8086 Far Return Instruction

The following events occur when a near return instruction is executed:
 The top of the stack is popped into IP and CS.
 The stack pointer is incremented by 4 to point to the new top of the stack.

Nesting of Subroutines
Subroutines can also be called from other subroutines. This is referred to as nesting subroutines. In theory, the limit on
subroutines that can be nested is determined by the maximum size of the stack.

Advantages of Subroutines
1. Makes programs to be modular. Software routines can be designed and tested as modules. Testing and debugging is
easier in modular software. After debugging each module is integrated into already built routines.
2. It can save memory space. For example, suppose for instance a block of 20 instructions that execute at 5 various points
in a program. This requires a total of 100 instruction spaces in the memory. If the block of instructions is developed into

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 a subroutine, only 21 (plus RET space) locations will be required for the subroutine. 5 more spaces will be required for
calls at the 5 places. The total memory requirement will be 26 spaces saving 74 spaces in memory.

Passing data to and from subroutines

Subroutines may require input data to be passed to the subroutine and output data to be passed out to the calling program. Input
data can be passed to the subroutine by initializing some registers or memory locations with the input data before calling the
subroutine. Alternatively, it can be pushed to the stack before entering the subroutine and popped back on entering the subroutine.
Output data can be passed out by storing it some in registers or some memory locations so that the calling program can access it
from there. Alternatively, it can be pushed to the stack before leaving the subroutine and popped back on entering calling routine.
When using the stack to pass and return values, the data must be popped back into registers/memory in reverse order to that of
pushing them to the stack so that data correctly goes back into the original registers/memory.

Preserving of Microprocessor Register Contents

Subroutines may change contents of some microprocessor registers. If the main program needs to use the original contents of the
registers after execution of the subroutine, then there is need to preserve these registers. Preserving is achieved by pushing the
registers to the stack on entering the subroutine then popping them back before a return from the subroutine.

Interrupts
An interrupt is an asynchronous hardware signal or a software event requiring the attention of a microprocessor. Interrupts,
can thus be divided into hardware and software interrupts. When an interrupt occurs, it causes the microprocessor to automatically
branch to a sub-program (i.e. automatically call a subroutine) specifically designed to handle the conditions that caused the
interrupt. This sub-program is called an interrupt service routine (ISR) or interrupt handler.

Hardware Interrupts
Hardware interrupts are generated by external hardware devices and are signaled to the microprocessor by a voltage signal on an
interrupt pin. The signal can be any of:
 A signal level (low or high level) on a microprocessor’s interrupt pin. Such an interrupt is called a level-triggered
interrupt.
 An edge (rising or falling edge) on a microprocessor’s interrupt pin. Such an interrupt is called an edge-triggered
interrupt.

Hardware interrupts can be classified into maskable and non-maskable interrupts:

 A maskable interrupt is one which may be ignored by the microprocessor. When a hardware interrupt is masked,
interrupt conditions may exist on the interrupt pin but will not cause the microprocessor to branch to the interrupt handler.
Enabling and disabling interrupts is done using microprocessor instructions that usually target some enable bit.
 A non-maskable interrupt is one which cannot be ignored by the microprocessor. Whenever it occurs, the microprocessor
is forced to branch to the service routine.

Examples of Uses of Hardware Interrupts

Hardware interrupts may be used to control and interact with external devices. As an example, a keyboard may be configured to
raise an interrupt each time a key is pressed. When this interrupt is raised, the microprocessor responds by reading the key and
performing an action dictated by the key. Whilst waiting for a key to be pressed, the microprocessor can be doing other tasks.

Hardware interrupts may also be used to perform critical functions in response to some external events. As an example, an
interrupt may be configured to make a microprocessor save critical registers and memory locations to some back up memory
when power fails. The power used in the back up process may be derived from energy stored in power supply smoothing
capacitors.

Software Interrupts, Exceptions and Traps

A software interrupt is initiated by executing an interrupt instruction. An exception is raised when some undesirable condition or
an instruction fault arises during an attempt to execute instructions. Examples of exceptions are an attempt to dived by zero, an
overflow from an arithmetic operation, an attempt to access an invalid memory location and an attempt to execute an invalid
instruction. Examples of traps are the debug (instruction trap) and the debug trap.

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8086 Interrupts, Exceptions and Traps
The 8086 supports hardware interrupts, software interrupts as well as exceptions. The supported hardware interrupts are the
maskable interrupt, INTR and the non-maskable interrupt, NMI. The supported exceptions are the divide and overflow exceptions.
The supported traps are the debug trap and the break point trap. Software interrupts are supported through the interrupt instruction.

The addresses of the respective ISRs for the interrupts are stored in a portion of memory known as a vector table. ISR addresses
that are stored in a vector table are known as interrupt vectors. Each interrupt vector consists of a 16-bit segment selector and a
16-bit offset address which together specify the address of the ISR. The interrupt vector table is located at memory locations
00000h through to 003FFh and contains 256 vector entries giving 256 possible interrupt types.

The different interrupt types are identified by an 8-bit number known as type number. Table 6.1 shows the type numbers for the
various 8086 interrupts and exceptions. Interrupt types 0 to 4 are used by NMI and exceptions. Interrupt types 5 to 31 are reserved
by Intel. Interrupt types 32 to 255 are available for INTR and software interrupts.

Table 6.1. The 8086 Vector table

Type Number Mnemonic Description Source

0 #DE Divide error DIV and IDIV instructions

1 #DB Debug Any code or data reference

2 Non maskable interrupt NMI pin

3 #BP Breakpoint INT 3 instruction

4 #OF Overflow INT 0 instruction

5 – 31 Reserved

32 – 255 Maskable interrupts INTR pin, INT n instruction

The type number of an interrupt is also the index of the corresponding vector into the interrupt vector. The address at which the
vector is located in the table is equal to the type number multiplied by four.

An interrupt or an exception supplies the type number to define its corresponding ISR. For the NMI and exceptions, the type
number is supplied inherently. For INTR, the 8086 issues an interrupt acknowledge cycle during which an interrupting device
supplies the type number via the data bus. For software interrupts, the type number is supplied as the instruction operand.

8086 Response to an interrupt or an Exception

When an interrupt or exception occurs, the 8086 responds as follows:
1. Pushes the flags register onto the stack.
2. Pushes the CS followed by the IP onto the stack.
3. Clears the interrupt flag in the flag register to disable any further maskable interrupts.
4. Determines the type number of the interrupt or exception.
5. Fetches the vector corresponding to the type number from the interrupt vector table.
6. Loads the interrupt vector into CS and IP so as to branch program execution to the ISR.

Things that may be necessary to do in an ISR

If necessary to preserve them, GPRs and segment registers are pushed to the stack on entering the ISR and popped back in reverse
order just before leaving the ISR.

Return from interrupt

Return from an ISR is achieved by executing the interrupt return instruction. The interrupt return is a special return instruction
that before popping the return address (CS and IP), pops the flags off the stack. Popping back flags restores the status of the
interrupt flag and hence re-enables interrupts. It is placed at the end of the ISR.

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I/O Control

Unconditional and Conditional I/O

Unconditional I/O is when an I/O device is always ready to receive data from, or send data to a microprocessor, for example, in
a seven segment display or in a simple switch. The microprocessor can, thus, exchange data with such a device at any time.

Conditional I/O is when an I/O device exchanges data with the microprocessor only when the data is ready, for example a
microprocessor can only read valid data from an ADC after it has completed the conversion process. In conditional I/O, there is
need for some control signals between the I/O device and the port to manage the exchange of data. Figure 6.4 shows the control
signals between an ADC and a port as an example.

I/O Port Chip ADC

8
PortB D0 – D7

Analogue
System input
PortC.0 START
bus

PortC.1 BUSY

PortC.2 OUTPUT ENABLE

Figure 6.4 Interfacing for control of an ADC using a microprocessor

(Note: portc.0, portc.1 and portc.2 are naming conventions for respective bits 0, 1 and 2 on portc)

The START signal, which is used to initiate a conversion process, is generated by a Microprocessor through pin portC.0. Whilst
the conversion is going on, the ADC keeps the BUSY signal active to indicate that digital output data is not yet ready. As soon
as the conversion is completed, the BUSY signal goes low. When the microprocessor detects a low on pin portC.1, which is
connected to the BUSY line, it activates the OUTPUT ENABLE through pin portC.2. This makes the ADC to place its output on
the output pins and hence on the input pins of port B. The digital output can then be read by the Microprocessor through port B.

The control signals that are used to manage the flow of data between an I/O device and an I/O port are called handshaking
signals.

Techniques of Data Transfer

There are two techniques of transferring data between a microprocessor and an I/O device and these are programmed I/O and
strobed I/O.

Programmed I/O
The microprocessor runs a program to control the exchange of data between it and the I/O device. In conditional I/O, the program
usually requires a loop, for example, polling and waiting for a key to be pressed on a keyboard or polling the BUSY line while
waiting for an analog to digital conversion to go to completion.

Polling loops has a disadvantage in that it causes the microprocessor to loose valuable time that could otherwise be used for other
tasks. For slow peripherals, the processor spends a lot of valuable time in polling loops and hence efficiency of using the processor
time is reduced.

Strobed I/O
Strobed I/O is when the port has inbuilt circuitry to exchange handshaking signals with an I/O device. The general handshaking
signals used are:

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  STROBE – a signal from an input device to a port that indicates that it has data ready for reading by the port. The port
can then respond by reading data from the input device. The alternate state indicates that data from the input port is not
yet ready.
 INPUT BUFFER FULL – a signal from a port to an input device that indicates that the port has received data from the
input device. The alternate state indicates that the data has not yet been read.
 OUTPUT BUFFER FULL – a signal from a port to an output device that indicates that the port has data ready for writing
to the output device. The output device can then respond by reading the data form the port. The alternate state indicates
that data for writing to the output device is not yet available.
 ACKNOWLEDGE INPUT – a signal from an output device to a port that indicates that the output device has read in
data from the port. The alternate state indicates that data from the port has not yet been read.
 INTERRUPT – a signal from port to a Microprocessor that indicates a request for attention. In strobed I/O, an interrupt
is raised when the STROBE signal or the ACKNOWLEDGE INPUT signal goes high. The Microprocessor can then
respond by reading in data from the input device (for STROBE active) or writing more data to the output device (for
ACKNOWLEDGE INPUT active).

The STROBE and INPUT BUFFER FULL handshaking signals are used when working with output devices. The OUTPUT
BUFFER FULL and ACKNOWLEDGE INPUT handshaking signals are used when working with input devices.

Operation Modes of Ports

Ports can generally be configured for operation in any of the following modes:
 Basic input/output – parallel input (all pins on port are inputs) or parallel output (all pins on port are outputs) with no
handshaking signals.
 Bit input/output – each pin within the port can individually be set to be an input or output.
 Strobed I/O – parallel input or parallel output port with handshaking signals.
 Bidirectional – port can accept data in either direction and has handshaking signals.

Peripherals with in-built port capabilities

Interfaces to some peripherals are built into chips that contain circuitry that enables the peripheral to be directly connected to the
system bus. Examples of such devices are timers, counters, serial transmitter/receivers, disk controllers. Such a device will contain
the port itself, control registers, interface and control circuitry in one chip.

Direct Memory Access

DMA is the direct transfer of data between an external device and the main memory without involvement of the microprocessor,
for example moving a block of data or program from a storage disk into memory. DMA uses a DMA controller chip to control
the data transfer operation. The DMA chip works in the following way:
 The I/O device requests DMA operation via the DMA request line of the controller chip.
 The DMA controller activates the HOLD pin of the microprocessor. Activating this pin is a way of requesting the
microprocessor to release the system bus.
 The microprocessor responds by putting its address bus, data bus and bus control pins (RD, WR, etc) into a high
impedance state. It then activates the HLDA pin to tell the DMA controller that the bus has been released.
 The DMA controller then controls the system bus so as to transfer data between the I/O device and memory. Controlling
the system bus implies generating the address values necessary on the data bus as well as control signals to enable the
data transfer.
 After completion of the transfer, the DMA controller releases the bus (by deactivating the HOLD pin).

Serial Communication
Serial communication is the transfer of digital data between two electronic devices in which the data bits are transmitted one after
the other. Serial communication can be synchronous or asynchronous. In synchronous communication, the communicating
devices share a clock signal to synchronize the communication. A single bit is transferred in each clock period. The speed of data
transfer is determined by the frequency of the clock signal. The speed of transmission is known as the baud rate and it is equal to
the number of bits transmitted over the line in one second (bps). In asynchronous communication, there is no common clock
signal. Instead, both sides are set to a pre-configured baud rate that dictates the speed and timing of data transmission. Figure 6.5
illustrates synchronous and asynchronous communication.

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 Figure 7.8 (a) Synchronous communication.

Figure 6.5 (b) Asynchronous communication.

Need for serial-parallel conversion

Data in microprocessors is represented in parallel form. To enable transmission and reception of serial data by a microprocessor,
a parallel to serial converter and a serial to parallel converter is required. The converters may be connected to I/O ports.
Alternatively, they may be designed with circuitry to interface directly to the system bus and be seen as a memory location or an
I/O port. An example of a converter is the 8251 Universal Synchronous Asynchronous Receiver/Transmitter (USART).

Need for Level Translation and Modulation

In digital devices generally ‘1’ is represented by 5V and ‘0’ is represented by 0V. In communication links, different voltage levels
may be used, for example, in RS232 protocol, ‘1’ is represented by a voltage in the range -9 to -15V while ‘0’ is represented by
a voltage in the range +9V to +15V. In such cases, a level translation circuit is required between the communication link and the
converter circuit. In some cases, data is required to be transmitted in modulated form and hence a modem is required between the
converter and the communication channel.

Communication Protocols
Communication protocol is the “electronic language” which is used when two devices are communicating. A communication
protocol defines the voltage levels used and the uses for the bits as well as the bit slots. Examples of serial communication
protocols are SPI, USART, I2C, USB, Ethernet and WiFi.

Review Questions
1. What do the following mean: Push? Pop?
2. What do you understand by the following?
a) ‘stack growing’ upwards
b) ‘stack growing downwards’
3. How does a stack pointer keep track of the top of the stack?
4. Describe what happens when:
a) Data is pushed onto the 8086 stack.
b) Data is popped from the 8086 stack.
5. How is a subroutine different from a jump? When does a subroutine begin executing? When does it stop executing?
6. Describe what happens when a far call instruction is executed.
7. Describe what happens when a far return instruction is executed.
8. How do subroutines save memory space?
9. What is nesting?
10. How can data be passed between software routines?
11. Define the following: level triggered interrupt, edge triggered interrupt.
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 12. What are the following: maskable interrupt? Non-maskable interrupt? Which of these interrupt types are supported in
the 8086? Suggest examples of their respective uses?
13. What is a software interrupt? What is an exception? List the exceptions supported in the 8086 microprocessor.
14. What is the difference between an interrupt service routine and a general subroutine?
15. What is a vector? What is a vector table? Describe how interrupt vectoring in the 8086 works.
16. Why may it be necessary to save GPRs on entering an interrupt service routine?
17. What does unconditional i/o mean? What does conditional i/o mean?
18. Describe the handshaking signals in strobed i/o.
19. What are the benefits of interrupts when applied to devices that have conditional i/o?
20. Which modes of operation can a port be generally configured to? Describe each mode.
21. Describe what DMA means.
22. Outline the difference between synchronous communication and asynchronous communication.
23. What is the role of a level translator in serial communication?
24. Outline the role of a USART in serial communication.
25. Outline the role of a modem in serial communication.
26. Compile notes on the following communication protocols: SPI, I2C, RS232, USB, HDMI, S2I. Your account must
give how they work, number of lines and respective purposes, signal types and levels, speed, advantages,
disadvantages and their common applications.

Chapter 6 Tutorial Questions

1. Write a program to read the flags of the 8086 and store them in register DX.

2. Using the stack, develop a program that can be used to set or clear any of the status flags. NB, the 8086 has
no instructions that can directly set or clear the status flags other than CF, IF and DF.

3. Write the program to provide a 5s delay as a subroutine.

4. Suppose there is developed subroutine which when executed offers a delay of 1 second. The subroutine is
located at memory offset 101H. You are required to develop a program that continuously flashes three
lamps (one red, one blue and one white) at intervals of 1s from red to blue, 3s from blue to white and 4s
from white to red. Make use of the subroutine.

5. Develop a subroutine program to add two 32 bit numbers using the 8086. The numbers to be added
together are passed to the subroutine in as DX:AX and BX:CX. The result is passed out in DX:AX. Repeat if
data is to be passed in and out via the stack.

6. Develop a subroutine that can be used to control operation of an 8-bit ADC using an 8086 microprocessor.
After conversion, store the results in register AH.

7. Develop a main program and an interrupt service routine that may be used to run an ADC using interrupts
on an 8086 microprocessor. Draw the proposed interconnection of the system components.

8. Research on how to write/read the 8255 PPI registers and the write 8086 programs that can be used to:
a) Configure port A as a strobed output and port A as a bidirectional bus
b) port A as a parallel input port, port B as a parallel output port, port C lower as an input port and
port C upper as an output port.
c) set bit 4 on port C and clear bit 6 on port C.

9. Research on how to write/read the Z80 PIO and then write 8086 programs that can be used to:
a) port A as a bidirectional bus

56
 b) port B as a bit I/O port, with upper nibble being inputs and lower nibble being outputs.
c) read value on input pins of port B and store in memory location 0A100h.

Program Design Questions

Question 1
a) Develop a program to pack two right-justified BCD codes into a single byte and write it as a subroutine.
The bytes to be packed are contained in the registers DH and DL where DL contains the lower BCD code
and DH contains the higher BCD code. The results are to be stored in register AL.
b) Write a main program to initialise registers DH and DL with BCD codes for 6 and 9; pack them using the
subroutine that you developed in (a) and write the packed BCD codes to port at address 08h.

Question 2
Develop a microprocessor-based system that can be used as a digital scale. The weight value is provided as an 8-
bit number equal to the weight by an ADC connected to a weight measurement circuit. Produce a block diagram of
the system and develop an assembly program. Assume you have a subroutine located at offset 301H that changes
an unpacked BCD code in AH into 7-segment code for displaying the corresponding decimal digit on a seven
segment display with the output seven segment code being stored in AH.

Repeat if the weight measurement sub system has a resolution of 0.25.

Question3
A microprocessor based system is required to control traffic lights at an intersection. The operation is as follows:
 The green lights are of equal durations for both streams, the period being 20 seconds.
 The red lights are of equal durations for both streams, the period being 20 seconds.
 The amber lights are of equal durations for both streams, the period being 5 seconds.
The traffic lights for stream A are connected to pins 0, 1 and 2 of port 06h and the traffic lights on stream B are
connected to pins 4, 5 and 6 of the same port (that is 06h).

Based on delay routines, develop a program that will generate the traffic light sequence at the intersection.

Repeat if traffic on one stream receives twice as much green time as that on the other stream.

Question 4
A system has a battery backed RAM located at addresses E000 to FFFF. Design a system that will save all GPRs and
memory block from address 8001H to 9000H when power fails. The program should be interrupt driven. Produce a
block diagram for the connections between components and a program in assembly language.

Question 5
Design an interrupt driven system that will read the illumination level from an ADC connected to a light sensor
(refer to section on control of peripherals) then switch on or off lights. Produce a block diagram for the
connections between components and a program in assembly language.

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