9/30/2023

ENT 239 Microprocessor Fundamentals

Chapter 2: AVR Architecture and

Assembly Language Programming –
Part 1
DR. FATEMAH BEHBEHANI

Objectives
 Introducing AVR microcontroller architecture.
 Introducing assembly language commands.

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AVR Memory Organization

 AVR microcontroller follows Harvard Architecutre, which has separate memories and bus lines
for program and data.
 Program (Code) Memory:
 Flash ROM, hold program after switching off device.
 Data Memory:
 SRAM, data are not kept when switched off.
 EEPROM, store data permanently.

AVR Memory
Organization
 Data Memory
 General Purpose Registers
(GPRs)
 I/O Registers (Special
Function Registers - SFRs)
 SRAM (Data) Space

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AVR Memory Organization:

Data Memory
 General Purpose Registers (GPRs):
 32 8-bits registers, known as R0-R31
 Addresses: $0000 to $001F
 Store data temporarily while running

 I/O Registers (SFRs):

 64 8-bits registers
 Addresses: $0020 to $005F
 Followed by extended I/O space, addresses $0060 to $00FF

AVR Memory Organization:

Data Memory
Address Register Address Register
I/O Registers (SFRs): Mem. I/O Name Address Register Mem. I/O Name
$20 $00 Reserved Mem. I/O Name $4C $2C SPCR
 each register has a memory address and a corresponding $21 $01 Reserved $4D $2D SPSR
I/O address $22 $02 Reserved $36 $16 TIFR1 $4E $2E SPDR
$23 $03 PINB $4F $2F Reserved
 In AVR, 8 flags are grouped in the Status Register $24 $04 DDRB $37 $17 TIFR2 $50 $30 ACSR
(SREG) located at address $005F of the Data Memory. $25 $05 PORTB
$38 $18 Reserved
$51 $31 Reserved
$26 $06 PINC $52 $32 Reserved
 Flags are special signals that indicate the outcomes of the $27 $07 DDRC $39 $19 Reserved
executed arithmetic or logic instruction $28 $08 PORTC $53 $33 SMCR
$29 $09 PIND $3A $1A Reserved $54 $34 MCUSR
$2A $0A DDRD $55 $35 MCUCR
$2B $0B PORTD $3B $1B PCIFR $56 $36 Reserved
$2C $0C Reserved $3C $1C EIFR $57 $37 SPMCSR
$2D $0D Reserved $58 $38 Reserved
$2E $0E Reserved $3D $1D EIMSK $59 $39 Reserved
$2F $0F Reserved $5A $3A Reserved
$3E $1E GPIOR0
I – Global Interrupt Enable V – Overflow Flag $30 $10 Reserved $5B $3B Reserved
$31 $11 Reserved $5C $3C Reserved
T – Bit Copy Storage N – Negative Flag $32 $12 Reserved
$3F $1F EECR
$5D $3D SPL
H – Half-Carry Flag Z – Zero Flag $33 $13 Reserved $40 $20 EEDR $5E $3E SPH
S – Sign Flag C – Carry Flag $34 $14 Reserved $5F $3F SREG
$35 $15 TIFR0 $41 $21 EEARL 6

I T H S V N Z C

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AVR Memory Organization:

Data Memory
 Internal SRAM
 Addresses: $0100 to $08FF
 Store any data needed by the programmer
 Internal SRAM is volatile (it will be cleared if the power is disconnected)

 External SRAM
 Addresses: $0900 to $FFFF
 can be used to expand the memory using an external memory chip

 EEPROM
 Can be used to store system settings and other data required to remain after power is disconnected

AVR Memory Organization:

Data Memory
 Data Memory Bus
 The CPU communicates with Data Memory using Data Memory Bus.
 Data Memory Bus contains:
 Data Memory Address Bus: 16-bits (16 lines) , one way bus from CPU to Data Memory.
 Data Memory Data Bus: 8-bits wide (8 lines) , bidirectional since it moves a whole data byte between
the memory and CPU (Parallel Transfer) in both directions.
 Data Memory Control Bus: activate memory elements and selects the direction of data transfer.

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AVR Memory Organization:

Program Memory
 Separate memory space to store program (code)
 It is a Flash ROM memory. Hence, it will retain the program even after turning off the
microcontroller.
In Atmega328, the Program Memory size is 32KB, organized as 16 x 1024 memory locations,
each of size 2 Bytes.
 In AVR, each location (2 Bytes) in program memory is called a Word.
 Program Memory Bus
 used by the CPU to fetch (read) The instructions from the Program Memory
 Program Memory Address Bus: (14 bits in Atmega328). Program Memory size of Atmega328 is 4MB
 Program Memory Data Bus: (16 bits) for moving the content (the needed instruction) of the program
memory location specified by the address bus to the Instruction Decoder in the CPU.

AVR System Architecture

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